Switch.hh revision 9302:c2e70a9bc340
13558SN/A/* 23558SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 33558SN/A * All rights reserved. 43558SN/A * 53558SN/A * Redistribution and use in source and binary forms, with or without 63558SN/A * modification, are permitted provided that the following conditions are 73558SN/A * met: redistributions of source code must retain the above copyright 83558SN/A * notice, this list of conditions and the following disclaimer; 93558SN/A * redistributions in binary form must reproduce the above copyright 103558SN/A * notice, this list of conditions and the following disclaimer in the 113558SN/A * documentation and/or other materials provided with the distribution; 123558SN/A * neither the name of the copyright holders nor the names of its 133558SN/A * contributors may be used to endorse or promote products derived from 143558SN/A * this software without specific prior written permission. 153558SN/A * 163558SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173558SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183558SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193558SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203558SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213558SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223558SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233558SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243558SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253558SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263558SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273558SN/A */ 283558SN/A 293558SN/A/* 303558SN/A * The actual modelled switch. It use the perfect switch and a 3111793Sbrandon.potter@amd.com * Throttle object to control and bandwidth and timing *only for the 3211793Sbrandon.potter@amd.com * output port*. So here we have un-realistic modelling, since the 333558SN/A * order of PerfectSwitch and Throttle objects get woke up affect the 343558SN/A * message timing. A more accurate model would be having two set of 356757SAli.Saidi@ARM.com * system states, one for this cycle, one for next cycle. And on the 366757SAli.Saidi@ARM.com * cycle boundary swap the two set of states. 373558SN/A */ 383558SN/A 393558SN/A#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 403558SN/A#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 418706Sandreas.hansson@arm.com 423558SN/A#include <iostream> 433558SN/A#include <vector> 446757SAli.Saidi@ARM.com 453570SN/A#include "mem/ruby/network/BasicRouter.hh" 463558SN/A#include "params/Switch.hh" 4713887Sgabeblack@google.com 4813887Sgabeblack@google.comclass MessageBuffer; 4913887Sgabeblack@google.comclass PerfectSwitch; 5013887Sgabeblack@google.comclass NetDest; 513558SN/Aclass SimpleNetwork; 5213887Sgabeblack@google.comclass Throttle; 533558SN/A 5413887Sgabeblack@google.comclass Switch : public BasicRouter 5513887Sgabeblack@google.com{ 5613887Sgabeblack@google.com public: 5713887Sgabeblack@google.com typedef SwitchParams Params; 5813887Sgabeblack@google.com Switch(const Params *p); 593558SN/A ~Switch(); 6013887Sgabeblack@google.com 6113887Sgabeblack@google.com void init(); 6213887Sgabeblack@google.com void addInPort(const std::vector<MessageBuffer*>& in); 6313887Sgabeblack@google.com void addOutPort(const std::vector<MessageBuffer*>& out, 6413887Sgabeblack@google.com const NetDest& routing_table_entry, int link_latency, 653558SN/A int bw_multiplier); 6613887Sgabeblack@google.com const Throttle* getThrottle(LinkID link_number) const; 6713887Sgabeblack@google.com const std::vector<Throttle*>* getThrottles() const; 6813887Sgabeblack@google.com void clearRoutingTables(); 6913887Sgabeblack@google.com void clearBuffers(); 7013887Sgabeblack@google.com void reconfigureOutPort(const NetDest& routing_table_entry); 713558SN/A 7213887Sgabeblack@google.com void printStats(std::ostream& out) const; 7313887Sgabeblack@google.com void clearStats(); 7413887Sgabeblack@google.com void print(std::ostream& out) const; 753558SN/A void init_net_ptr(SimpleNetwork* net_ptr) { m_network_ptr = net_ptr; } 7613887Sgabeblack@google.com 773558SN/A bool functionalRead(Packet *); 7813887Sgabeblack@google.com uint32_t functionalWrite(Packet *); 7913887Sgabeblack@google.com 8013887Sgabeblack@google.com private: 8113887Sgabeblack@google.com // Private copy constructor and assignment operator 8213887Sgabeblack@google.com Switch(const Switch& obj); 8313887Sgabeblack@google.com Switch& operator=(const Switch& obj); 849069Satgutier@umich.edu 8513887Sgabeblack@google.com PerfectSwitch* m_perfect_switch_ptr; 8613887Sgabeblack@google.com SimpleNetwork* m_network_ptr; 8713887Sgabeblack@google.com std::vector<Throttle*> m_throttles; 8813887Sgabeblack@google.com std::vector<MessageBuffer*> m_buffers_to_free; 8913887Sgabeblack@google.com}; 9013887Sgabeblack@google.com 919069Satgutier@umich.eduinline std::ostream& 9213887Sgabeblack@google.comoperator<<(std::ostream& out, const Switch& obj) 939069Satgutier@umich.edu{ 9413887Sgabeblack@google.com obj.print(out); 9513887Sgabeblack@google.com out << std::flush; 963558SN/A return out; 9713887Sgabeblack@google.com} 9813887Sgabeblack@google.com 999069Satgutier@umich.edu#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 10013887Sgabeblack@google.com