Switch.hh revision 8259 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The actual modelled switch. It use the perfect switch and a
31 * Throttle object to control and bandwidth and timing *only for the
32 * output port*. So here we have un-realistic modelling, since the
33 * order of PerfectSwitch and Throttle objects get woke up affect the
34 * message timing. A more accurate model would be having two set of
35 * system states, one for this cycle, one for next cycle. And on the
36 * cycle boundary swap the two set of states.
37 */
38
39#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
40#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
41
42#include <iostream>
43#include <vector>
44
45#include "mem/ruby/common/Global.hh"
46
47class MessageBuffer;
48class PerfectSwitch;
49class NetDest;
50class SimpleNetwork;
51class Throttle;
52
53class Switch
54{
55  public:
56    Switch(SwitchID sid, SimpleNetwork* network_ptr);
57    ~Switch();
58
59    void addInPort(const std::vector<MessageBuffer*>& in);
60    void addOutPort(const std::vector<MessageBuffer*>& out,
61        const NetDest& routing_table_entry, int link_latency,
62        int bw_multiplier);
63    const Throttle* getThrottle(LinkID link_number) const;
64    const std::vector<Throttle*>* getThrottles() const;
65    void clearRoutingTables();
66    void clearBuffers();
67    void reconfigureOutPort(const NetDest& routing_table_entry);
68
69    void printStats(std::ostream& out) const;
70    void clearStats();
71    void printConfig(std::ostream& out) const;
72
73    void print(std::ostream& out) const;
74
75  private:
76    // Private copy constructor and assignment operator
77    Switch(const Switch& obj);
78    Switch& operator=(const Switch& obj);
79
80    PerfectSwitch* m_perfect_switch_ptr;
81    SimpleNetwork* m_network_ptr;
82    std::vector<Throttle*> m_throttles;
83    std::vector<MessageBuffer*> m_buffers_to_free;
84    SwitchID m_switch_id;
85};
86
87inline std::ostream&
88operator<<(std::ostream& out, const Switch& obj)
89{
90    obj.print(out);
91    out << std::flush;
92    return out;
93}
94
95#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
96