Switch.hh revision 7002:48a19d52d939
1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * $Id$ 32 * 33 * Description: The actual modelled switch. It use the perfect switch and a 34 * Throttle object to control and bandwidth and timing *only for 35 * the output port*. So here we have un-realistic modelling, 36 * since the order of PerfectSwitch and Throttle objects get 37 * woke up affect the message timing. A more accurate model would 38 * be having two set of system states, one for this cycle, one for 39 * next cycle. And on the cycle boundary swap the two set of 40 * states. 41 * 42 */ 43 44#ifndef Switch_H 45#define Switch_H 46 47#include <iostream> 48 49#include "mem/ruby/common/Global.hh" 50#include "mem/gems_common/Vector.hh" 51 52class MessageBuffer; 53class PerfectSwitch; 54class NetDest; 55class SimpleNetwork; 56class Throttle; 57class Network; 58 59class Switch { 60public: 61 // Constructors 62 63 // constructor specifying the number of ports 64 Switch(SwitchID sid, SimpleNetwork* network_ptr); 65 void addInPort(const Vector<MessageBuffer*>& in); 66 void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry, int link_latency, int bw_multiplier); 67 const Throttle* getThrottle(LinkID link_number) const; 68 const Vector<Throttle*>* getThrottles() const; 69 void clearRoutingTables(); 70 void clearBuffers(); 71 void reconfigureOutPort(const NetDest& routing_table_entry); 72 73 void printStats(std::ostream& out) const; 74 void clearStats(); 75 void printConfig(std::ostream& out) const; 76 77 // Destructor 78 ~Switch(); 79 80 void print(std::ostream& out) const; 81private: 82 83 // Private copy constructor and assignment operator 84 Switch(const Switch& obj); 85 Switch& operator=(const Switch& obj); 86 87 // Data Members (m_ prefix) 88 PerfectSwitch* m_perfect_switch_ptr; 89 Network* m_network_ptr; 90 Vector<Throttle*> m_throttles; 91 Vector<MessageBuffer*> m_buffers_to_free; 92 SwitchID m_switch_id; 93}; 94 95// Output operator declaration 96std::ostream& operator<<(std::ostream& out, const Switch& obj); 97 98// ******************* Definitions ******************* 99 100// Output operator definition 101extern inline 102std::ostream& operator<<(std::ostream& out, const Switch& obj) 103{ 104 obj.print(out); 105 out << std::flush; 106 return out; 107} 108 109#endif //Switch_H 110