Switch.hh revision 10311:ad9c042dce54
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * The actual modelled switch. It use the perfect switch and a 31 * Throttle object to control and bandwidth and timing *only for the 32 * output port*. So here we have un-realistic modelling, since the 33 * order of PerfectSwitch and Throttle objects get woke up affect the 34 * message timing. A more accurate model would be having two set of 35 * system states, one for this cycle, one for next cycle. And on the 36 * cycle boundary swap the two set of states. 37 */ 38 39#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 40#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 41 42#include <iostream> 43#include <vector> 44 45#include "mem/packet.hh" 46#include "mem/protocol/MessageSizeType.hh" 47#include "mem/ruby/common/TypeDefines.hh" 48#include "mem/ruby/network/BasicRouter.hh" 49#include "params/Switch.hh" 50 51class MessageBuffer; 52class PerfectSwitch; 53class NetDest; 54class SimpleNetwork; 55class Throttle; 56 57class Switch : public BasicRouter 58{ 59 public: 60 typedef SwitchParams Params; 61 Switch(const Params *p); 62 ~Switch(); 63 void init(); 64 65 void addInPort(const std::map<int, MessageBuffer*>& in); 66 void addOutPort(const std::map<int, MessageBuffer*>& out, 67 const NetDest& routing_table_entry, 68 Cycles link_latency, int bw_multiplier); 69 70 const Throttle* getThrottle(LinkID link_number) const; 71 72 void resetStats(); 73 void collateStats(); 74 void regStats(); 75 const Stats::Formula & getMsgCount(unsigned int type) const 76 { return m_msg_counts[type]; } 77 78 void print(std::ostream& out) const; 79 void init_net_ptr(SimpleNetwork* net_ptr) { m_network_ptr = net_ptr; } 80 81 bool functionalRead(Packet *); 82 uint32_t functionalWrite(Packet *); 83 84 private: 85 // Private copy constructor and assignment operator 86 Switch(const Switch& obj); 87 Switch& operator=(const Switch& obj); 88 89 PerfectSwitch* m_perfect_switch; 90 SimpleNetwork* m_network_ptr; 91 std::vector<Throttle*> m_throttles; 92 std::vector<MessageBuffer*> m_buffers_to_free; 93 94 // Statistical variables 95 Stats::Formula m_avg_utilization; 96 Stats::Formula m_msg_counts[MessageSizeType_NUM]; 97 Stats::Formula m_msg_bytes[MessageSizeType_NUM]; 98}; 99 100inline std::ostream& 101operator<<(std::ostream& out, const Switch& obj) 102{ 103 obj.print(out); 104 out << std::flush; 105 return out; 106} 107 108#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 109