Switch.cc revision 11111:6da33e720481 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <numeric>
30
31#include "base/cast.hh"
32#include "base/stl_helpers.hh"
33#include "mem/ruby/network/MessageBuffer.hh"
34#include "mem/ruby/network/simple/PerfectSwitch.hh"
35#include "mem/ruby/network/simple/SimpleNetwork.hh"
36#include "mem/ruby/network/simple/Switch.hh"
37#include "mem/ruby/network/simple/Throttle.hh"
38
39using namespace std;
40using m5::stl_helpers::deletePointers;
41using m5::stl_helpers::operator<<;
42
43Switch::Switch(const Params *p) : BasicRouter(p)
44{
45    m_perfect_switch = new PerfectSwitch(m_id, this, p->virt_nets);
46    m_port_buffers = p->port_buffers;
47    m_num_connected_buffers = 0;
48}
49
50Switch::~Switch()
51{
52    delete m_perfect_switch;
53
54    // Delete throttles (one per output port)
55    deletePointers(m_throttles);
56
57    // Delete MessageBuffers
58    deletePointers(m_port_buffers);
59}
60
61void
62Switch::init()
63{
64    BasicRouter::init();
65    m_perfect_switch->init(m_network_ptr);
66}
67
68void
69Switch::addInPort(const vector<MessageBuffer*>& in)
70{
71    m_perfect_switch->addInPort(in);
72}
73
74void
75Switch::addOutPort(const vector<MessageBuffer*>& out,
76                   const NetDest& routing_table_entry,
77                   Cycles link_latency, int bw_multiplier)
78{
79    // Create a throttle
80    RubySystem *rs = m_network_ptr->params()->ruby_system;
81    Throttle* throttle_ptr = new Throttle(m_id, rs, m_throttles.size(),
82                                          link_latency, bw_multiplier,
83                                          m_network_ptr->getEndpointBandwidth(),
84                                          this);
85
86    m_throttles.push_back(throttle_ptr);
87
88    // Create one buffer per vnet (these are intermediaryQueues)
89    vector<MessageBuffer*> intermediateBuffers;
90
91    for (int i = 0; i < out.size(); ++i) {
92        assert(m_num_connected_buffers < m_port_buffers.size());
93        MessageBuffer* buffer_ptr = m_port_buffers[m_num_connected_buffers];
94        m_num_connected_buffers++;
95        intermediateBuffers.push_back(buffer_ptr);
96    }
97
98    // Hook the queues to the PerfectSwitch
99    m_perfect_switch->addOutPort(intermediateBuffers, routing_table_entry);
100
101    // Hook the queues to the Throttle
102    throttle_ptr->addLinks(intermediateBuffers, out);
103}
104
105const Throttle*
106Switch::getThrottle(LinkID link_number) const
107{
108    assert(m_throttles[link_number] != NULL);
109    return m_throttles[link_number];
110}
111
112void
113Switch::regStats()
114{
115    for (int link = 0; link < m_throttles.size(); link++) {
116        m_throttles[link]->regStats(name());
117    }
118
119    m_avg_utilization.name(name() + ".percent_links_utilized");
120    for (unsigned int i = 0; i < m_throttles.size(); i++) {
121        m_avg_utilization += m_throttles[i]->getUtilization();
122    }
123    m_avg_utilization /= Stats::constant(m_throttles.size());
124
125    for (unsigned int type = MessageSizeType_FIRST;
126         type < MessageSizeType_NUM; ++type) {
127        m_msg_counts[type]
128            .name(name() + ".msg_count." +
129                MessageSizeType_to_string(MessageSizeType(type)))
130            .flags(Stats::nozero)
131            ;
132        m_msg_bytes[type]
133            .name(name() + ".msg_bytes." +
134                MessageSizeType_to_string(MessageSizeType(type)))
135            .flags(Stats::nozero)
136            ;
137
138        for (unsigned int i = 0; i < m_throttles.size(); i++) {
139            m_msg_counts[type] += m_throttles[i]->getMsgCount(type);
140        }
141        m_msg_bytes[type] = m_msg_counts[type] * Stats::constant(
142                Network::MessageSizeType_to_int(MessageSizeType(type)));
143    }
144}
145
146void
147Switch::resetStats()
148{
149    m_perfect_switch->clearStats();
150    for (int i = 0; i < m_throttles.size(); i++) {
151        m_throttles[i]->clearStats();
152    }
153}
154
155void
156Switch::collateStats()
157{
158    m_perfect_switch->collateStats();
159    for (int i = 0; i < m_throttles.size(); i++) {
160        m_throttles[i]->collateStats();
161    }
162}
163
164void
165Switch::print(std::ostream& out) const
166{
167    // FIXME printing
168    out << "[Switch]";
169}
170
171bool
172Switch::functionalRead(Packet *pkt)
173{
174    // Access the buffers in the switch for performing a functional read
175    for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
176        if (m_port_buffers[i]->functionalRead(pkt)) {
177            return true;
178        }
179    }
180    return false;
181}
182
183uint32_t
184Switch::functionalWrite(Packet *pkt)
185{
186    // Access the buffers in the switch for performing a functional write
187    uint32_t num_functional_writes = 0;
188    for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
189        num_functional_writes += m_port_buffers[i]->functionalWrite(pkt);
190    }
191    return num_functional_writes;
192}
193
194Switch *
195SwitchParams::create()
196{
197    return new Switch(this);
198}
199