SimpleNetwork.py revision 11021:e8a6637afa4c
12934Sktlim@umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 22934Sktlim@umich.edu# All rights reserved. 32934Sktlim@umich.edu# 42934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132934Sktlim@umich.edu# this software without specific prior written permission. 142934Sktlim@umich.edu# 152934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# Authors: Steve Reinhardt 282934Sktlim@umich.edu# Brad Beckmann 292934Sktlim@umich.edu 302969Sktlim@umich.edufrom m5.params import * 312934Sktlim@umich.edufrom m5.proxy import * 322934Sktlim@umich.edufrom Network import RubyNetwork 332934Sktlim@umich.edufrom BasicRouter import BasicRouter 342934Sktlim@umich.edufrom MessageBuffer import MessageBuffer 352934Sktlim@umich.edu 362934Sktlim@umich.educlass SimpleNetwork(RubyNetwork): 372934Sktlim@umich.edu type = 'SimpleNetwork' 382934Sktlim@umich.edu cxx_header = "mem/ruby/network/simple/SimpleNetwork.hh" 392934Sktlim@umich.edu buffer_size = Param.Int(0, 402934Sktlim@umich.edu "default buffer size; 0 indicates infinite buffering"); 412934Sktlim@umich.edu endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor"); 422934Sktlim@umich.edu adaptive_routing = Param.Bool(False, "enable adaptive routing"); 432934Sktlim@umich.edu int_link_buffers = VectorParam.MessageBuffer("Buffers for int_links") 442934Sktlim@umich.edu # int_links do not recycle buffers, so this parameter is not used. 452934Sktlim@umich.edu # TODO: Move recycle_latency out of MessageBuffers and into controllers 462934Sktlim@umich.edu recycle_latency = Param.Cycles(0, "") 472934Sktlim@umich.edu 482934Sktlim@umich.edu def setup_buffers(self): 492934Sktlim@umich.edu # Note that all SimpleNetwork MessageBuffers are currently ordered 502934Sktlim@umich.edu network_buffers = [] 512934Sktlim@umich.edu for link in self.int_links: 522934Sktlim@umich.edu # The network needs number_of_virtual_networks buffers per 532969Sktlim@umich.edu # int_link port 542934Sktlim@umich.edu for i in xrange(self.number_of_virtual_networks): 552934Sktlim@umich.edu network_buffers.append(MessageBuffer(ordered = True)) 562934Sktlim@umich.edu network_buffers.append(MessageBuffer(ordered = True)) 572934Sktlim@umich.edu self.int_link_buffers = network_buffers 582934Sktlim@umich.edu 592934Sktlim@umich.edu # Also add buffers for all router-link connections 602934Sktlim@umich.edu for router in self.routers: 612934Sktlim@umich.edu router_buffers = [] 622934Sktlim@umich.edu # Add message buffers to routers for each internal link connection 632934Sktlim@umich.edu for link in self.int_links: 642934Sktlim@umich.edu if link.node_a == router: 652934Sktlim@umich.edu for i in xrange(self.number_of_virtual_networks): 662934Sktlim@umich.edu router_buffers.append(MessageBuffer(ordered = True)) 672934Sktlim@umich.edu if link.node_b == router: 682934Sktlim@umich.edu for i in xrange(self.number_of_virtual_networks): 692934Sktlim@umich.edu router_buffers.append(MessageBuffer(ordered = True)) 702934Sktlim@umich.edu 712934Sktlim@umich.edu # Add message buffers to routers for each external link connection 722934Sktlim@umich.edu for link in self.ext_links: 732934Sktlim@umich.edu # Routers can only be int_nodes on ext_links 742934Sktlim@umich.edu if link.int_node in self.routers: 752934Sktlim@umich.edu for i in xrange(self.number_of_virtual_networks): 762934Sktlim@umich.edu router_buffers.append(MessageBuffer(ordered = True)) 772934Sktlim@umich.edu router.port_buffers = router_buffers 782953Sktlim@umich.edu 792934Sktlim@umich.educlass Switch(BasicRouter): 802969Sktlim@umich.edu type = 'Switch' 812934Sktlim@umich.edu cxx_header = 'mem/ruby/network/simple/Switch.hh' 822934Sktlim@umich.edu virt_nets = Param.Int(Parent.number_of_virtual_networks, 832934Sktlim@umich.edu "number of virtual networks") 842934Sktlim@umich.edu port_buffers = VectorParam.MessageBuffer("Port buffers") 852934Sktlim@umich.edu # Ports do not recycle buffers, so this parameter is not used. 862934Sktlim@umich.edu # TODO: Move recycle_latency out of MessageBuffers and into controllers 872934Sktlim@umich.edu recycle_latency = Param.Cycles(0, "") 882934Sktlim@umich.edu