SimpleNetwork.hh revision 7454 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The SimpleNetwork class implements the interconnection
31 * SimpleNetwork between components (processor/cache components and
32 * memory/directory components).  The interconnection network as
33 * described here is not a physical network, but a programming concept
34 * used to implement all communication between components.  Thus parts
35 * of this 'network' may model the on-chip connections between cache
36 * controllers and directory controllers as well as the links between
37 * chip and network switches.
38 *
39 * Two conceptual networks, an address and data network, are modeled.
40 * The data network is unordered, where the address network provides
41 * and conforms to a global ordering of all transactions.
42 *
43 * Currently the data network is point-to-point and the address
44 * network is a broadcast network. These two distinct conceptual
45 * network can be modeled as physically separate networks or
46 * multiplexed over a single physical network.
47 *
48 * The network encapsulates all notion of virtual global time and is
49 * responsible for ordering the network transactions received.  This
50 * hides all of these ordering details from the processor/cache and
51 * directory/memory modules.
52 *
53 * FIXME: Various flavor of networks are provided as a compiler time
54 *        configurable. We currently include this SimpleNetwork in the
55 *        makefile's vpath, so that SimpleNetwork.cc can provide an alternative
56 *        version constructor for the abstract Network class. It is easy to
57 *        modify this to make network a runtime configuable. Just make the
58 *        abstract Network class take a enumeration parameter, and based on
59 *        that to initial proper network. Or even better, just make the ruby
60 *        system initializer choose the proper network to initiate.
61 */
62
63#ifndef __MEM_RUBY_NETWORK_SIMPLE_SIMPLENETWORK_HH__
64#define __MEM_RUBY_NETWORK_SIMPLE_SIMPLENETWORK_HH__
65
66#include <iostream>
67#include <vector>
68
69#include "mem/ruby/common/Global.hh"
70#include "mem/ruby/network/Network.hh"
71#include "mem/ruby/system/NodeID.hh"
72#include "params/SimpleNetwork.hh"
73#include "sim/sim_object.hh"
74
75class NetDest;
76class MessageBuffer;
77class Throttle;
78class Switch;
79class Topology;
80
81class SimpleNetwork : public Network
82{
83  public:
84    typedef SimpleNetworkParams Params;
85    SimpleNetwork(const Params *p);
86    ~SimpleNetwork();
87
88    void init();
89
90    void printStats(std::ostream& out) const;
91    void clearStats();
92    void printConfig(std::ostream& out) const;
93
94    void reset();
95
96    // returns the queue requested for the given component
97    MessageBuffer* getToNetQueue(NodeID id, bool ordered, int network_num);
98    MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int network_num);
99    virtual const std::vector<Throttle*>* getThrottles(NodeID id) const;
100
101    bool isVNetOrdered(int vnet) { return m_ordered[vnet]; }
102    bool validVirtualNetwork(int vnet) { return m_in_use[vnet]; }
103
104    int getNumNodes() {return m_nodes; }
105
106    // Methods used by Topology to setup the network
107    void makeOutLink(SwitchID src, NodeID dest,
108        const NetDest& routing_table_entry, int link_latency, int link_weight,
109        int bw_multiplier, bool isReconfiguration);
110    void makeInLink(SwitchID src, NodeID dest,
111        const NetDest& routing_table_entry, int link_latency,
112        int bw_multiplier, bool isReconfiguration);
113    void makeInternalLink(SwitchID src, NodeID dest,
114        const NetDest& routing_table_entry, int link_latency, int link_weight,
115        int bw_multiplier, bool isReconfiguration);
116
117    void print(std::ostream& out) const;
118
119  private:
120    void checkNetworkAllocation(NodeID id, bool ordered, int network_num);
121    void addLink(SwitchID src, SwitchID dest, int link_latency);
122    void makeLink(SwitchID src, SwitchID dest,
123        const NetDest& routing_table_entry, int link_latency);
124    SwitchID createSwitch();
125    void makeTopology();
126    void linkTopology();
127
128    // Private copy constructor and assignment operator
129    SimpleNetwork(const SimpleNetwork& obj);
130    SimpleNetwork& operator=(const SimpleNetwork& obj);
131
132    // vector of queues from the components
133    std::vector<std::vector<MessageBuffer*> > m_toNetQueues;
134    std::vector<std::vector<MessageBuffer*> > m_fromNetQueues;
135
136    std::vector<bool> m_in_use;
137    std::vector<bool> m_ordered;
138    std::vector<Switch*> m_switch_ptr_vector;
139    std::vector<MessageBuffer*> m_buffers_to_free;
140    std::vector<Switch*> m_endpoint_switches;
141};
142
143inline std::ostream&
144operator<<(std::ostream& out, const SimpleNetwork& obj)
145{
146    obj.print(out);
147    out << std::flush;
148    return out;
149}
150
151#endif // __MEM_RUBY_NETWORK_SIMPLE_SIMPLENETWORK_HH__
152