SimpleLink.hh revision 6493 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * Network.hh
32 *
33 * Description: The Network class is the base class for classes that
34 * implement the interconnection network between components
35 * (processor/cache components and memory/directory components).  The
36 * interconnection network as described here is not a physical
37 * network, but a programming concept used to implement all
38 * communication between components.  Thus parts of this 'network'
39 * will model the on-chip connections between cache controllers and
40 * directory controllers as well as the links between chip and network
41 * switches.
42 *
43 * $Id$
44 * */
45
46#ifndef NETWORK_H
47#define NETWORK_H
48
49#include "mem/ruby/common/Global.hh"
50#include "mem/ruby/system/NodeID.hh"
51#include "mem/protocol/MessageSizeType.hh"
52#include "mem/ruby/system/System.hh"
53
54class NetDest;
55class MessageBuffer;
56class Throttle;
57class Topology;
58
59class Network {
60public:
61  // Constructors
62  Network(const string & name);
63  virtual void init(const vector<string> & argv);
64
65  // Destructor
66  virtual ~Network() {}
67
68  // Public Methods
69  int getBufferSize() { return m_buffer_size; }
70  int getNumberOfVirtualNetworks() { return m_virtual_networks; }
71  int getEndpointBandwidth() { return m_endpoint_bandwidth; }
72  bool getAdaptiveRouting() {return m_adaptive_routing; }
73  int getLinkLatency() { return m_link_latency; }
74  int MessageSizeType_to_int(MessageSizeType size_type);
75
76
77  // returns the queue requested for the given component
78  virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered, int netNumber) = 0;
79  virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int netNumber) = 0;
80  virtual const Vector<Throttle*>* getThrottles(NodeID id) const { return NULL; }
81
82  virtual int getNumNodes() {return 1;}
83
84  virtual void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) = 0;
85  virtual void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration) = 0;
86  virtual void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) = 0;
87
88  virtual void reset() = 0;
89
90  virtual void printStats(ostream& out) const = 0;
91  virtual void clearStats() = 0;
92  virtual void printConfig(ostream& out) const = 0;
93  virtual void print(ostream& out) const = 0;
94
95protected:
96
97  // Private Methods
98  // Private copy constructor and assignment operator
99  Network(const Network& obj);
100  Network& operator=(const Network& obj);
101
102  // Data Members (m_ prefix)
103protected:
104  const string m_name;
105  int m_nodes;
106  int m_virtual_networks;
107  int m_buffer_size;
108  int m_endpoint_bandwidth;
109  Topology* m_topology_ptr;
110  bool m_adaptive_routing;
111  int m_link_latency;
112  int m_control_msg_size;
113  int m_data_msg_size;
114};
115
116// Output operator declaration
117ostream& operator<<(ostream& out, const Network& obj);
118
119// ******************* Definitions *******************
120
121// Output operator definition
122extern inline
123ostream& operator<<(ostream& out, const Network& obj)
124{
125  obj.print(out);
126  out << flush;
127  return out;
128}
129
130#endif //NETWORK_H
131