Topology.hh revision 6879 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * Topology.hh
32 *
33 * Description: The topology here is configurable; it can be a hierachical
34 *              (default one) or a 2D torus or a 2D torus with half switches
35 *              killed. I think all input port has a
36 *              one-input-one-output switch connected just to control and
37 *              bandwidth, since we don't control bandwidth on input ports.
38 *              Basically, the class has a vector of nodes and edges. First
39 *              2*m_nodes elements in the node vector are input and output
40 *              ports. Edges are represented in two vectors of src and dest
41 *              nodes. All edges have latency.
42 *
43 * $Id$
44 *
45 * */
46
47#ifndef TOPOLOGY_H
48#define TOPOLOGY_H
49
50#include "mem/ruby/common/Global.hh"
51#include "mem/gems_common/Vector.hh"
52#include "mem/ruby/system/NodeID.hh"
53#include "sim/sim_object.hh"
54#include "params/Topology.hh"
55#include "params/Link.hh"
56#include "params/ExtLink.hh"
57#include "params/IntLink.hh"
58
59class Network;
60class NetDest;
61
62typedef Vector < Vector <int> > Matrix;
63
64class Link : public SimObject {
65  public:
66    typedef LinkParams Params;
67    Link(const Params *p) : SimObject(p) {}
68    const Params *params() const { return (const Params *)_params; }
69};
70
71
72class ExtLink : public Link {
73  public:
74    typedef ExtLinkParams Params;
75    ExtLink(const Params *p) : Link(p) {}
76    const Params *params() const { return (const Params *)_params; }
77};
78
79
80class IntLink : public Link {
81  public:
82    typedef IntLinkParams Params;
83    IntLink(const Params *p) : Link(p) {}
84    const Params *params() const { return (const Params *)_params; }
85};
86
87
88class Topology : public SimObject {
89public:
90  // Constructors
91    typedef TopologyParams Params;
92    Topology(const Params *p);
93    const Params *params() const { return (const Params *)_params; }
94
95  // Destructor
96  virtual ~Topology() {}
97
98  virtual void init();
99
100  // Public Methods
101  void makeTopology();
102  int numSwitches() const { return m_number_of_switches; }
103  void createLinks(Network *net, bool isReconfiguration);
104
105  const string getName() { return m_name; }
106  void printStats(ostream& out) const {}
107  void clearStats() {}
108  void printConfig(ostream& out) const;
109  void print(ostream& out) const { out << "[Topology]"; }
110
111protected:
112  // Private Methods
113  SwitchID newSwitchID();
114  void addLink(SwitchID src, SwitchID dest, int link_latency);
115  void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier);
116  void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier, int link_weight);
117  void makeLink(Network *net, SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int weight, int bw_multiplier, bool isReconfiguration);
118
119  //  void makeSwitchesPerChip(Vector< Vector < SwitchID > > &nodePairs, Vector<int> &latencies, Vector<int> &bw_multis, int numberOfChips);
120
121  string getDesignStr();
122  // Private copy constructor and assignment operator
123  Topology(const Topology& obj);
124  Topology& operator=(const Topology& obj);
125
126  // Data Members (m_ prefix)
127  string m_name;
128  bool m_print_config;
129  NodeID m_nodes;
130  int m_number_of_switches;
131
132  Vector<SwitchID> m_links_src_vector;
133  Vector<SwitchID> m_links_dest_vector;
134  Vector<int> m_links_latency_vector;
135  Vector<int> m_links_weight_vector;
136  Vector<int> m_bw_multiplier_vector;
137
138  Matrix m_component_latencies;
139  Matrix m_component_inter_switches;
140};
141
142// Output operator declaration
143ostream& operator<<(ostream& out, const Topology& obj);
144
145// ******************* Definitions *******************
146
147// Output operator definition
148extern inline
149ostream& operator<<(ostream& out, const Topology& obj)
150{
151  obj.print(out);
152  out << flush;
153  return out;
154}
155
156#endif
157