Topology.hh revision 6145 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * Topology.h
32 *
33 * Description: The topology here is configurable; it can be a hierachical
34 *              (default one) or a 2D torus or a 2D torus with half switches
35 *              killed. I think all input port has a
36 *              one-input-one-output switch connected just to control and
37 *              bandwidth, since we don't control bandwidth on input ports.
38 *              Basically, the class has a vector of nodes and edges. First
39 *              2*m_nodes elements in the node vector are input and output
40 *              ports. Edges are represented in two vectors of src and dest
41 *              nodes. All edges have latency.
42 *
43 * $Id$
44 *
45 * */
46
47#ifndef TOPOLOGY_H
48#define TOPOLOGY_H
49
50#include "Global.hh"
51#include "Vector.hh"
52#include "NodeID.hh"
53
54class Network;
55class NetDest;
56
57typedef Vector < Vector <int> > Matrix;
58
59class Topology {
60public:
61  // Constructors
62  Topology(Network* network_ptr, int number_of_nodes);
63
64  // Destructor
65  ~Topology() {}
66
67  // Public Methods
68  int numSwitches() const { return m_number_of_switches; }
69  void createLinks(bool isReconfiguration);
70
71  void printStats(ostream& out) const {}
72  void clearStats() {}
73  void printConfig(ostream& out) const;
74  void print(ostream& out) const { out << "[Topology]"; }
75
76private:
77  // Private Methods
78  void init();
79  SwitchID newSwitchID();
80  void addLink(SwitchID src, SwitchID dest, int link_latency);
81  void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier);
82  void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier, int link_weight);
83  void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int weight, int bw_multiplier, bool isReconfiguration);
84
85  void makeHierarchicalSwitch(int fan_out_degree);
86  void make2DTorus();
87  void makePtToPt();
88  void makeFileSpecified();
89
90  void makeSwitchesPerChip(Vector< Vector < SwitchID > > &nodePairs, Vector<int> &latencies, Vector<int> &bw_multis, int numberOfChips);
91
92  string getDesignStr();
93  // Private copy constructor and assignment operator
94  Topology(const Topology& obj);
95  Topology& operator=(const Topology& obj);
96
97  // Data Members (m_ prefix)
98  Network* m_network_ptr;
99  NodeID m_nodes;
100  int m_number_of_switches;
101
102  Vector<SwitchID> m_links_src_vector;
103  Vector<SwitchID> m_links_dest_vector;
104  Vector<int> m_links_latency_vector;
105  Vector<int> m_links_weight_vector;
106  Vector<int> m_bw_multiplier_vector;
107
108  Matrix m_component_latencies;
109  Matrix m_component_inter_switches;
110};
111
112// Output operator declaration
113ostream& operator<<(ostream& out, const Topology& obj);
114
115// ******************* Definitions *******************
116
117// Output operator definition
118extern inline
119ostream& operator<<(ostream& out, const Topology& obj)
120{
121  obj.print(out);
122  out << flush;
123  return out;
124}
125
126#endif
127