Topology.cc revision 9356
112641Sgiacomo.travaglini@arm.com/* 212641Sgiacomo.travaglini@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 312641Sgiacomo.travaglini@arm.com * All rights reserved. 412641Sgiacomo.travaglini@arm.com * 512641Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 612641Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 712641Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 812641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 912641Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1012641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1112641Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1212641Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1312641Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1412641Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1512641Sgiacomo.travaglini@arm.com * 1612641Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712641Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812641Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912641Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012641Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112641Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212641Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312641Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412641Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512641Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612641Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712641Sgiacomo.travaglini@arm.com */ 2812641Sgiacomo.travaglini@arm.com 2912641Sgiacomo.travaglini@arm.com#include <cassert> 3012641Sgiacomo.travaglini@arm.com 3112641Sgiacomo.travaglini@arm.com#include "base/trace.hh" 3212641Sgiacomo.travaglini@arm.com#include "debug/RubyNetwork.hh" 3312641Sgiacomo.travaglini@arm.com#include "mem/protocol/MachineType.hh" 3412641Sgiacomo.travaglini@arm.com#include "mem/ruby/common/NetDest.hh" 3512641Sgiacomo.travaglini@arm.com#include "mem/ruby/network/BasicLink.hh" 3612641Sgiacomo.travaglini@arm.com#include "mem/ruby/network/Network.hh" 3712641Sgiacomo.travaglini@arm.com#include "mem/ruby/network/Topology.hh" 3812641Sgiacomo.travaglini@arm.com#include "mem/ruby/slicc_interface/AbstractController.hh" 3912641Sgiacomo.travaglini@arm.com 4012641Sgiacomo.travaglini@arm.comusing namespace std; 4112641Sgiacomo.travaglini@arm.com 4212641Sgiacomo.travaglini@arm.comconst int INFINITE_LATENCY = 10000; // Yes, this is a big hack 4312641Sgiacomo.travaglini@arm.com 4412641Sgiacomo.travaglini@arm.com// Note: In this file, we use the first 2*m_nodes SwitchIDs to 4512641Sgiacomo.travaglini@arm.com// represent the input and output endpoint links. These really are 4612641Sgiacomo.travaglini@arm.com// not 'switches', as they will not have a Switch object allocated for 4712641Sgiacomo.travaglini@arm.com// them. The first m_nodes SwitchIDs are the links into the network, 4812641Sgiacomo.travaglini@arm.com// the second m_nodes set of SwitchIDs represent the the output queues 4912641Sgiacomo.travaglini@arm.com// of the network. 5012641Sgiacomo.travaglini@arm.com 5112641Sgiacomo.travaglini@arm.com// Helper functions based on chapter 29 of Cormen et al. 5212641Sgiacomo.travaglini@arm.comvoid extend_shortest_path(Matrix& current_dist, Matrix& latencies, 5312641Sgiacomo.travaglini@arm.com Matrix& inter_switches); 5412641Sgiacomo.travaglini@arm.comMatrix shortest_path(const Matrix& weights, Matrix& latencies, 5512641Sgiacomo.travaglini@arm.com Matrix& inter_switches); 5612641Sgiacomo.travaglini@arm.combool link_is_shortest_path_to_node(SwitchID src, SwitchID next, 5712641Sgiacomo.travaglini@arm.com SwitchID final, const Matrix& weights, const Matrix& dist); 5812641Sgiacomo.travaglini@arm.comNetDest shortest_path_to_node(SwitchID src, SwitchID next, 5912641Sgiacomo.travaglini@arm.com const Matrix& weights, const Matrix& dist); 6012641Sgiacomo.travaglini@arm.com 6112641Sgiacomo.travaglini@arm.comTopology::Topology(const Params *p) 6212641Sgiacomo.travaglini@arm.com : SimObject(p) 6312641Sgiacomo.travaglini@arm.com{ 6412641Sgiacomo.travaglini@arm.com m_print_config = p->print_config; 6512641Sgiacomo.travaglini@arm.com m_number_of_switches = p->routers.size(); 6612641Sgiacomo.travaglini@arm.com 6712641Sgiacomo.travaglini@arm.com // initialize component latencies record 6812641Sgiacomo.travaglini@arm.com m_component_latencies.resize(0); 6912641Sgiacomo.travaglini@arm.com m_component_inter_switches.resize(0); 7012641Sgiacomo.travaglini@arm.com 7112641Sgiacomo.travaglini@arm.com // Total nodes/controllers in network 7212641Sgiacomo.travaglini@arm.com // Must make sure this is called after the State Machine constructors 7312641Sgiacomo.travaglini@arm.com m_nodes = MachineType_base_number(MachineType_NUM); 7412641Sgiacomo.travaglini@arm.com assert(m_nodes > 1); 7512641Sgiacomo.travaglini@arm.com 7612641Sgiacomo.travaglini@arm.com if (m_nodes != params()->ext_links.size() && 7712641Sgiacomo.travaglini@arm.com m_nodes != params()->ext_links.size()) { 7812641Sgiacomo.travaglini@arm.com fatal("m_nodes (%d) != ext_links vector length (%d)\n", 7912641Sgiacomo.travaglini@arm.com m_nodes, params()->ext_links.size()); 8012641Sgiacomo.travaglini@arm.com } 8112641Sgiacomo.travaglini@arm.com 8212641Sgiacomo.travaglini@arm.com // analyze both the internal and external links, create data structures 8312641Sgiacomo.travaglini@arm.com // Note that the python created links are bi-directional, but that the 8412641Sgiacomo.travaglini@arm.com // topology and networks utilize uni-directional links. Thus each 8512641Sgiacomo.travaglini@arm.com // BasicLink is converted to two calls to add link, on for each direction 8612641Sgiacomo.travaglini@arm.com for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin(); 8712641Sgiacomo.travaglini@arm.com i != params()->ext_links.end(); ++i) { 8813915Sgabeblack@google.com BasicExtLink *ext_link = (*i); 8912641Sgiacomo.travaglini@arm.com AbstractController *abs_cntrl = ext_link->params()->ext_node; 9012641Sgiacomo.travaglini@arm.com BasicRouter *router = ext_link->params()->int_node; 9112641Sgiacomo.travaglini@arm.com 9212641Sgiacomo.travaglini@arm.com // Store the controller and ExtLink pointers for later 9312641Sgiacomo.travaglini@arm.com m_controller_vector.push_back(abs_cntrl); 9412641Sgiacomo.travaglini@arm.com m_ext_link_vector.push_back(ext_link); 9512641Sgiacomo.travaglini@arm.com 9612641Sgiacomo.travaglini@arm.com int ext_idx1 = abs_cntrl->params()->cntrl_id; 9712641Sgiacomo.travaglini@arm.com int ext_idx2 = ext_idx1 + m_nodes; 9812641Sgiacomo.travaglini@arm.com int int_idx = router->params()->router_id + 2*m_nodes; 9912641Sgiacomo.travaglini@arm.com 10012641Sgiacomo.travaglini@arm.com // create the internal uni-directional links in both directions 10112641Sgiacomo.travaglini@arm.com // the first direction is marked: In 10212641Sgiacomo.travaglini@arm.com addLink(ext_idx1, int_idx, ext_link, LinkDirection_In); 10312641Sgiacomo.travaglini@arm.com // the first direction is marked: Out 10413915Sgabeblack@google.com addLink(int_idx, ext_idx2, ext_link, LinkDirection_Out); 10512641Sgiacomo.travaglini@arm.com } 10612641Sgiacomo.travaglini@arm.com 10712641Sgiacomo.travaglini@arm.com for (vector<BasicIntLink*>::const_iterator i = params()->int_links.begin(); 10812641Sgiacomo.travaglini@arm.com i != params()->int_links.end(); ++i) { 10912641Sgiacomo.travaglini@arm.com BasicIntLink *int_link = (*i); 11012641Sgiacomo.travaglini@arm.com BasicRouter *router_a = int_link->params()->node_a; 11112641Sgiacomo.travaglini@arm.com BasicRouter *router_b = int_link->params()->node_b; 11212641Sgiacomo.travaglini@arm.com 11312641Sgiacomo.travaglini@arm.com // Store the IntLink pointers for later 11412641Sgiacomo.travaglini@arm.com m_int_link_vector.push_back(int_link); 11512641Sgiacomo.travaglini@arm.com 11612641Sgiacomo.travaglini@arm.com int a = router_a->params()->router_id + 2*m_nodes; 11712641Sgiacomo.travaglini@arm.com int b = router_b->params()->router_id + 2*m_nodes; 11812641Sgiacomo.travaglini@arm.com 11912641Sgiacomo.travaglini@arm.com // create the internal uni-directional links in both directions 12012641Sgiacomo.travaglini@arm.com // the first direction is marked: In 12112641Sgiacomo.travaglini@arm.com addLink(a, b, int_link, LinkDirection_In); 12212641Sgiacomo.travaglini@arm.com // the second direction is marked: Out 12312641Sgiacomo.travaglini@arm.com addLink(b, a, int_link, LinkDirection_Out); 12412641Sgiacomo.travaglini@arm.com } 12512641Sgiacomo.travaglini@arm.com} 12613915Sgabeblack@google.com 12712641Sgiacomo.travaglini@arm.comvoid 12812641Sgiacomo.travaglini@arm.comTopology::init() 12912641Sgiacomo.travaglini@arm.com{ 13012641Sgiacomo.travaglini@arm.com} 13112641Sgiacomo.travaglini@arm.com 13212641Sgiacomo.travaglini@arm.com 13312641Sgiacomo.travaglini@arm.comvoid 13412641Sgiacomo.travaglini@arm.comTopology::initNetworkPtr(Network* net_ptr) 13512641Sgiacomo.travaglini@arm.com{ 13612641Sgiacomo.travaglini@arm.com for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin(); 13712641Sgiacomo.travaglini@arm.com i != params()->ext_links.end(); ++i) { 13813915Sgabeblack@google.com BasicExtLink *ext_link = (*i); 13912641Sgiacomo.travaglini@arm.com AbstractController *abs_cntrl = ext_link->params()->ext_node; 14012641Sgiacomo.travaglini@arm.com abs_cntrl->initNetworkPtr(net_ptr); 14112641Sgiacomo.travaglini@arm.com } 14212641Sgiacomo.travaglini@arm.com} 14312641Sgiacomo.travaglini@arm.com 14412641Sgiacomo.travaglini@arm.comvoid 145Topology::createLinks(Network *net, bool isReconfiguration) 146{ 147 // Find maximum switchID 148 SwitchID max_switch_id = 0; 149 for (LinkMap::const_iterator i = m_link_map.begin(); 150 i != m_link_map.end(); ++i) { 151 std::pair<int, int> src_dest = (*i).first; 152 max_switch_id = max(max_switch_id, src_dest.first); 153 max_switch_id = max(max_switch_id, src_dest.second); 154 } 155 156 // Initialize weight, latency, and inter switched vectors 157 Matrix topology_weights; 158 int num_switches = max_switch_id+1; 159 topology_weights.resize(num_switches); 160 m_component_latencies.resize(num_switches); 161 m_component_inter_switches.resize(num_switches); 162 163 for (int i = 0; i < topology_weights.size(); i++) { 164 topology_weights[i].resize(num_switches); 165 m_component_latencies[i].resize(num_switches); 166 m_component_inter_switches[i].resize(num_switches); 167 168 for (int j = 0; j < topology_weights[i].size(); j++) { 169 topology_weights[i][j] = INFINITE_LATENCY; 170 171 // initialize to invalid values 172 m_component_latencies[i][j] = -1; 173 174 // initially assume direct connections / no intermediate 175 // switches between components 176 m_component_inter_switches[i][j] = 0; 177 } 178 } 179 180 // Set identity weights to zero 181 for (int i = 0; i < topology_weights.size(); i++) { 182 topology_weights[i][i] = 0; 183 } 184 185 // Fill in the topology weights and bandwidth multipliers 186 for (LinkMap::const_iterator i = m_link_map.begin(); 187 i != m_link_map.end(); ++i) { 188 std::pair<int, int> src_dest = (*i).first; 189 BasicLink* link = (*i).second.link; 190 int src = src_dest.first; 191 int dst = src_dest.second; 192 m_component_latencies[src][dst] = link->m_latency; 193 topology_weights[src][dst] = link->m_weight; 194 } 195 196 // Walk topology and hookup the links 197 Matrix dist = shortest_path(topology_weights, m_component_latencies, 198 m_component_inter_switches); 199 for (int i = 0; i < topology_weights.size(); i++) { 200 for (int j = 0; j < topology_weights[i].size(); j++) { 201 int weight = topology_weights[i][j]; 202 if (weight > 0 && weight != INFINITE_LATENCY) { 203 NetDest destination_set = shortest_path_to_node(i, j, 204 topology_weights, dist); 205 makeLink(net, i, j, destination_set, isReconfiguration); 206 } 207 } 208 } 209} 210 211void 212Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, 213 LinkDirection dir) 214{ 215 assert(src <= m_number_of_switches+m_nodes+m_nodes); 216 assert(dest <= m_number_of_switches+m_nodes+m_nodes); 217 218 std::pair<int, int> src_dest_pair; 219 LinkEntry link_entry; 220 221 src_dest_pair.first = src; 222 src_dest_pair.second = dest; 223 link_entry.direction = dir; 224 link_entry.link = link; 225 m_link_map[src_dest_pair] = link_entry; 226} 227 228void 229Topology::makeLink(Network *net, SwitchID src, SwitchID dest, 230 const NetDest& routing_table_entry, bool isReconfiguration) 231{ 232 // Make sure we're not trying to connect two end-point nodes 233 // directly together 234 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); 235 236 std::pair<int, int> src_dest; 237 LinkEntry link_entry; 238 239 if (src < m_nodes) { 240 src_dest.first = src; 241 src_dest.second = dest; 242 link_entry = m_link_map[src_dest]; 243 net->makeInLink(src, dest - (2 * m_nodes), link_entry.link, 244 link_entry.direction, 245 routing_table_entry, 246 isReconfiguration); 247 } else if (dest < 2*m_nodes) { 248 assert(dest >= m_nodes); 249 NodeID node = dest - m_nodes; 250 src_dest.first = src; 251 src_dest.second = dest; 252 link_entry = m_link_map[src_dest]; 253 net->makeOutLink(src - (2 * m_nodes), node, link_entry.link, 254 link_entry.direction, 255 routing_table_entry, 256 isReconfiguration); 257 } else { 258 assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes)); 259 src_dest.first = src; 260 src_dest.second = dest; 261 link_entry = m_link_map[src_dest]; 262 net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes), 263 link_entry.link, link_entry.direction, 264 routing_table_entry, isReconfiguration); 265 } 266} 267 268void 269Topology::printStats(std::ostream& out) const 270{ 271 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 272 m_controller_vector[cntrl]->printStats(out); 273 } 274} 275 276void 277Topology::clearStats() 278{ 279 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 280 m_controller_vector[cntrl]->clearStats(); 281 } 282} 283 284// The following all-pairs shortest path algorithm is based on the 285// discussion from Cormen et al., Chapter 26.1. 286void 287extend_shortest_path(Matrix& current_dist, Matrix& latencies, 288 Matrix& inter_switches) 289{ 290 bool change = true; 291 int nodes = current_dist.size(); 292 293 while (change) { 294 change = false; 295 for (int i = 0; i < nodes; i++) { 296 for (int j = 0; j < nodes; j++) { 297 int minimum = current_dist[i][j]; 298 int previous_minimum = minimum; 299 int intermediate_switch = -1; 300 for (int k = 0; k < nodes; k++) { 301 minimum = min(minimum, 302 current_dist[i][k] + current_dist[k][j]); 303 if (previous_minimum != minimum) { 304 intermediate_switch = k; 305 inter_switches[i][j] = 306 inter_switches[i][k] + 307 inter_switches[k][j] + 1; 308 } 309 previous_minimum = minimum; 310 } 311 if (current_dist[i][j] != minimum) { 312 change = true; 313 current_dist[i][j] = minimum; 314 assert(intermediate_switch >= 0); 315 assert(intermediate_switch < latencies[i].size()); 316 latencies[i][j] = latencies[i][intermediate_switch] + 317 latencies[intermediate_switch][j]; 318 } 319 } 320 } 321 } 322} 323 324Matrix 325shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches) 326{ 327 Matrix dist = weights; 328 extend_shortest_path(dist, latencies, inter_switches); 329 return dist; 330} 331 332bool 333link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, 334 const Matrix& weights, const Matrix& dist) 335{ 336 return weights[src][next] + dist[next][final] == dist[src][final]; 337} 338 339NetDest 340shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights, 341 const Matrix& dist) 342{ 343 NetDest result; 344 int d = 0; 345 int machines; 346 int max_machines; 347 348 machines = MachineType_NUM; 349 max_machines = MachineType_base_number(MachineType_NUM); 350 351 for (int m = 0; m < machines; m++) { 352 for (int i = 0; i < MachineType_base_count((MachineType)m); i++) { 353 // we use "d+max_machines" below since the "destination" 354 // switches for the machines are numbered 355 // [MachineType_base_number(MachineType_NUM)... 356 // 2*MachineType_base_number(MachineType_NUM)-1] for the 357 // component network 358 if (link_is_shortest_path_to_node(src, next, d + max_machines, 359 weights, dist)) { 360 MachineID mach = {(MachineType)m, i}; 361 result.add(mach); 362 } 363 d++; 364 } 365 } 366 367 DPRINTF(RubyNetwork, "Returning shortest path\n" 368 "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, " 369 "src: %d, next: %d, result: %s\n", 370 (src-(2*max_machines)), (next-(2*max_machines)), 371 src, next, result); 372 373 return result; 374} 375 376Topology * 377TopologyParams::create() 378{ 379 return new Topology(this); 380} 381 382