Topology.cc revision 7054
111666Stushar@ece.gatech.edu/* 211666Stushar@ece.gatech.edu * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 311666Stushar@ece.gatech.edu * All rights reserved. 411666Stushar@ece.gatech.edu * 511666Stushar@ece.gatech.edu * Redistribution and use in source and binary forms, with or without 611666Stushar@ece.gatech.edu * modification, are permitted provided that the following conditions are 711666Stushar@ece.gatech.edu * met: redistributions of source code must retain the above copyright 811666Stushar@ece.gatech.edu * notice, this list of conditions and the following disclaimer; 911666Stushar@ece.gatech.edu * redistributions in binary form must reproduce the above copyright 1011666Stushar@ece.gatech.edu * notice, this list of conditions and the following disclaimer in the 1111666Stushar@ece.gatech.edu * documentation and/or other materials provided with the distribution; 1211666Stushar@ece.gatech.edu * neither the name of the copyright holders nor the names of its 1311666Stushar@ece.gatech.edu * contributors may be used to endorse or promote products derived from 1411666Stushar@ece.gatech.edu * this software without specific prior written permission. 1511666Stushar@ece.gatech.edu * 1611666Stushar@ece.gatech.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711666Stushar@ece.gatech.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811666Stushar@ece.gatech.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911666Stushar@ece.gatech.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011666Stushar@ece.gatech.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111666Stushar@ece.gatech.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211666Stushar@ece.gatech.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311666Stushar@ece.gatech.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411666Stushar@ece.gatech.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511666Stushar@ece.gatech.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611666Stushar@ece.gatech.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711666Stushar@ece.gatech.edu */ 2811666Stushar@ece.gatech.edu 2911666Stushar@ece.gatech.edu#include "mem/gems_common/util.hh" 3011666Stushar@ece.gatech.edu#include "mem/protocol/MachineType.hh" 3111666Stushar@ece.gatech.edu#include "mem/protocol/Protocol.hh" 3211666Stushar@ece.gatech.edu#include "mem/protocol/TopologyType.hh" 3311666Stushar@ece.gatech.edu#include "mem/ruby/common/NetDest.hh" 3412492Sodanrc@yahoo.com.br#include "mem/ruby/network/Network.hh" 3512492Sodanrc@yahoo.com.br#include "mem/ruby/network/simple/Topology.hh" 3611666Stushar@ece.gatech.edu#include "mem/ruby/slicc_interface/AbstractController.hh" 3711666Stushar@ece.gatech.edu#include "mem/ruby/system/System.hh" 3811666Stushar@ece.gatech.edu 3911666Stushar@ece.gatech.educonst int INFINITE_LATENCY = 10000; // Yes, this is a big hack 4011666Stushar@ece.gatech.educonst int DEFAULT_BW_MULTIPLIER = 1; // Just to be consistent with above :) 4111666Stushar@ece.gatech.edu 4211666Stushar@ece.gatech.edu// Note: In this file, we use the first 2*m_nodes SwitchIDs to 4311666Stushar@ece.gatech.edu// represent the input and output endpoint links. These really are 4411666Stushar@ece.gatech.edu// not 'switches', as they will not have a Switch object allocated for 4511666Stushar@ece.gatech.edu// them. The first m_nodes SwitchIDs are the links into the network, 4611666Stushar@ece.gatech.edu// the second m_nodes set of SwitchIDs represent the the output queues 4711666Stushar@ece.gatech.edu// of the network. 4811666Stushar@ece.gatech.edu 4911666Stushar@ece.gatech.edu// Helper functions based on chapter 29 of Cormen et al. 5011666Stushar@ece.gatech.eduvoid extend_shortest_path(Matrix& current_dist, Matrix& latencies, 5111666Stushar@ece.gatech.edu Matrix& inter_switches); 5211666Stushar@ece.gatech.eduMatrix shortest_path(const Matrix& weights, Matrix& latencies, 5311666Stushar@ece.gatech.edu Matrix& inter_switches); 5411797Smatthew.poremba@amd.combool link_is_shortest_path_to_node(SwitchID src, SwitchID next, 5511666Stushar@ece.gatech.edu SwitchID final, const Matrix& weights, const Matrix& dist); 5611666Stushar@ece.gatech.eduNetDest shortest_path_to_node(SwitchID src, SwitchID next, 5711666Stushar@ece.gatech.edu const Matrix& weights, const Matrix& dist); 5811666Stushar@ece.gatech.edu 5911666Stushar@ece.gatech.eduTopology::Topology(const Params *p) 6011666Stushar@ece.gatech.edu : SimObject(p) 6111666Stushar@ece.gatech.edu{ 6211666Stushar@ece.gatech.edu m_print_config = p->print_config; 6311666Stushar@ece.gatech.edu m_number_of_switches = p->num_int_nodes; 6411666Stushar@ece.gatech.edu // initialize component latencies record 6511666Stushar@ece.gatech.edu m_component_latencies.setSize(0); 6611666Stushar@ece.gatech.edu m_component_inter_switches.setSize(0); 6711666Stushar@ece.gatech.edu 6811666Stushar@ece.gatech.edu // Total nodes/controllers in network 6911666Stushar@ece.gatech.edu // Must make sure this is called after the State Machine constructors 7011797Smatthew.poremba@amd.com m_nodes = MachineType_base_number(MachineType_NUM); 7111666Stushar@ece.gatech.edu assert(m_nodes > 1); 7211666Stushar@ece.gatech.edu 7311666Stushar@ece.gatech.edu if (m_nodes != params()->ext_links.size() && 7411666Stushar@ece.gatech.edu m_nodes != params()->ext_links.size()) { 7511666Stushar@ece.gatech.edu fatal("m_nodes (%d) != ext_links vector length (%d)\n", 7611666Stushar@ece.gatech.edu m_nodes != params()->ext_links.size()); 7711666Stushar@ece.gatech.edu } 7811666Stushar@ece.gatech.edu 7911666Stushar@ece.gatech.edu // First create the links between the endpoints (i.e. controllers) 8011666Stushar@ece.gatech.edu // and the network. 8111666Stushar@ece.gatech.edu for (vector<ExtLink*>::const_iterator i = params()->ext_links.begin(); 8211666Stushar@ece.gatech.edu i != params()->ext_links.end(); ++i) { 8311666Stushar@ece.gatech.edu const ExtLinkParams *p = (*i)->params(); 8411666Stushar@ece.gatech.edu AbstractController *c = p->ext_node; 8511666Stushar@ece.gatech.edu 8611666Stushar@ece.gatech.edu // Store the controller pointers for later 8711666Stushar@ece.gatech.edu m_controller_vector.insertAtBottom(c); 8811666Stushar@ece.gatech.edu 8911666Stushar@ece.gatech.edu int ext_idx1 = 9011666Stushar@ece.gatech.edu MachineType_base_number(c->getMachineType()) + c->getVersion(); 9111666Stushar@ece.gatech.edu int ext_idx2 = ext_idx1 + m_nodes; 9211666Stushar@ece.gatech.edu int int_idx = p->int_node + 2*m_nodes; 9311666Stushar@ece.gatech.edu 9411666Stushar@ece.gatech.edu // create the links in both directions 9511666Stushar@ece.gatech.edu addLink(ext_idx1, int_idx, p->latency, p->bw_multiplier, p->weight); 9611666Stushar@ece.gatech.edu addLink(int_idx, ext_idx2, p->latency, p->bw_multiplier, p->weight); 9711666Stushar@ece.gatech.edu } 9811666Stushar@ece.gatech.edu 9911666Stushar@ece.gatech.edu for (vector<IntLink*>::const_iterator i = params()->int_links.begin(); 10011666Stushar@ece.gatech.edu i != params()->int_links.end(); ++i) { 10111666Stushar@ece.gatech.edu const IntLinkParams *p = (*i)->params(); 10211666Stushar@ece.gatech.edu int a = p->node_a + 2*m_nodes; 10311666Stushar@ece.gatech.edu int b = p->node_b + 2*m_nodes; 10411666Stushar@ece.gatech.edu 10511666Stushar@ece.gatech.edu // create the links in both directions 10611666Stushar@ece.gatech.edu addLink(a, b, p->latency, p->bw_multiplier, p->weight); 10711666Stushar@ece.gatech.edu addLink(b, a, p->latency, p->bw_multiplier, p->weight); 10811797Smatthew.poremba@amd.com } 10911666Stushar@ece.gatech.edu} 11011666Stushar@ece.gatech.edu 11111666Stushar@ece.gatech.edu 11211666Stushar@ece.gatech.eduvoid 11311666Stushar@ece.gatech.eduTopology::initNetworkPtr(Network* net_ptr) 11411666Stushar@ece.gatech.edu{ 11511666Stushar@ece.gatech.edu for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 11611666Stushar@ece.gatech.edu m_controller_vector[cntrl]->initNetworkPtr(net_ptr); 11711666Stushar@ece.gatech.edu } 11811666Stushar@ece.gatech.edu} 11911666Stushar@ece.gatech.edu 12011666Stushar@ece.gatech.eduvoid 12111666Stushar@ece.gatech.eduTopology::createLinks(Network *net, bool isReconfiguration) 12211666Stushar@ece.gatech.edu{ 12311666Stushar@ece.gatech.edu // Find maximum switchID 12412492Sodanrc@yahoo.com.br SwitchID max_switch_id = 0; 125 for (int i = 0; i < m_links_src_vector.size(); i++) { 126 max_switch_id = max(max_switch_id, m_links_src_vector[i]); 127 max_switch_id = max(max_switch_id, m_links_dest_vector[i]); 128 } 129 130 // Initialize weight vector 131 Matrix topology_weights; 132 Matrix topology_latency; 133 Matrix topology_bw_multis; 134 int num_switches = max_switch_id+1; 135 topology_weights.setSize(num_switches); 136 topology_latency.setSize(num_switches); 137 topology_bw_multis.setSize(num_switches); 138 139 // FIXME setting the size of a member variable here is a HACK! 140 m_component_latencies.setSize(num_switches); 141 142 // FIXME setting the size of a member variable here is a HACK! 143 m_component_inter_switches.setSize(num_switches); 144 145 for (int i = 0; i < topology_weights.size(); i++) { 146 topology_weights[i].setSize(num_switches); 147 topology_latency[i].setSize(num_switches); 148 topology_bw_multis[i].setSize(num_switches); 149 m_component_latencies[i].setSize(num_switches); 150 151 // FIXME setting the size of a member variable here is a HACK! 152 m_component_inter_switches[i].setSize(num_switches); 153 154 for (int j = 0; j < topology_weights[i].size(); j++) { 155 topology_weights[i][j] = INFINITE_LATENCY; 156 157 // initialize to invalid values 158 topology_latency[i][j] = -1; 159 topology_bw_multis[i][j] = -1; 160 m_component_latencies[i][j] = -1; 161 162 // initially assume direct connections / no intermediate 163 // switches between components 164 m_component_inter_switches[i][j] = 0; 165 } 166 } 167 168 // Set identity weights to zero 169 for (int i = 0; i < topology_weights.size(); i++) { 170 topology_weights[i][i] = 0; 171 } 172 173 // Fill in the topology weights and bandwidth multipliers 174 for (int i = 0; i < m_links_src_vector.size(); i++) { 175 int src = m_links_src_vector[i]; 176 int dst = m_links_dest_vector[i]; 177 topology_weights[src][dst] = m_links_weight_vector[i]; 178 topology_latency[src][dst] = m_links_latency_vector[i]; 179 m_component_latencies[src][dst] = m_links_latency_vector[i]; 180 topology_bw_multis[src][dst] = m_bw_multiplier_vector[i]; 181 } 182 183 // Walk topology and hookup the links 184 Matrix dist = shortest_path(topology_weights, m_component_latencies, 185 m_component_inter_switches); 186 for (int i = 0; i < topology_weights.size(); i++) { 187 for (int j = 0; j < topology_weights[i].size(); j++) { 188 int weight = topology_weights[i][j]; 189 int bw_multiplier = topology_bw_multis[i][j]; 190 int latency = topology_latency[i][j]; 191 if (weight > 0 && weight != INFINITE_LATENCY) { 192 NetDest destination_set = shortest_path_to_node(i, j, 193 topology_weights, dist); 194 assert(latency != -1); 195 makeLink(net, i, j, destination_set, latency, weight, 196 bw_multiplier, isReconfiguration); 197 } 198 } 199 } 200} 201 202SwitchID 203Topology::newSwitchID() 204{ 205 m_number_of_switches++; 206 return m_number_of_switches-1+m_nodes+m_nodes; 207} 208 209void 210Topology::addLink(SwitchID src, SwitchID dest, int link_latency) 211{ 212 addLink(src, dest, link_latency, DEFAULT_BW_MULTIPLIER, link_latency); 213} 214 215void 216Topology::addLink(SwitchID src, SwitchID dest, int link_latency, 217 int bw_multiplier) 218{ 219 addLink(src, dest, link_latency, bw_multiplier, link_latency); 220} 221 222void 223Topology::addLink(SwitchID src, SwitchID dest, int link_latency, 224 int bw_multiplier, int link_weight) 225{ 226 ASSERT(src <= m_number_of_switches+m_nodes+m_nodes); 227 ASSERT(dest <= m_number_of_switches+m_nodes+m_nodes); 228 m_links_src_vector.insertAtBottom(src); 229 m_links_dest_vector.insertAtBottom(dest); 230 m_links_latency_vector.insertAtBottom(link_latency); 231 m_links_weight_vector.insertAtBottom(link_weight); 232 m_bw_multiplier_vector.insertAtBottom(bw_multiplier); 233} 234 235void 236Topology::makeLink(Network *net, SwitchID src, SwitchID dest, 237 const NetDest& routing_table_entry, int link_latency, int link_weight, 238 int bw_multiplier, bool isReconfiguration) 239{ 240 // Make sure we're not trying to connect two end-point nodes 241 // directly together 242 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); 243 244 if (src < m_nodes) { 245 net->makeInLink(src, dest-(2*m_nodes), routing_table_entry, 246 link_latency, bw_multiplier, isReconfiguration); 247 } else if (dest < 2*m_nodes) { 248 assert(dest >= m_nodes); 249 NodeID node = dest-m_nodes; 250 net->makeOutLink(src-(2*m_nodes), node, routing_table_entry, 251 link_latency, link_weight, bw_multiplier, isReconfiguration); 252 } else { 253 assert((src >= 2*m_nodes) && (dest >= 2*m_nodes)); 254 net->makeInternalLink(src-(2*m_nodes), dest-(2*m_nodes), 255 routing_table_entry, link_latency, link_weight, bw_multiplier, 256 isReconfiguration); 257 } 258} 259 260void 261Topology::printStats(std::ostream& out) const 262{ 263 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 264 m_controller_vector[cntrl]->printStats(out); 265 } 266} 267 268void 269Topology::clearStats() 270{ 271 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 272 m_controller_vector[cntrl]->clearStats(); 273 } 274} 275 276void 277Topology::printConfig(std::ostream& out) const 278{ 279 using namespace std; 280 281 if (m_print_config == false) 282 return; 283 284 assert(m_component_latencies.size() > 0); 285 286 out << "--- Begin Topology Print ---" << endl 287 << endl 288 << "Topology print ONLY indicates the _NETWORK_ latency between two " 289 << "machines" << endl 290 << "It does NOT include the latency within the machines" << endl 291 << endl; 292 293 for (int m = 0; m < MachineType_NUM; m++) { 294 int i_end = MachineType_base_count((MachineType)m); 295 for (int i = 0; i < i_end; i++) { 296 MachineID cur_mach = {(MachineType)m, i}; 297 out << cur_mach << " Network Latencies" << endl; 298 for (int n = 0; n < MachineType_NUM; n++) { 299 int j_end = MachineType_base_count((MachineType)n); 300 for (int j = 0; j < j_end; j++) { 301 MachineID dest_mach = {(MachineType)n, j}; 302 if (cur_mach == dest_mach) 303 continue; 304 305 int src = MachineType_base_number((MachineType)m) + i; 306 int dst = MachineType_base_number(MachineType_NUM) + 307 MachineType_base_number((MachineType)n) + j; 308 int link_latency = m_component_latencies[src][dst]; 309 int intermediate_switches = 310 m_component_inter_switches[src][dst]; 311 312 // NOTE switches are assumed to have single 313 // cycle latency 314 out << " " << cur_mach << " -> " << dest_mach 315 << " net_lat: " 316 << link_latency + intermediate_switches << endl; 317 } 318 } 319 out << endl; 320 } 321 } 322 323 out << "--- End Topology Print ---" << endl; 324} 325 326// The following all-pairs shortest path algorithm is based on the 327// discussion from Cormen et al., Chapter 26.1. 328void 329extend_shortest_path(Matrix& current_dist, Matrix& latencies, 330 Matrix& inter_switches) 331{ 332 bool change = true; 333 int nodes = current_dist.size(); 334 335 while (change) { 336 change = false; 337 for (int i = 0; i < nodes; i++) { 338 for (int j = 0; j < nodes; j++) { 339 int minimum = current_dist[i][j]; 340 int previous_minimum = minimum; 341 int intermediate_switch = -1; 342 for (int k = 0; k < nodes; k++) { 343 minimum = min(minimum, 344 current_dist[i][k] + current_dist[k][j]); 345 if (previous_minimum != minimum) { 346 intermediate_switch = k; 347 inter_switches[i][j] = 348 inter_switches[i][k] + 349 inter_switches[k][j] + 1; 350 } 351 previous_minimum = minimum; 352 } 353 if (current_dist[i][j] != minimum) { 354 change = true; 355 current_dist[i][j] = minimum; 356 assert(intermediate_switch >= 0); 357 assert(intermediate_switch < latencies[i].size()); 358 latencies[i][j] = latencies[i][intermediate_switch] + 359 latencies[intermediate_switch][j]; 360 } 361 } 362 } 363 } 364} 365 366Matrix 367shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches) 368{ 369 Matrix dist = weights; 370 extend_shortest_path(dist, latencies, inter_switches); 371 return dist; 372} 373 374bool 375link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, 376 const Matrix& weights, const Matrix& dist) 377{ 378 return weights[src][next] + dist[next][final] == dist[src][final]; 379} 380 381NetDest 382shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights, 383 const Matrix& dist) 384{ 385 NetDest result; 386 int d = 0; 387 int machines; 388 int max_machines; 389 390 machines = MachineType_NUM; 391 max_machines = MachineType_base_number(MachineType_NUM); 392 393 for (int m = 0; m < machines; m++) { 394 for (int i = 0; i < MachineType_base_count((MachineType)m); i++) { 395 // we use "d+max_machines" below since the "destination" 396 // switches for the machines are numbered 397 // [MachineType_base_number(MachineType_NUM)... 398 // 2*MachineType_base_number(MachineType_NUM)-1] for the 399 // component network 400 if (link_is_shortest_path_to_node(src, next, d + max_machines, 401 weights, dist)) { 402 MachineID mach = {(MachineType)m, i}; 403 result.add(mach); 404 } 405 d++; 406 } 407 } 408 409 DEBUG_MSG(NETWORK_COMP, MedPrio, "returning shortest path"); 410 DEBUG_EXPR(NETWORK_COMP, MedPrio, (src-(2*max_machines))); 411 DEBUG_EXPR(NETWORK_COMP, MedPrio, (next-(2*max_machines))); 412 DEBUG_EXPR(NETWORK_COMP, MedPrio, src); 413 DEBUG_EXPR(NETWORK_COMP, MedPrio, next); 414 DEBUG_EXPR(NETWORK_COMP, MedPrio, result); 415 DEBUG_NEWLINE(NETWORK_COMP, MedPrio); 416 417 return result; 418} 419 420Topology * 421TopologyParams::create() 422{ 423 return new Topology(this); 424} 425 426Link * 427LinkParams::create() 428{ 429 return new Link(this); 430} 431 432ExtLink * 433ExtLinkParams::create() 434{ 435 return new ExtLink(this); 436} 437 438IntLink * 439IntLinkParams::create() 440{ 441 return new IntLink(this); 442} 443