Network.hh revision 10311:ad9c042dce54
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * The Network class is the base class for classes that implement the 31 * interconnection network between components (processor/cache 32 * components and memory/directory components). The interconnection 33 * network as described here is not a physical network, but a 34 * programming concept used to implement all communication between 35 * components. Thus parts of this 'network' will model the on-chip 36 * connections between cache controllers and directory controllers as 37 * well as the links between chip and network switches. 38 */ 39 40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__ 41#define __MEM_RUBY_NETWORK_NETWORK_HH__ 42 43#include <iostream> 44#include <string> 45#include <vector> 46 47#include "mem/protocol/LinkDirection.hh" 48#include "mem/protocol/MessageSizeType.hh" 49#include "mem/ruby/common/TypeDefines.hh" 50#include "mem/ruby/network/Topology.hh" 51#include "mem/packet.hh" 52#include "params/RubyNetwork.hh" 53#include "sim/clocked_object.hh" 54 55class NetDest; 56class MessageBuffer; 57 58class Network : public ClockedObject 59{ 60 public: 61 typedef RubyNetworkParams Params; 62 Network(const Params *p); 63 const Params * params() const 64 { return dynamic_cast<const Params *>(_params);} 65 66 virtual ~Network(); 67 virtual void init(); 68 69 static uint32_t getNumberOfVirtualNetworks() { return m_virtual_networks; } 70 int getNumNodes() const { return m_nodes; } 71 72 static uint32_t MessageSizeType_to_int(MessageSizeType size_type); 73 74 // returns the queue requested for the given component 75 virtual void setToNetQueue(NodeID id, bool ordered, int netNumber, 76 std::string vnet_type, MessageBuffer *b) = 0; 77 virtual void setFromNetQueue(NodeID id, bool ordered, int netNumber, 78 std::string vnet_type, MessageBuffer *b) = 0; 79 80 virtual void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, 81 LinkDirection direction, 82 const NetDest& routing_table_entry) = 0; 83 virtual void makeInLink(NodeID src, SwitchID dest, BasicLink* link, 84 LinkDirection direction, 85 const NetDest& routing_table_entry) = 0; 86 virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, 87 LinkDirection direction, 88 const NetDest& routing_table_entry) = 0; 89 90 virtual void collateStats() = 0; 91 virtual void print(std::ostream& out) const = 0; 92 93 /* 94 * Virtual functions for functionally reading and writing packets in 95 * the network. Each network needs to implement these for functional 96 * accesses to work correctly. 97 */ 98 virtual bool functionalRead(Packet *pkt) 99 { fatal("Functional read not implemented.\n"); } 100 virtual uint32_t functionalWrite(Packet *pkt) 101 { fatal("Functional write not implemented.\n"); } 102 103 protected: 104 // Private copy constructor and assignment operator 105 Network(const Network& obj); 106 Network& operator=(const Network& obj); 107 108 uint32_t m_nodes; 109 static uint32_t m_virtual_networks; 110 Topology* m_topology_ptr; 111 static uint32_t m_control_msg_size; 112 static uint32_t m_data_msg_size; 113 114 // vector of queues from the components 115 std::vector<std::map<int, MessageBuffer*> > m_toNetQueues; 116 std::vector<std::map<int, MessageBuffer*> > m_fromNetQueues; 117 118 std::vector<bool> m_in_use; 119 std::vector<bool> m_ordered; 120 121 private: 122 //! Callback class used for collating statistics from all the 123 //! controller of this type. 124 class StatsCallback : public Callback 125 { 126 private: 127 Network *ctr; 128 129 public: 130 virtual ~StatsCallback() {} 131 132 StatsCallback(Network *_ctr) 133 : ctr(_ctr) 134 { 135 } 136 137 void process() {ctr->collateStats();} 138 }; 139}; 140 141inline std::ostream& 142operator<<(std::ostream& out, const Network& obj) 143{ 144 obj.print(out); 145 out << std::flush; 146 return out; 147} 148 149#endif // __MEM_RUBY_NETWORK_NETWORK_HH__ 150