request.hh revision 10824
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Steve Reinhardt 42 * Ali Saidi 43 */ 44 45/** 46 * @file 47 * Declaration of a request, the overall memory request consisting of 48 the parts of the request that are persistent throughout the transaction. 49 */ 50 51#ifndef __MEM_REQUEST_HH__ 52#define __MEM_REQUEST_HH__ 53 54#include <cassert> 55#include <climits> 56 57#include "base/flags.hh" 58#include "base/misc.hh" 59#include "base/types.hh" 60#include "sim/core.hh" 61 62/** 63 * Special TaskIds that are used for per-context-switch stats dumps 64 * and Cache Occupancy. Having too many tasks seems to be a problem 65 * with vector stats. 1024 seems to be a reasonable number that 66 * doesn't cause a problem with stats and is large enough to realistic 67 * benchmarks (Linux/Android boot, BBench, etc.) 68 */ 69 70namespace ContextSwitchTaskId { 71 enum TaskId { 72 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */ 73 Prefetcher = 1022, /* For cache lines brought in by prefetcher */ 74 DMA = 1023, /* Mostly Table Walker */ 75 Unknown = 1024, 76 NumTaskId 77 }; 78} 79 80class Request; 81 82typedef Request* RequestPtr; 83typedef uint16_t MasterID; 84 85class Request 86{ 87 public: 88 typedef uint32_t FlagsType; 89 typedef uint8_t ArchFlagsType; 90 typedef ::Flags<FlagsType> Flags; 91 92 /** 93 * Architecture specific flags. 94 * 95 * These bits int the flag field are reserved for 96 * architecture-specific code. For example, SPARC uses them to 97 * represent ASIs. 98 */ 99 static const FlagsType ARCH_BITS = 0x000000FF; 100 /** The request was an instruction fetch. */ 101 static const FlagsType INST_FETCH = 0x00000100; 102 /** The virtual address is also the physical address. */ 103 static const FlagsType PHYSICAL = 0x00000200; 104 /** 105 * The request is to an uncacheable address. 106 * 107 * @note Uncacheable accesses may be reordered by CPU models. The 108 * STRICT_ORDER flag should be set if such reordering is 109 * undesirable. 110 */ 111 static const FlagsType UNCACHEABLE = 0x00000400; 112 /** 113 * The request is required to be strictly ordered by <i>CPU 114 * models</i> and is non-speculative. 115 * 116 * A strictly ordered request is guaranteed to never be re-ordered 117 * or executed speculatively by a CPU model. The memory system may 118 * still reorder requests in caches unless the UNCACHEABLE flag is 119 * set as well. 120 */ 121 static const FlagsType STRICT_ORDER = 0x00000800; 122 /** This request is to a memory mapped register. */ 123 static const FlagsType MMAPPED_IPR = 0x00002000; 124 /** This request is a clear exclusive. */ 125 static const FlagsType CLEAR_LL = 0x00004000; 126 /** This request is made in privileged mode. */ 127 static const FlagsType PRIVILEGED = 0x00008000; 128 129 /** This is a write that is targeted and zeroing an entire cache block. 130 * There is no need for a read/modify/write 131 */ 132 static const FlagsType CACHE_BLOCK_ZERO = 0x00010000; 133 134 /** The request should not cause a memory access. */ 135 static const FlagsType NO_ACCESS = 0x00080000; 136 /** This request will lock or unlock the accessed memory. When used with 137 * a load, the access locks the particular chunk of memory. When used 138 * with a store, it unlocks. The rule is that locked accesses have to be 139 * made up of a locked load, some operation on the data, and then a locked 140 * store. 141 */ 142 static const FlagsType LOCKED_RMW = 0x00100000; 143 /** The request is a Load locked/store conditional. */ 144 static const FlagsType LLSC = 0x00200000; 145 /** This request is for a memory swap. */ 146 static const FlagsType MEM_SWAP = 0x00400000; 147 static const FlagsType MEM_SWAP_COND = 0x00800000; 148 149 /** The request is a prefetch. */ 150 static const FlagsType PREFETCH = 0x01000000; 151 /** The request should be prefetched into the exclusive state. */ 152 static const FlagsType PF_EXCLUSIVE = 0x02000000; 153 /** The request should be marked as LRU. */ 154 static const FlagsType EVICT_NEXT = 0x04000000; 155 156 /** The request should be handled by the generic IPR code (only 157 * valid together with MMAPPED_IPR) */ 158 static const FlagsType GENERIC_IPR = 0x08000000; 159 160 /** The request targets the secure memory space. */ 161 static const FlagsType SECURE = 0x10000000; 162 /** The request is a page table walk */ 163 static const FlagsType PT_WALK = 0x20000000; 164 165 /** These flags are *not* cleared when a Request object is reused 166 (assigned a new address). */ 167 static const FlagsType STICKY_FLAGS = INST_FETCH; 168 169 /** Request Ids that are statically allocated 170 * @{*/ 171 /** This request id is used for writeback requests by the caches */ 172 static const MasterID wbMasterId = 0; 173 /** This request id is used for functional requests that don't come from a 174 * particular device 175 */ 176 static const MasterID funcMasterId = 1; 177 /** This request id is used for message signaled interrupts */ 178 static const MasterID intMasterId = 2; 179 /** Invalid request id for assertion checking only. It is invalid behavior 180 * to ever send this id as part of a request. 181 * @todo C++1x replace with numeric_limits when constexpr is added */ 182 static const MasterID invldMasterId = std::numeric_limits<MasterID>::max(); 183 /** @} */ 184 185 /** Invalid or unknown Pid. Possible when operating system is not present 186 * or has not assigned a pid yet */ 187 static const uint32_t invldPid = std::numeric_limits<uint32_t>::max(); 188 189 private: 190 typedef uint8_t PrivateFlagsType; 191 typedef ::Flags<PrivateFlagsType> PrivateFlags; 192 193 /** Whether or not the size is valid. */ 194 static const PrivateFlagsType VALID_SIZE = 0x00000001; 195 /** Whether or not paddr is valid (has been written yet). */ 196 static const PrivateFlagsType VALID_PADDR = 0x00000002; 197 /** Whether or not the vaddr & asid are valid. */ 198 static const PrivateFlagsType VALID_VADDR = 0x00000004; 199 /** Whether or not the pc is valid. */ 200 static const PrivateFlagsType VALID_PC = 0x00000010; 201 /** Whether or not the context ID is valid. */ 202 static const PrivateFlagsType VALID_CONTEXT_ID = 0x00000020; 203 static const PrivateFlagsType VALID_THREAD_ID = 0x00000040; 204 /** Whether or not the sc result is valid. */ 205 static const PrivateFlagsType VALID_EXTRA_DATA = 0x00000080; 206 207 /** These flags are *not* cleared when a Request object is reused 208 (assigned a new address). */ 209 static const PrivateFlagsType STICKY_PRIVATE_FLAGS = 210 VALID_CONTEXT_ID | VALID_THREAD_ID; 211 212 private: 213 214 /** 215 * Set up a physical (e.g. device) request in a previously 216 * allocated Request object. 217 */ 218 void 219 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 220 { 221 assert(size >= 0); 222 _paddr = paddr; 223 _size = size; 224 _time = time; 225 _masterId = mid; 226 _flags.clear(~STICKY_FLAGS); 227 _flags.set(flags); 228 privateFlags.clear(~STICKY_PRIVATE_FLAGS); 229 privateFlags.set(VALID_PADDR|VALID_SIZE); 230 depth = 0; 231 accessDelta = 0; 232 //translateDelta = 0; 233 } 234 235 /** 236 * The physical address of the request. Valid only if validPaddr 237 * is set. 238 */ 239 Addr _paddr; 240 241 /** 242 * The size of the request. This field must be set when vaddr or 243 * paddr is written via setVirt() or setPhys(), so it is always 244 * valid as long as one of the address fields is valid. 245 */ 246 unsigned _size; 247 248 /** The requestor ID which is unique in the system for all ports 249 * that are capable of issuing a transaction 250 */ 251 MasterID _masterId; 252 253 /** Flag structure for the request. */ 254 Flags _flags; 255 256 /** Private flags for field validity checking. */ 257 PrivateFlags privateFlags; 258 259 /** 260 * The time this request was started. Used to calculate 261 * latencies. This field is set to curTick() any time paddr or vaddr 262 * is written. 263 */ 264 Tick _time; 265 266 /** 267 * The task id associated with this request 268 */ 269 uint32_t _taskId; 270 271 /** The address space ID. */ 272 int _asid; 273 274 /** The virtual address of the request. */ 275 Addr _vaddr; 276 277 /** 278 * Extra data for the request, such as the return value of 279 * store conditional or the compare value for a CAS. */ 280 uint64_t _extraData; 281 282 /** The context ID (for statistics, typically). */ 283 int _contextId; 284 /** The thread ID (id within this CPU) */ 285 ThreadID _threadId; 286 287 /** program counter of initiating access; for tracing/debugging */ 288 Addr _pc; 289 290 public: 291 292 /** 293 * Minimal constructor. No fields are initialized. (Note that 294 * _flags and privateFlags are cleared by Flags default 295 * constructor.) 296 */ 297 Request() 298 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 299 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 300 _extraData(0), _contextId(0), _threadId(0), _pc(0), 301 translateDelta(0), accessDelta(0), depth(0) 302 {} 303 304 /** 305 * Constructor for physical (e.g. device) requests. Initializes 306 * just physical address, size, flags, and timestamp (to curTick()). 307 * These fields are adequate to perform a request. 308 */ 309 Request(Addr paddr, unsigned size, Flags flags, MasterID mid) 310 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 311 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 312 _extraData(0), _contextId(0), _threadId(0), _pc(0), 313 translateDelta(0), accessDelta(0), depth(0) 314 { 315 setPhys(paddr, size, flags, mid, curTick()); 316 } 317 318 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 319 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 320 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 321 _extraData(0), _contextId(0), _threadId(0), _pc(0), 322 translateDelta(0), accessDelta(0), depth(0) 323 { 324 setPhys(paddr, size, flags, mid, time); 325 } 326 327 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time, 328 Addr pc) 329 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 330 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 331 _extraData(0), _contextId(0), _threadId(0), _pc(0), 332 translateDelta(0), accessDelta(0), depth(0) 333 { 334 setPhys(paddr, size, flags, mid, time); 335 privateFlags.set(VALID_PC); 336 _pc = pc; 337 } 338 339 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 340 Addr pc, int cid, ThreadID tid) 341 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 342 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 343 _extraData(0), _contextId(0), _threadId(0), _pc(0), 344 translateDelta(0), accessDelta(0), depth(0) 345 { 346 setVirt(asid, vaddr, size, flags, mid, pc); 347 setThreadContext(cid, tid); 348 } 349 350 ~Request() {} 351 352 /** 353 * Set up CPU and thread numbers. 354 */ 355 void 356 setThreadContext(int context_id, ThreadID tid) 357 { 358 _contextId = context_id; 359 _threadId = tid; 360 privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID); 361 } 362 363 /** 364 * Set up a virtual (e.g., CPU) request in a previously 365 * allocated Request object. 366 */ 367 void 368 setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 369 Addr pc) 370 { 371 _asid = asid; 372 _vaddr = vaddr; 373 _size = size; 374 _masterId = mid; 375 _pc = pc; 376 _time = curTick(); 377 378 _flags.clear(~STICKY_FLAGS); 379 _flags.set(flags); 380 privateFlags.clear(~STICKY_PRIVATE_FLAGS); 381 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC); 382 depth = 0; 383 accessDelta = 0; 384 translateDelta = 0; 385 } 386 387 /** 388 * Set just the physical address. This usually used to record the 389 * result of a translation. However, when using virtualized CPUs 390 * setPhys() is sometimes called to finalize a physical address 391 * without a virtual address, so we can't check if the virtual 392 * address is valid. 393 */ 394 void 395 setPaddr(Addr paddr) 396 { 397 _paddr = paddr; 398 privateFlags.set(VALID_PADDR); 399 } 400 401 /** 402 * Generate two requests as if this request had been split into two 403 * pieces. The original request can't have been translated already. 404 */ 405 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2) 406 { 407 assert(privateFlags.isSet(VALID_VADDR)); 408 assert(privateFlags.noneSet(VALID_PADDR)); 409 assert(split_addr > _vaddr && split_addr < _vaddr + _size); 410 req1 = new Request(*this); 411 req2 = new Request(*this); 412 req1->_size = split_addr - _vaddr; 413 req2->_vaddr = split_addr; 414 req2->_size = _size - req1->_size; 415 } 416 417 /** 418 * Accessor for paddr. 419 */ 420 bool 421 hasPaddr() const 422 { 423 return privateFlags.isSet(VALID_PADDR); 424 } 425 426 Addr 427 getPaddr() const 428 { 429 assert(privateFlags.isSet(VALID_PADDR)); 430 return _paddr; 431 } 432 433 /** 434 * Time for the TLB/table walker to successfully translate this request. 435 */ 436 Tick translateDelta; 437 438 /** 439 * Access latency to complete this memory transaction not including 440 * translation time. 441 */ 442 Tick accessDelta; 443 444 /** 445 * Level of the cache hierachy where this request was responded to 446 * (e.g. 0 = L1; 1 = L2). 447 */ 448 mutable int depth; 449 450 /** 451 * Accessor for size. 452 */ 453 bool 454 hasSize() const 455 { 456 return privateFlags.isSet(VALID_SIZE); 457 } 458 459 unsigned 460 getSize() const 461 { 462 assert(privateFlags.isSet(VALID_SIZE)); 463 return _size; 464 } 465 466 /** Accessor for time. */ 467 Tick 468 time() const 469 { 470 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 471 return _time; 472 } 473 474 /** Accessor for flags. */ 475 Flags 476 getFlags() 477 { 478 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 479 return _flags; 480 } 481 482 /** Note that unlike other accessors, this function sets *specific 483 flags* (ORs them in); it does not assign its argument to the 484 _flags field. Thus this method should rightly be called 485 setFlags() and not just flags(). */ 486 void 487 setFlags(Flags flags) 488 { 489 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 490 _flags.set(flags); 491 } 492 493 /** Accessor function for vaddr.*/ 494 bool 495 hasVaddr() const 496 { 497 return privateFlags.isSet(VALID_VADDR); 498 } 499 500 Addr 501 getVaddr() const 502 { 503 assert(privateFlags.isSet(VALID_VADDR)); 504 return _vaddr; 505 } 506 507 /** Accesssor for the requestor id. */ 508 MasterID 509 masterId() const 510 { 511 return _masterId; 512 } 513 514 uint32_t 515 taskId() const 516 { 517 return _taskId; 518 } 519 520 void 521 taskId(uint32_t id) { 522 _taskId = id; 523 } 524 525 /** Accessor function for asid.*/ 526 int 527 getAsid() const 528 { 529 assert(privateFlags.isSet(VALID_VADDR)); 530 return _asid; 531 } 532 533 /** Accessor function for asid.*/ 534 void 535 setAsid(int asid) 536 { 537 _asid = asid; 538 } 539 540 /** Accessor function for architecture-specific flags.*/ 541 ArchFlagsType 542 getArchFlags() const 543 { 544 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 545 return _flags & ARCH_BITS; 546 } 547 548 /** Accessor function to check if sc result is valid. */ 549 bool 550 extraDataValid() const 551 { 552 return privateFlags.isSet(VALID_EXTRA_DATA); 553 } 554 555 /** Accessor function for store conditional return value.*/ 556 uint64_t 557 getExtraData() const 558 { 559 assert(privateFlags.isSet(VALID_EXTRA_DATA)); 560 return _extraData; 561 } 562 563 /** Accessor function for store conditional return value.*/ 564 void 565 setExtraData(uint64_t extraData) 566 { 567 _extraData = extraData; 568 privateFlags.set(VALID_EXTRA_DATA); 569 } 570 571 bool 572 hasContextId() const 573 { 574 return privateFlags.isSet(VALID_CONTEXT_ID); 575 } 576 577 /** Accessor function for context ID.*/ 578 int 579 contextId() const 580 { 581 assert(privateFlags.isSet(VALID_CONTEXT_ID)); 582 return _contextId; 583 } 584 585 /** Accessor function for thread ID. */ 586 ThreadID 587 threadId() const 588 { 589 assert(privateFlags.isSet(VALID_THREAD_ID)); 590 return _threadId; 591 } 592 593 void 594 setPC(Addr pc) 595 { 596 privateFlags.set(VALID_PC); 597 _pc = pc; 598 } 599 600 bool 601 hasPC() const 602 { 603 return privateFlags.isSet(VALID_PC); 604 } 605 606 /** Accessor function for pc.*/ 607 Addr 608 getPC() const 609 { 610 assert(privateFlags.isSet(VALID_PC)); 611 return _pc; 612 } 613 614 /** 615 * Increment/Get the depth at which this request is responded to. 616 * This currently happens when the request misses in any cache level. 617 */ 618 void incAccessDepth() const { depth++; } 619 int getAccessDepth() const { return depth; } 620 621 /** 622 * Set/Get the time taken for this request to be successfully translated. 623 */ 624 void setTranslateLatency() { translateDelta = curTick() - _time; } 625 Tick getTranslateLatency() const { return translateDelta; } 626 627 /** 628 * Set/Get the time taken to complete this request's access, not including 629 * the time to successfully translate the request. 630 */ 631 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; } 632 Tick getAccessLatency() const { return accessDelta; } 633 634 /** Accessor functions for flags. Note that these are for testing 635 only; setting flags should be done via setFlags(). */ 636 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); } 637 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); } 638 bool isInstFetch() const { return _flags.isSet(INST_FETCH); } 639 bool isPrefetch() const { return _flags.isSet(PREFETCH); } 640 bool isLLSC() const { return _flags.isSet(LLSC); } 641 bool isPriv() const { return _flags.isSet(PRIVILEGED); } 642 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); } 643 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } 644 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } 645 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); } 646 bool isClearLL() const { return _flags.isSet(CLEAR_LL); } 647 bool isSecure() const { return _flags.isSet(SECURE); } 648 bool isPTWalk() const { return _flags.isSet(PT_WALK); } 649}; 650 651#endif // __MEM_REQUEST_HH__ 652