request.hh revision 3806
12381SN/A/* 22381SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32381SN/A * All rights reserved. 42381SN/A * 52381SN/A * Redistribution and use in source and binary forms, with or without 62381SN/A * modification, are permitted provided that the following conditions are 72381SN/A * met: redistributions of source code must retain the above copyright 82381SN/A * notice, this list of conditions and the following disclaimer; 92381SN/A * redistributions in binary form must reproduce the above copyright 102381SN/A * notice, this list of conditions and the following disclaimer in the 112381SN/A * documentation and/or other materials provided with the distribution; 122381SN/A * neither the name of the copyright holders nor the names of its 132381SN/A * contributors may be used to endorse or promote products derived from 142381SN/A * this software without specific prior written permission. 152381SN/A * 162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Ali Saidi 312381SN/A */ 322381SN/A 332381SN/A/** 342982Sstever@eecs.umich.edu * @file 352982Sstever@eecs.umich.edu * Declaration of a request, the overall memory request consisting of 362381SN/A the parts of the request that are persistent throughout the transaction. 372381SN/A */ 382381SN/A 392381SN/A#ifndef __MEM_REQUEST_HH__ 402381SN/A#define __MEM_REQUEST_HH__ 412381SN/A 422980Sgblack@eecs.umich.edu#include "sim/host.hh" 432972Sgblack@eecs.umich.edu#include "sim/root.hh" 442394SN/A 452989Ssaidi@eecs.umich.edu#include <cassert> 462989Ssaidi@eecs.umich.edu 472394SN/Aclass Request; 482394SN/A 492394SN/Atypedef Request* RequestPtr; 502394SN/A 512812Srdreslin@umich.edu 523806Ssaidi@eecs.umich.edu/** ASI information for this request if it exsits. */ 533806Ssaidi@eecs.umich.educonst uint32_t ASI_BITS = 0x000FF; 542395SN/A/** The request is a Load locked/store conditional. */ 553806Ssaidi@eecs.umich.educonst uint32_t LOCKED = 0x00100; 562395SN/A/** The virtual address is also the physical address. */ 573806Ssaidi@eecs.umich.educonst uint32_t PHYSICAL = 0x00200; 582395SN/A/** The request is an ALPHA VPTE pal access (hw_ld). */ 593806Ssaidi@eecs.umich.educonst uint32_t VPTE = 0x00400; 602395SN/A/** Use the alternate mode bits in ALPHA. */ 613806Ssaidi@eecs.umich.educonst uint32_t ALTMODE = 0x00800; 622395SN/A/** The request is to an uncacheable address. */ 633806Ssaidi@eecs.umich.educonst uint32_t UNCACHEABLE = 0x01000; 642395SN/A/** The request should not cause a page fault. */ 653806Ssaidi@eecs.umich.educonst uint32_t NO_FAULT = 0x02000; 662397SN/A/** The request should be prefetched into the exclusive state. */ 673806Ssaidi@eecs.umich.educonst uint32_t PF_EXCLUSIVE = 0x10000; 682397SN/A/** The request should be marked as LRU. */ 693806Ssaidi@eecs.umich.educonst uint32_t EVICT_NEXT = 0x20000; 702495SN/A/** The request should ignore unaligned access faults */ 713806Ssaidi@eecs.umich.educonst uint32_t NO_ALIGN_FAULT = 0x40000; 722814Srdreslin@umich.edu/** The request was an instruction read. */ 733806Ssaidi@eecs.umich.educonst uint32_t INST_READ = 0x80000; 742395SN/A 752381SN/Aclass Request 762381SN/A{ 772663Sstever@eecs.umich.edu private: 782663Sstever@eecs.umich.edu /** 792663Sstever@eecs.umich.edu * The physical address of the request. Valid only if validPaddr 802663Sstever@eecs.umich.edu * is set. */ 812663Sstever@eecs.umich.edu Addr paddr; 822532SN/A 832663Sstever@eecs.umich.edu /** 842663Sstever@eecs.umich.edu * The size of the request. This field must be set when vaddr or 852663Sstever@eecs.umich.edu * paddr is written via setVirt() or setPhys(), so it is always 862663Sstever@eecs.umich.edu * valid as long as one of the address fields is valid. */ 872381SN/A int size; 882395SN/A 892532SN/A /** Flag structure for the request. */ 902395SN/A uint32_t flags; 912384SN/A 922663Sstever@eecs.umich.edu /** 932663Sstever@eecs.umich.edu * The time this request was started. Used to calculate 942663Sstever@eecs.umich.edu * latencies. This field is set to curTick any time paddr or vaddr 952663Sstever@eecs.umich.edu * is written. */ 962663Sstever@eecs.umich.edu Tick time; 972384SN/A 982384SN/A /** The address space ID. */ 992384SN/A int asid; 1003806Ssaidi@eecs.umich.edu 1013804Ssaidi@eecs.umich.edu /** This request is to a memory mapped register. */ 1023806Ssaidi@eecs.umich.edu bool mmapedIpr; 1033804Ssaidi@eecs.umich.edu 1042663Sstever@eecs.umich.edu /** The virtual address of the request. */ 1052663Sstever@eecs.umich.edu Addr vaddr; 1062384SN/A 1072384SN/A /** The return value of store conditional. */ 1082384SN/A uint64_t scResult; 1092384SN/A 1102663Sstever@eecs.umich.edu /** The cpu number (for statistics, typically). */ 1112384SN/A int cpuNum; 1122663Sstever@eecs.umich.edu /** The requesting thread id (for statistics, typically). */ 1132384SN/A int threadNum; 1142384SN/A 1152381SN/A /** program counter of initiating access; for tracing/debugging */ 1162381SN/A Addr pc; 1172663Sstever@eecs.umich.edu 1182663Sstever@eecs.umich.edu /** Whether or not paddr is valid (has been written yet). */ 1192663Sstever@eecs.umich.edu bool validPaddr; 1202663Sstever@eecs.umich.edu /** Whether or not the asid & vaddr are valid. */ 1212663Sstever@eecs.umich.edu bool validAsidVaddr; 1222663Sstever@eecs.umich.edu /** Whether or not the sc result is valid. */ 1232663Sstever@eecs.umich.edu bool validScResult; 1242663Sstever@eecs.umich.edu /** Whether or not the cpu number & thread ID are valid. */ 1252663Sstever@eecs.umich.edu bool validCpuAndThreadNums; 1262663Sstever@eecs.umich.edu /** Whether or not the pc is valid. */ 1272532SN/A bool validPC; 1282532SN/A 1292532SN/A public: 1302663Sstever@eecs.umich.edu /** Minimal constructor. No fields are initialized. */ 1312663Sstever@eecs.umich.edu Request() 1322663Sstever@eecs.umich.edu : validPaddr(false), validAsidVaddr(false), 1332663Sstever@eecs.umich.edu validScResult(false), validCpuAndThreadNums(false), validPC(false) 1342663Sstever@eecs.umich.edu {} 1352532SN/A 1362663Sstever@eecs.umich.edu /** 1372663Sstever@eecs.umich.edu * Constructor for physical (e.g. device) requests. Initializes 1382663Sstever@eecs.umich.edu * just physical address, size, flags, and timestamp (to curTick). 1392663Sstever@eecs.umich.edu * These fields are adequate to perform a request. */ 1402663Sstever@eecs.umich.edu Request(Addr _paddr, int _size, int _flags) 1412663Sstever@eecs.umich.edu : validCpuAndThreadNums(false) 1422663Sstever@eecs.umich.edu { setPhys(_paddr, _size, _flags); } 1432532SN/A 1442669Sktlim@umich.edu Request(int _asid, Addr _vaddr, int _size, int _flags, Addr _pc, 1452669Sktlim@umich.edu int _cpuNum, int _threadNum) 1462669Sktlim@umich.edu { 1472669Sktlim@umich.edu setThreadContext(_cpuNum, _threadNum); 1482669Sktlim@umich.edu setVirt(_asid, _vaddr, _size, _flags, _pc); 1492669Sktlim@umich.edu } 1502669Sktlim@umich.edu 1512663Sstever@eecs.umich.edu /** 1522663Sstever@eecs.umich.edu * Set up CPU and thread numbers. */ 1532663Sstever@eecs.umich.edu void setThreadContext(int _cpuNum, int _threadNum) 1542663Sstever@eecs.umich.edu { 1552663Sstever@eecs.umich.edu cpuNum = _cpuNum; 1562663Sstever@eecs.umich.edu threadNum = _threadNum; 1572663Sstever@eecs.umich.edu validCpuAndThreadNums = true; 1582663Sstever@eecs.umich.edu } 1592532SN/A 1602663Sstever@eecs.umich.edu /** 1612663Sstever@eecs.umich.edu * Set up a physical (e.g. device) request in a previously 1622663Sstever@eecs.umich.edu * allocated Request object. */ 1632663Sstever@eecs.umich.edu void setPhys(Addr _paddr, int _size, int _flags) 1642663Sstever@eecs.umich.edu { 1652663Sstever@eecs.umich.edu paddr = _paddr; 1662663Sstever@eecs.umich.edu size = _size; 1672663Sstever@eecs.umich.edu flags = _flags; 1682663Sstever@eecs.umich.edu time = curTick; 1692663Sstever@eecs.umich.edu validPaddr = true; 1702663Sstever@eecs.umich.edu validAsidVaddr = false; 1712663Sstever@eecs.umich.edu validPC = false; 1722663Sstever@eecs.umich.edu validScResult = false; 1733806Ssaidi@eecs.umich.edu mmapedIpr = false; 1742663Sstever@eecs.umich.edu } 1752532SN/A 1762663Sstever@eecs.umich.edu /** 1772663Sstever@eecs.umich.edu * Set up a virtual (e.g., CPU) request in a previously 1782663Sstever@eecs.umich.edu * allocated Request object. */ 1792663Sstever@eecs.umich.edu void setVirt(int _asid, Addr _vaddr, int _size, int _flags, Addr _pc) 1802663Sstever@eecs.umich.edu { 1812663Sstever@eecs.umich.edu asid = _asid; 1822663Sstever@eecs.umich.edu vaddr = _vaddr; 1832663Sstever@eecs.umich.edu size = _size; 1842663Sstever@eecs.umich.edu flags = _flags; 1852663Sstever@eecs.umich.edu pc = _pc; 1862663Sstever@eecs.umich.edu time = curTick; 1872663Sstever@eecs.umich.edu validPaddr = false; 1882663Sstever@eecs.umich.edu validAsidVaddr = true; 1892663Sstever@eecs.umich.edu validPC = true; 1902663Sstever@eecs.umich.edu validScResult = false; 1913806Ssaidi@eecs.umich.edu mmapedIpr = false; 1922663Sstever@eecs.umich.edu } 1932532SN/A 1942663Sstever@eecs.umich.edu /** Set just the physical address. This should only be used to 1952663Sstever@eecs.umich.edu * record the result of a translation, and thus the vaddr must be 1962663Sstever@eecs.umich.edu * valid before this method is called. Otherwise, use setPhys() 1972663Sstever@eecs.umich.edu * to guarantee that the size and flags are also set. 1982663Sstever@eecs.umich.edu */ 1992663Sstever@eecs.umich.edu void setPaddr(Addr _paddr) 2002663Sstever@eecs.umich.edu { 2012663Sstever@eecs.umich.edu assert(validAsidVaddr); 2022663Sstever@eecs.umich.edu paddr = _paddr; 2032663Sstever@eecs.umich.edu validPaddr = true; 2042663Sstever@eecs.umich.edu } 2052532SN/A 2062663Sstever@eecs.umich.edu /** Accessor for paddr. */ 2072663Sstever@eecs.umich.edu Addr getPaddr() { assert(validPaddr); return paddr; } 2082663Sstever@eecs.umich.edu 2092663Sstever@eecs.umich.edu /** Accessor for size. */ 2102663Sstever@eecs.umich.edu int getSize() { assert(validPaddr || validAsidVaddr); return size; } 2112663Sstever@eecs.umich.edu /** Accessor for time. */ 2122663Sstever@eecs.umich.edu Tick getTime() { assert(validPaddr || validAsidVaddr); return time; } 2132663Sstever@eecs.umich.edu 2142663Sstever@eecs.umich.edu /** Accessor for flags. */ 2152663Sstever@eecs.umich.edu uint32_t getFlags() { assert(validPaddr || validAsidVaddr); return flags; } 2162663Sstever@eecs.umich.edu /** Accessor for paddr. */ 2172663Sstever@eecs.umich.edu void setFlags(uint32_t _flags) 2182663Sstever@eecs.umich.edu { assert(validPaddr || validAsidVaddr); flags = _flags; } 2192663Sstever@eecs.umich.edu 2202663Sstever@eecs.umich.edu /** Accessor function for vaddr.*/ 2212663Sstever@eecs.umich.edu Addr getVaddr() { assert(validAsidVaddr); return vaddr; } 2222663Sstever@eecs.umich.edu 2232663Sstever@eecs.umich.edu /** Accessor function for asid.*/ 2242663Sstever@eecs.umich.edu int getAsid() { assert(validAsidVaddr); return asid; } 2252663Sstever@eecs.umich.edu 2263804Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2273806Ssaidi@eecs.umich.edu uint8_t getAsi() { assert(validAsidVaddr); return flags & ASI_BITS; } 2283804Ssaidi@eecs.umich.edu 2293804Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2303806Ssaidi@eecs.umich.edu void setAsi(uint8_t a) 2313806Ssaidi@eecs.umich.edu { assert(validAsidVaddr); flags = (flags & ~ASI_BITS) | a; } 2323806Ssaidi@eecs.umich.edu 2333804Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2343806Ssaidi@eecs.umich.edu bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; } 2353806Ssaidi@eecs.umich.edu 2363806Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2373806Ssaidi@eecs.umich.edu void setMmapedIpr(bool r) { assert(validPaddr); mmapedIpr = r; } 2383804Ssaidi@eecs.umich.edu 2392679Sktlim@umich.edu /** Accessor function to check if sc result is valid. */ 2402679Sktlim@umich.edu bool scResultValid() { return validScResult; } 2412663Sstever@eecs.umich.edu /** Accessor function for store conditional return value.*/ 2422663Sstever@eecs.umich.edu uint64_t getScResult() { assert(validScResult); return scResult; } 2432663Sstever@eecs.umich.edu /** Accessor function for store conditional return value.*/ 2442663Sstever@eecs.umich.edu void setScResult(uint64_t _scResult) 2452663Sstever@eecs.umich.edu { scResult = _scResult; validScResult = true; } 2462663Sstever@eecs.umich.edu 2472663Sstever@eecs.umich.edu /** Accessor function for cpu number.*/ 2482663Sstever@eecs.umich.edu int getCpuNum() { assert(validCpuAndThreadNums); return cpuNum; } 2492663Sstever@eecs.umich.edu /** Accessor function for thread number.*/ 2502663Sstever@eecs.umich.edu int getThreadNum() { assert(validCpuAndThreadNums); return threadNum; } 2512663Sstever@eecs.umich.edu 2522663Sstever@eecs.umich.edu /** Accessor function for pc.*/ 2532663Sstever@eecs.umich.edu Addr getPC() { assert(validPC); return pc; } 2542532SN/A 2552811Srdreslin@umich.edu /** Accessor Function to Check Cacheability. */ 2563170Sstever@eecs.umich.edu bool isUncacheable() { return (getFlags() & UNCACHEABLE) != 0; } 2572811Srdreslin@umich.edu 2583170Sstever@eecs.umich.edu bool isInstRead() { return (getFlags() & INST_READ) != 0; } 2593170Sstever@eecs.umich.edu 2603170Sstever@eecs.umich.edu bool isLocked() { return (getFlags() & LOCKED) != 0; } 2612814Srdreslin@umich.edu 2622641Sstever@eecs.umich.edu friend class Packet; 2632384SN/A}; 2642381SN/A 2652381SN/A#endif // __MEM_REQUEST_HH__ 266