request.hh revision 2395
1802SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 3802SN/A * All rights reserved. 4802SN/A * 5802SN/A * Redistribution and use in source and binary forms, with or without 6802SN/A * modification, are permitted provided that the following conditions are 7802SN/A * met: redistributions of source code must retain the above copyright 8802SN/A * notice, this list of conditions and the following disclaimer; 9802SN/A * redistributions in binary form must reproduce the above copyright 10802SN/A * notice, this list of conditions and the following disclaimer in the 11802SN/A * documentation and/or other materials provided with the distribution; 12802SN/A * neither the name of the copyright holders nor the names of its 13802SN/A * contributors may be used to endorse or promote products derived from 14802SN/A * this software without specific prior written permission. 15802SN/A * 16802SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17802SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18802SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19802SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20802SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21802SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22802SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23802SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24802SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25802SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26802SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 29802SN/A/** 30802SN/A * @file Decleration of a request, the overall memory request consisting of 311722SN/A the parts of the request that are persistent throughout the transaction. 32802SN/A */ 33802SN/A 34802SN/A#ifndef __MEM_REQUEST_HH__ 35802SN/A#define __MEM_REQUEST_HH__ 361310SN/A 371310SN/A#include "targetarch/isa_traits.hh" 38802SN/A 39909SN/Aclass Request; 40909SN/Aclass CpuRequest; 414762Snate@binkert.org 422257SN/Atypedef Request* RequestPtr; 43802SN/Atypedef CpuRequest* CpuRequestPtr; 44802SN/A 45802SN/A/** The request is a Load locked/store conditional. */ 46802SN/Aconst unsigned LOCKED = 0x001; 47802SN/A/** The virtual address is also the physical address. */ 48802SN/Aconst unsigned PHYSICAL = 0x002; 492539SN/A/** The request is an ALPHA VPTE pal access (hw_ld). */ 50802SN/Aconst unsigned VPTE = 0x004; 51802SN/A/** Use the alternate mode bits in ALPHA. */ 522539SN/Aconst unsigned ALTMODE = 0x008; 53802SN/A/** The request is to an uncacheable address. */ 542539SN/Aconst unsigned UNCACHEABLE = 0x010; 554762Snate@binkert.org/** The request should not cause a page fault. */ 564762Snate@binkert.orgconst unsigned NO_FAULT = 0x020; 574762Snate@binkert.org 584762Snate@binkert.orgclass Request 594762Snate@binkert.org{ 602539SN/A //@todo Make Accesor functions, make these private. 614762Snate@binkert.org public: 624762Snate@binkert.org /** The physical address of the request. */ 63802SN/A Addr paddr; 64802SN/A 65885SN/A /** whether this req came from the CPU or not **DO we need this??***/ 66885SN/A bool nicReq; 672539SN/A 68885SN/A /** The size of the request. */ 69885SN/A int size; 702539SN/A 71802SN/A /** The time this request was started. Used to calculate latencies. */ 723349Sbinkertn@umich.edu Tick time; 733349Sbinkertn@umich.edu 74802SN/A /** Destination address if this is a block copy. */ 75802SN/A Addr copyDest; 761310SN/A 77 uint32_t flags; 78}; 79 80class CpuRequest : public Request 81{ 82 //@todo Make Accesor functions, make these private. 83 public: 84 /** The virtual address of the request. */ 85 Addr vaddr; 86 87 /** The address space ID. */ 88 int asid; 89 90 /** The return value of store conditional. */ 91 uint64_t scResult; 92 93 /** The cpu number for statistics. */ 94 int cpuNum; 95 96 /** The requesting thread id. */ 97 int threadNum; 98 99 /** program counter of initiating access; for tracing/debugging */ 100 Addr pc; 101}; 102 103#endif // __MEM_REQUEST_HH__ 104