request.hh revision 12766
12381SN/A/* 212346Snikos.nikoleris@arm.com * Copyright (c) 2012-2013,2017 ARM Limited 39332Sdam.sunwoo@arm.com * All rights reserved 49332Sdam.sunwoo@arm.com * 59332Sdam.sunwoo@arm.com * The license below extends only to copyright in the software and shall 69332Sdam.sunwoo@arm.com * not be construed as granting a license to any other intellectual 79332Sdam.sunwoo@arm.com * property including but not limited to intellectual property relating 89332Sdam.sunwoo@arm.com * to a hardware implementation of the functionality of the software 99332Sdam.sunwoo@arm.com * licensed hereunder. You may use the software subject to the license 109332Sdam.sunwoo@arm.com * terms below provided that you ensure that this notice is replicated 119332Sdam.sunwoo@arm.com * unmodified and in its entirety in all distributions of the software, 129332Sdam.sunwoo@arm.com * modified or unmodified, in source code or in binary form. 139332Sdam.sunwoo@arm.com * 142381SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 1510975Sdavid.hashe@amd.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162381SN/A * All rights reserved. 172381SN/A * 182381SN/A * Redistribution and use in source and binary forms, with or without 192381SN/A * modification, are permitted provided that the following conditions are 202381SN/A * met: redistributions of source code must retain the above copyright 212381SN/A * notice, this list of conditions and the following disclaimer; 222381SN/A * redistributions in binary form must reproduce the above copyright 232381SN/A * notice, this list of conditions and the following disclaimer in the 242381SN/A * documentation and/or other materials provided with the distribution; 252381SN/A * neither the name of the copyright holders nor the names of its 262381SN/A * contributors may be used to endorse or promote products derived from 272381SN/A * this software without specific prior written permission. 282381SN/A * 292381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 422665Ssaidi@eecs.umich.edu * Steve Reinhardt 432665Ssaidi@eecs.umich.edu * Ali Saidi 442381SN/A */ 452381SN/A 462381SN/A/** 472982Sstever@eecs.umich.edu * @file 482982Sstever@eecs.umich.edu * Declaration of a request, the overall memory request consisting of 492381SN/A the parts of the request that are persistent throughout the transaction. 502381SN/A */ 512381SN/A 522381SN/A#ifndef __MEM_REQUEST_HH__ 532381SN/A#define __MEM_REQUEST_HH__ 542381SN/A 555735Snate@binkert.org#include <cassert> 568833Sdam.sunwoo@arm.com#include <climits> 575735Snate@binkert.org 585735Snate@binkert.org#include "base/flags.hh" 5912334Sgabeblack@google.com#include "base/logging.hh" 606214Snate@binkert.org#include "base/types.hh" 6111248Sradhika.jagtap@ARM.com#include "cpu/inst_seq.hh" 624167Sbinkertn@umich.edu#include "sim/core.hh" 632394SN/A 649332Sdam.sunwoo@arm.com/** 659332Sdam.sunwoo@arm.com * Special TaskIds that are used for per-context-switch stats dumps 669332Sdam.sunwoo@arm.com * and Cache Occupancy. Having too many tasks seems to be a problem 679332Sdam.sunwoo@arm.com * with vector stats. 1024 seems to be a reasonable number that 689332Sdam.sunwoo@arm.com * doesn't cause a problem with stats and is large enough to realistic 699332Sdam.sunwoo@arm.com * benchmarks (Linux/Android boot, BBench, etc.) 709332Sdam.sunwoo@arm.com */ 719332Sdam.sunwoo@arm.com 729332Sdam.sunwoo@arm.comnamespace ContextSwitchTaskId { 739332Sdam.sunwoo@arm.com enum TaskId { 749332Sdam.sunwoo@arm.com MaxNormalTaskId = 1021, /* Maximum number of normal tasks */ 759332Sdam.sunwoo@arm.com Prefetcher = 1022, /* For cache lines brought in by prefetcher */ 769332Sdam.sunwoo@arm.com DMA = 1023, /* Mostly Table Walker */ 779332Sdam.sunwoo@arm.com Unknown = 1024, 789332Sdam.sunwoo@arm.com NumTaskId 799332Sdam.sunwoo@arm.com }; 809332Sdam.sunwoo@arm.com} 819332Sdam.sunwoo@arm.com 822394SN/Aclass Request; 832394SN/A 8412749Sgiacomo.travaglini@arm.comtypedef std::shared_ptr<Request> RequestPtr; 858832SAli.Saidi@ARM.comtypedef uint16_t MasterID; 862394SN/A 879044SAli.Saidi@ARM.comclass Request 882381SN/A{ 895735Snate@binkert.org public: 9012346Snikos.nikoleris@arm.com typedef uint64_t FlagsType; 919912Sandreas@sandberg.pp.se typedef uint8_t ArchFlagsType; 925735Snate@binkert.org typedef ::Flags<FlagsType> Flags; 935735Snate@binkert.org 9410882Sandreas.hansson@arm.com enum : FlagsType { 9510882Sandreas.hansson@arm.com /** 9610882Sandreas.hansson@arm.com * Architecture specific flags. 9710882Sandreas.hansson@arm.com * 9810882Sandreas.hansson@arm.com * These bits int the flag field are reserved for 9910882Sandreas.hansson@arm.com * architecture-specific code. For example, SPARC uses them to 10010882Sandreas.hansson@arm.com * represent ASIs. 10110882Sandreas.hansson@arm.com */ 10211003Sandreas.hansson@arm.com ARCH_BITS = 0x000000FF, 10310882Sandreas.hansson@arm.com /** The request was an instruction fetch. */ 10411003Sandreas.hansson@arm.com INST_FETCH = 0x00000100, 10510882Sandreas.hansson@arm.com /** The virtual address is also the physical address. */ 10611003Sandreas.hansson@arm.com PHYSICAL = 0x00000200, 10710882Sandreas.hansson@arm.com /** 10810882Sandreas.hansson@arm.com * The request is to an uncacheable address. 10910882Sandreas.hansson@arm.com * 11010882Sandreas.hansson@arm.com * @note Uncacheable accesses may be reordered by CPU models. The 11110882Sandreas.hansson@arm.com * STRICT_ORDER flag should be set if such reordering is 11210882Sandreas.hansson@arm.com * undesirable. 11310882Sandreas.hansson@arm.com */ 11411003Sandreas.hansson@arm.com UNCACHEABLE = 0x00000400, 11510882Sandreas.hansson@arm.com /** 11610882Sandreas.hansson@arm.com * The request is required to be strictly ordered by <i>CPU 11710882Sandreas.hansson@arm.com * models</i> and is non-speculative. 11810882Sandreas.hansson@arm.com * 11910882Sandreas.hansson@arm.com * A strictly ordered request is guaranteed to never be 12010882Sandreas.hansson@arm.com * re-ordered or executed speculatively by a CPU model. The 12110882Sandreas.hansson@arm.com * memory system may still reorder requests in caches unless 12210882Sandreas.hansson@arm.com * the UNCACHEABLE flag is set as well. 12310882Sandreas.hansson@arm.com */ 12411003Sandreas.hansson@arm.com STRICT_ORDER = 0x00000800, 12510882Sandreas.hansson@arm.com /** This request is to a memory mapped register. */ 12611003Sandreas.hansson@arm.com MMAPPED_IPR = 0x00002000, 12710882Sandreas.hansson@arm.com /** This request is made in privileged mode. */ 12811003Sandreas.hansson@arm.com PRIVILEGED = 0x00008000, 1296133Ssteve.reinhardt@amd.com 13010882Sandreas.hansson@arm.com /** 13110882Sandreas.hansson@arm.com * This is a write that is targeted and zeroing an entire 13210882Sandreas.hansson@arm.com * cache block. There is no need for a read/modify/write 13310882Sandreas.hansson@arm.com */ 13411003Sandreas.hansson@arm.com CACHE_BLOCK_ZERO = 0x00010000, 13510031SAli.Saidi@ARM.com 13610882Sandreas.hansson@arm.com /** The request should not cause a memory access. */ 13711003Sandreas.hansson@arm.com NO_ACCESS = 0x00080000, 13810882Sandreas.hansson@arm.com /** 13910882Sandreas.hansson@arm.com * This request will lock or unlock the accessed memory. When 14010882Sandreas.hansson@arm.com * used with a load, the access locks the particular chunk of 14110882Sandreas.hansson@arm.com * memory. When used with a store, it unlocks. The rule is 14210882Sandreas.hansson@arm.com * that locked accesses have to be made up of a locked load, 14310882Sandreas.hansson@arm.com * some operation on the data, and then a locked store. 14410882Sandreas.hansson@arm.com */ 14511003Sandreas.hansson@arm.com LOCKED_RMW = 0x00100000, 14610882Sandreas.hansson@arm.com /** The request is a Load locked/store conditional. */ 14711003Sandreas.hansson@arm.com LLSC = 0x00200000, 14810882Sandreas.hansson@arm.com /** This request is for a memory swap. */ 14911003Sandreas.hansson@arm.com MEM_SWAP = 0x00400000, 15011003Sandreas.hansson@arm.com MEM_SWAP_COND = 0x00800000, 1516133Ssteve.reinhardt@amd.com 15210882Sandreas.hansson@arm.com /** The request is a prefetch. */ 15311003Sandreas.hansson@arm.com PREFETCH = 0x01000000, 15410882Sandreas.hansson@arm.com /** The request should be prefetched into the exclusive state. */ 15511003Sandreas.hansson@arm.com PF_EXCLUSIVE = 0x02000000, 15610882Sandreas.hansson@arm.com /** The request should be marked as LRU. */ 15711003Sandreas.hansson@arm.com EVICT_NEXT = 0x04000000, 15811269Sdavid.hashe@amd.com /** The request should be marked with ACQUIRE. */ 15911269Sdavid.hashe@amd.com ACQUIRE = 0x00020000, 16011269Sdavid.hashe@amd.com /** The request should be marked with RELEASE. */ 16111269Sdavid.hashe@amd.com RELEASE = 0x00040000, 1625735Snate@binkert.org 16311306Santhony.gutierrez@amd.com /** The request is an atomic that returns data. */ 16411306Santhony.gutierrez@amd.com ATOMIC_RETURN_OP = 0x40000000, 16511306Santhony.gutierrez@amd.com /** The request is an atomic that does not return data. */ 16611306Santhony.gutierrez@amd.com ATOMIC_NO_RETURN_OP = 0x80000000, 16711306Santhony.gutierrez@amd.com 16811305Sblake.hechtman@amd.com /** The request should be marked with KERNEL. 16911305Sblake.hechtman@amd.com * Used to indicate the synchronization associated with a GPU kernel 17011305Sblake.hechtman@amd.com * launch or completion. 17111305Sblake.hechtman@amd.com */ 17211305Sblake.hechtman@amd.com KERNEL = 0x00001000, 17311305Sblake.hechtman@amd.com 17410882Sandreas.hansson@arm.com /** 17510882Sandreas.hansson@arm.com * The request should be handled by the generic IPR code (only 17610882Sandreas.hansson@arm.com * valid together with MMAPPED_IPR) 17710882Sandreas.hansson@arm.com */ 17811003Sandreas.hansson@arm.com GENERIC_IPR = 0x08000000, 1799911Sandreas@sandberg.pp.se 18010882Sandreas.hansson@arm.com /** The request targets the secure memory space. */ 18111003Sandreas.hansson@arm.com SECURE = 0x10000000, 18210882Sandreas.hansson@arm.com /** The request is a page table walk */ 18311003Sandreas.hansson@arm.com PT_WALK = 0x20000000, 18410028SGiacomo.Gabrielli@arm.com 18512347Snikos.nikoleris@arm.com /** The request invalidates a memory location */ 18612347Snikos.nikoleris@arm.com INVALIDATE = 0x0000000100000000, 18712347Snikos.nikoleris@arm.com /** The request cleans a memory location */ 18812347Snikos.nikoleris@arm.com CLEAN = 0x0000000200000000, 18912347Snikos.nikoleris@arm.com 19012346Snikos.nikoleris@arm.com /** The request targets the point of unification */ 19112346Snikos.nikoleris@arm.com DST_POU = 0x0000001000000000, 19212346Snikos.nikoleris@arm.com 19312346Snikos.nikoleris@arm.com /** The request targets the point of coherence */ 19412346Snikos.nikoleris@arm.com DST_POC = 0x0000002000000000, 19512346Snikos.nikoleris@arm.com 19612346Snikos.nikoleris@arm.com /** Bits to define the destination of a request */ 19712346Snikos.nikoleris@arm.com DST_BITS = 0x0000003000000000, 19812346Snikos.nikoleris@arm.com 19910882Sandreas.hansson@arm.com /** 20010882Sandreas.hansson@arm.com * These flags are *not* cleared when a Request object is 20110882Sandreas.hansson@arm.com * reused (assigned a new address). 20210882Sandreas.hansson@arm.com */ 20310882Sandreas.hansson@arm.com STICKY_FLAGS = INST_FETCH 20410882Sandreas.hansson@arm.com }; 20512355Snikos.nikoleris@arm.com static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO | 20612355Snikos.nikoleris@arm.com CLEAN | INVALIDATE; 2076104Ssteve.reinhardt@amd.com 20810882Sandreas.hansson@arm.com /** Master Ids that are statically allocated 2098832SAli.Saidi@ARM.com * @{*/ 21010882Sandreas.hansson@arm.com enum : MasterID { 21110882Sandreas.hansson@arm.com /** This master id is used for writeback requests by the caches */ 21210882Sandreas.hansson@arm.com wbMasterId = 0, 21310882Sandreas.hansson@arm.com /** 21410882Sandreas.hansson@arm.com * This master id is used for functional requests that 21510882Sandreas.hansson@arm.com * don't come from a particular device 21610882Sandreas.hansson@arm.com */ 21710882Sandreas.hansson@arm.com funcMasterId = 1, 21810882Sandreas.hansson@arm.com /** This master id is used for message signaled interrupts */ 21910882Sandreas.hansson@arm.com intMasterId = 2, 22010882Sandreas.hansson@arm.com /** 22110882Sandreas.hansson@arm.com * Invalid master id for assertion checking only. It is 22210882Sandreas.hansson@arm.com * invalid behavior to ever send this id as part of a request. 22310882Sandreas.hansson@arm.com */ 22410882Sandreas.hansson@arm.com invldMasterId = std::numeric_limits<MasterID>::max() 22510882Sandreas.hansson@arm.com }; 2268832SAli.Saidi@ARM.com /** @} */ 2278832SAli.Saidi@ARM.com 22811305Sblake.hechtman@amd.com typedef uint32_t MemSpaceConfigFlagsType; 22911305Sblake.hechtman@amd.com typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags; 23011305Sblake.hechtman@amd.com 23111305Sblake.hechtman@amd.com enum : MemSpaceConfigFlagsType { 23211305Sblake.hechtman@amd.com /** Has a synchronization scope been set? */ 23311305Sblake.hechtman@amd.com SCOPE_VALID = 0x00000001, 23411305Sblake.hechtman@amd.com /** Access has Wavefront scope visibility */ 23511305Sblake.hechtman@amd.com WAVEFRONT_SCOPE = 0x00000002, 23611305Sblake.hechtman@amd.com /** Access has Workgroup scope visibility */ 23711305Sblake.hechtman@amd.com WORKGROUP_SCOPE = 0x00000004, 23811305Sblake.hechtman@amd.com /** Access has Device (e.g., GPU) scope visibility */ 23911305Sblake.hechtman@amd.com DEVICE_SCOPE = 0x00000008, 24011305Sblake.hechtman@amd.com /** Access has System (e.g., CPU + GPU) scope visibility */ 24111305Sblake.hechtman@amd.com SYSTEM_SCOPE = 0x00000010, 24211305Sblake.hechtman@amd.com 24311305Sblake.hechtman@amd.com /** Global Segment */ 24411305Sblake.hechtman@amd.com GLOBAL_SEGMENT = 0x00000020, 24511305Sblake.hechtman@amd.com /** Group Segment */ 24611305Sblake.hechtman@amd.com GROUP_SEGMENT = 0x00000040, 24711305Sblake.hechtman@amd.com /** Private Segment */ 24811305Sblake.hechtman@amd.com PRIVATE_SEGMENT = 0x00000080, 24911305Sblake.hechtman@amd.com /** Kergarg Segment */ 25011305Sblake.hechtman@amd.com KERNARG_SEGMENT = 0x00000100, 25111305Sblake.hechtman@amd.com /** Readonly Segment */ 25211305Sblake.hechtman@amd.com READONLY_SEGMENT = 0x00000200, 25311305Sblake.hechtman@amd.com /** Spill Segment */ 25411305Sblake.hechtman@amd.com SPILL_SEGMENT = 0x00000400, 25511305Sblake.hechtman@amd.com /** Arg Segment */ 25611305Sblake.hechtman@amd.com ARG_SEGMENT = 0x00000800, 25711305Sblake.hechtman@amd.com }; 25811305Sblake.hechtman@amd.com 2595735Snate@binkert.org private: 2606104Ssteve.reinhardt@amd.com typedef uint8_t PrivateFlagsType; 2616104Ssteve.reinhardt@amd.com typedef ::Flags<PrivateFlagsType> PrivateFlags; 2625735Snate@binkert.org 26310882Sandreas.hansson@arm.com enum : PrivateFlagsType { 26410882Sandreas.hansson@arm.com /** Whether or not the size is valid. */ 26510882Sandreas.hansson@arm.com VALID_SIZE = 0x00000001, 26610882Sandreas.hansson@arm.com /** Whether or not paddr is valid (has been written yet). */ 26710882Sandreas.hansson@arm.com VALID_PADDR = 0x00000002, 26810882Sandreas.hansson@arm.com /** Whether or not the vaddr & asid are valid. */ 26910882Sandreas.hansson@arm.com VALID_VADDR = 0x00000004, 27011248Sradhika.jagtap@ARM.com /** Whether or not the instruction sequence number is valid. */ 27111248Sradhika.jagtap@ARM.com VALID_INST_SEQ_NUM = 0x00000008, 27210882Sandreas.hansson@arm.com /** Whether or not the pc is valid. */ 27310882Sandreas.hansson@arm.com VALID_PC = 0x00000010, 27410882Sandreas.hansson@arm.com /** Whether or not the context ID is valid. */ 27510882Sandreas.hansson@arm.com VALID_CONTEXT_ID = 0x00000020, 27610882Sandreas.hansson@arm.com /** Whether or not the sc result is valid. */ 27710882Sandreas.hansson@arm.com VALID_EXTRA_DATA = 0x00000080, 27810882Sandreas.hansson@arm.com /** 27910882Sandreas.hansson@arm.com * These flags are *not* cleared when a Request object is reused 28010882Sandreas.hansson@arm.com * (assigned a new address). 28110882Sandreas.hansson@arm.com */ 28211435Smitch.hayenga@arm.com STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID 28310882Sandreas.hansson@arm.com }; 2845735Snate@binkert.org 2852663Sstever@eecs.umich.edu private: 28610653Sandreas.hansson@arm.com 28710653Sandreas.hansson@arm.com /** 28810653Sandreas.hansson@arm.com * Set up a physical (e.g. device) request in a previously 28910653Sandreas.hansson@arm.com * allocated Request object. 29010653Sandreas.hansson@arm.com */ 29110653Sandreas.hansson@arm.com void 29210653Sandreas.hansson@arm.com setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 29310653Sandreas.hansson@arm.com { 29410653Sandreas.hansson@arm.com _paddr = paddr; 29510653Sandreas.hansson@arm.com _size = size; 29610653Sandreas.hansson@arm.com _time = time; 29710653Sandreas.hansson@arm.com _masterId = mid; 29810653Sandreas.hansson@arm.com _flags.clear(~STICKY_FLAGS); 29910653Sandreas.hansson@arm.com _flags.set(flags); 30010653Sandreas.hansson@arm.com privateFlags.clear(~STICKY_PRIVATE_FLAGS); 30110653Sandreas.hansson@arm.com privateFlags.set(VALID_PADDR|VALID_SIZE); 30210653Sandreas.hansson@arm.com depth = 0; 30310653Sandreas.hansson@arm.com accessDelta = 0; 30410653Sandreas.hansson@arm.com //translateDelta = 0; 30510653Sandreas.hansson@arm.com } 30610653Sandreas.hansson@arm.com 3072663Sstever@eecs.umich.edu /** 3082663Sstever@eecs.umich.edu * The physical address of the request. Valid only if validPaddr 3095735Snate@binkert.org * is set. 3105735Snate@binkert.org */ 3116427Ssteve.reinhardt@amd.com Addr _paddr; 3122532SN/A 3132663Sstever@eecs.umich.edu /** 3142663Sstever@eecs.umich.edu * The size of the request. This field must be set when vaddr or 3152663Sstever@eecs.umich.edu * paddr is written via setVirt() or setPhys(), so it is always 3165735Snate@binkert.org * valid as long as one of the address fields is valid. 3175735Snate@binkert.org */ 31810653Sandreas.hansson@arm.com unsigned _size; 3192395SN/A 3208832SAli.Saidi@ARM.com /** The requestor ID which is unique in the system for all ports 3218832SAli.Saidi@ARM.com * that are capable of issuing a transaction 3228832SAli.Saidi@ARM.com */ 3238832SAli.Saidi@ARM.com MasterID _masterId; 3248832SAli.Saidi@ARM.com 3252532SN/A /** Flag structure for the request. */ 3266427Ssteve.reinhardt@amd.com Flags _flags; 3272384SN/A 32811305Sblake.hechtman@amd.com /** Memory space configuraiton flag structure for the request. */ 32911305Sblake.hechtman@amd.com MemSpaceConfigFlags _memSpaceConfigFlags; 33011305Sblake.hechtman@amd.com 3316104Ssteve.reinhardt@amd.com /** Private flags for field validity checking. */ 3326104Ssteve.reinhardt@amd.com PrivateFlags privateFlags; 3336104Ssteve.reinhardt@amd.com 3342663Sstever@eecs.umich.edu /** 3352663Sstever@eecs.umich.edu * The time this request was started. Used to calculate 3367823Ssteve.reinhardt@amd.com * latencies. This field is set to curTick() any time paddr or vaddr 3375735Snate@binkert.org * is written. 3385735Snate@binkert.org */ 3396223Snate@binkert.org Tick _time; 3402384SN/A 34110024Sdam.sunwoo@arm.com /** 34210024Sdam.sunwoo@arm.com * The task id associated with this request 34310024Sdam.sunwoo@arm.com */ 34410024Sdam.sunwoo@arm.com uint32_t _taskId; 34510024Sdam.sunwoo@arm.com 3462384SN/A /** The address space ID. */ 3476427Ssteve.reinhardt@amd.com int _asid; 3483806Ssaidi@eecs.umich.edu 3492663Sstever@eecs.umich.edu /** The virtual address of the request. */ 3506427Ssteve.reinhardt@amd.com Addr _vaddr; 3512384SN/A 3525735Snate@binkert.org /** 3535735Snate@binkert.org * Extra data for the request, such as the return value of 3544040Ssaidi@eecs.umich.edu * store conditional or the compare value for a CAS. */ 3556427Ssteve.reinhardt@amd.com uint64_t _extraData; 3562384SN/A 35711435Smitch.hayenga@arm.com /** The context ID (for statistics, locks, and wakeups). */ 35811005Sandreas.sandberg@arm.com ContextID _contextId; 3592384SN/A 3602381SN/A /** program counter of initiating access; for tracing/debugging */ 3616427Ssteve.reinhardt@amd.com Addr _pc; 3622663Sstever@eecs.umich.edu 36311248Sradhika.jagtap@ARM.com /** Sequence number of the instruction that creates the request */ 36411253Sradhika.jagtap@ARM.com InstSeqNum _reqInstSeqNum; 36511248Sradhika.jagtap@ARM.com 36611306Santhony.gutierrez@amd.com /** A pointer to an atomic operation */ 36711306Santhony.gutierrez@amd.com AtomicOpFunctor *atomicOpFunctor; 36811306Santhony.gutierrez@amd.com 3692532SN/A public: 37010653Sandreas.hansson@arm.com 37110653Sandreas.hansson@arm.com /** 37210653Sandreas.hansson@arm.com * Minimal constructor. No fields are initialized. (Note that 37310653Sandreas.hansson@arm.com * _flags and privateFlags are cleared by Flags default 37410653Sandreas.hansson@arm.com * constructor.) 3756427Ssteve.reinhardt@amd.com */ 3762663Sstever@eecs.umich.edu Request() 37710360Sandreas.hansson@arm.com : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 37810360Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 37911435Smitch.hayenga@arm.com _extraData(0), _contextId(0), _pc(0), 38011306Santhony.gutierrez@amd.com _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 38111306Santhony.gutierrez@amd.com accessDelta(0), depth(0) 3822663Sstever@eecs.umich.edu {} 3832532SN/A 38411248Sradhika.jagtap@ARM.com Request(Addr paddr, unsigned size, Flags flags, MasterID mid, 38511435Smitch.hayenga@arm.com InstSeqNum seq_num, ContextID cid) 38611248Sradhika.jagtap@ARM.com : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 38711248Sradhika.jagtap@ARM.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 38811435Smitch.hayenga@arm.com _extraData(0), _contextId(0), _pc(0), 38911306Santhony.gutierrez@amd.com _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0), 39011306Santhony.gutierrez@amd.com accessDelta(0), depth(0) 39111248Sradhika.jagtap@ARM.com { 39211248Sradhika.jagtap@ARM.com setPhys(paddr, size, flags, mid, curTick()); 39311435Smitch.hayenga@arm.com setContext(cid); 39411248Sradhika.jagtap@ARM.com privateFlags.set(VALID_INST_SEQ_NUM); 39511248Sradhika.jagtap@ARM.com } 39611248Sradhika.jagtap@ARM.com 3972663Sstever@eecs.umich.edu /** 3982663Sstever@eecs.umich.edu * Constructor for physical (e.g. device) requests. Initializes 3997823Ssteve.reinhardt@amd.com * just physical address, size, flags, and timestamp (to curTick()). 40010653Sandreas.hansson@arm.com * These fields are adequate to perform a request. 4015735Snate@binkert.org */ 40210653Sandreas.hansson@arm.com Request(Addr paddr, unsigned size, Flags flags, MasterID mid) 40310360Sandreas.hansson@arm.com : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 40410360Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 40511435Smitch.hayenga@arm.com _extraData(0), _contextId(0), _pc(0), 40611306Santhony.gutierrez@amd.com _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 40711306Santhony.gutierrez@amd.com accessDelta(0), depth(0) 4085735Snate@binkert.org { 40910653Sandreas.hansson@arm.com setPhys(paddr, size, flags, mid, curTick()); 4105735Snate@binkert.org } 4112532SN/A 41210653Sandreas.hansson@arm.com Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 41310360Sandreas.hansson@arm.com : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 41410360Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 41511435Smitch.hayenga@arm.com _extraData(0), _contextId(0), _pc(0), 41611306Santhony.gutierrez@amd.com _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 41711306Santhony.gutierrez@amd.com accessDelta(0), depth(0) 4186223Snate@binkert.org { 4198832SAli.Saidi@ARM.com setPhys(paddr, size, flags, mid, time); 4206223Snate@binkert.org } 4216223Snate@binkert.org 42210653Sandreas.hansson@arm.com Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time, 42310653Sandreas.hansson@arm.com Addr pc) 42410360Sandreas.hansson@arm.com : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 42510360Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 42611435Smitch.hayenga@arm.com _extraData(0), _contextId(0), _pc(pc), 42711306Santhony.gutierrez@amd.com _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 42811306Santhony.gutierrez@amd.com accessDelta(0), depth(0) 4296899SBrad.Beckmann@amd.com { 4308832SAli.Saidi@ARM.com setPhys(paddr, size, flags, mid, time); 4316899SBrad.Beckmann@amd.com privateFlags.set(VALID_PC); 4326899SBrad.Beckmann@amd.com } 4336899SBrad.Beckmann@amd.com 43410653Sandreas.hansson@arm.com Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 43511435Smitch.hayenga@arm.com Addr pc, ContextID cid) 43610360Sandreas.hansson@arm.com : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 43710360Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 43811435Smitch.hayenga@arm.com _extraData(0), _contextId(0), _pc(0), 43911306Santhony.gutierrez@amd.com _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 44011306Santhony.gutierrez@amd.com accessDelta(0), depth(0) 4412669Sktlim@umich.edu { 4428832SAli.Saidi@ARM.com setVirt(asid, vaddr, size, flags, mid, pc); 44311435Smitch.hayenga@arm.com setContext(cid); 4442669Sktlim@umich.edu } 4452669Sktlim@umich.edu 44611435Smitch.hayenga@arm.com Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 44711435Smitch.hayenga@arm.com Addr pc, ContextID cid, AtomicOpFunctor *atomic_op) 44811306Santhony.gutierrez@amd.com { 44912766Sqtt2@cornell.edu setVirt(asid, vaddr, size, flags, mid, pc, atomic_op); 45011435Smitch.hayenga@arm.com setContext(cid); 45111306Santhony.gutierrez@amd.com } 45211306Santhony.gutierrez@amd.com 45312766Sqtt2@cornell.edu Request(const Request& other) 45412766Sqtt2@cornell.edu : _paddr(other._paddr), _size(other._size), 45512766Sqtt2@cornell.edu _masterId(other._masterId), 45612766Sqtt2@cornell.edu _flags(other._flags), 45712766Sqtt2@cornell.edu _memSpaceConfigFlags(other._memSpaceConfigFlags), 45812766Sqtt2@cornell.edu privateFlags(other.privateFlags), 45912766Sqtt2@cornell.edu _time(other._time), 46012766Sqtt2@cornell.edu _taskId(other._taskId), _asid(other._asid), _vaddr(other._vaddr), 46112766Sqtt2@cornell.edu _extraData(other._extraData), _contextId(other._contextId), 46212766Sqtt2@cornell.edu _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum), 46312766Sqtt2@cornell.edu translateDelta(other.translateDelta), 46412766Sqtt2@cornell.edu accessDelta(other.accessDelta), depth(other.depth) 46512766Sqtt2@cornell.edu { 46612766Sqtt2@cornell.edu if (other.atomicOpFunctor) 46712766Sqtt2@cornell.edu atomicOpFunctor = (other.atomicOpFunctor)->clone(); 46812766Sqtt2@cornell.edu else 46912766Sqtt2@cornell.edu atomicOpFunctor = nullptr; 47012766Sqtt2@cornell.edu } 47112766Sqtt2@cornell.edu 47211306Santhony.gutierrez@amd.com ~Request() 47311306Santhony.gutierrez@amd.com { 47411306Santhony.gutierrez@amd.com if (hasAtomicOpFunctor()) { 47511306Santhony.gutierrez@amd.com delete atomicOpFunctor; 47611306Santhony.gutierrez@amd.com } 47711306Santhony.gutierrez@amd.com } 4784610Ssaidi@eecs.umich.edu 4792663Sstever@eecs.umich.edu /** 48011435Smitch.hayenga@arm.com * Set up Context numbers. 4815735Snate@binkert.org */ 4825735Snate@binkert.org void 48311435Smitch.hayenga@arm.com setContext(ContextID context_id) 4842663Sstever@eecs.umich.edu { 4855735Snate@binkert.org _contextId = context_id; 48611435Smitch.hayenga@arm.com privateFlags.set(VALID_CONTEXT_ID); 4872663Sstever@eecs.umich.edu } 4882532SN/A 4892663Sstever@eecs.umich.edu /** 4902663Sstever@eecs.umich.edu * Set up a virtual (e.g., CPU) request in a previously 4915735Snate@binkert.org * allocated Request object. 4925735Snate@binkert.org */ 4935735Snate@binkert.org void 49410653Sandreas.hansson@arm.com setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 49512766Sqtt2@cornell.edu Addr pc, AtomicOpFunctor *amo_op = nullptr) 4962663Sstever@eecs.umich.edu { 4976427Ssteve.reinhardt@amd.com _asid = asid; 4986427Ssteve.reinhardt@amd.com _vaddr = vaddr; 4996427Ssteve.reinhardt@amd.com _size = size; 5008832SAli.Saidi@ARM.com _masterId = mid; 5016427Ssteve.reinhardt@amd.com _pc = pc; 5027823Ssteve.reinhardt@amd.com _time = curTick(); 5035735Snate@binkert.org 5046427Ssteve.reinhardt@amd.com _flags.clear(~STICKY_FLAGS); 5056427Ssteve.reinhardt@amd.com _flags.set(flags); 5066104Ssteve.reinhardt@amd.com privateFlags.clear(~STICKY_PRIVATE_FLAGS); 5076104Ssteve.reinhardt@amd.com privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC); 50810020Smatt.horsnell@ARM.com depth = 0; 50910020Smatt.horsnell@ARM.com accessDelta = 0; 51010020Smatt.horsnell@ARM.com translateDelta = 0; 51112766Sqtt2@cornell.edu atomicOpFunctor = amo_op; 5122663Sstever@eecs.umich.edu } 5132532SN/A 5145735Snate@binkert.org /** 5159760Sandreas@sandberg.pp.se * Set just the physical address. This usually used to record the 5169760Sandreas@sandberg.pp.se * result of a translation. However, when using virtualized CPUs 5179760Sandreas@sandberg.pp.se * setPhys() is sometimes called to finalize a physical address 5189760Sandreas@sandberg.pp.se * without a virtual address, so we can't check if the virtual 5199760Sandreas@sandberg.pp.se * address is valid. 5202663Sstever@eecs.umich.edu */ 5215735Snate@binkert.org void 5226427Ssteve.reinhardt@amd.com setPaddr(Addr paddr) 5232663Sstever@eecs.umich.edu { 5246427Ssteve.reinhardt@amd.com _paddr = paddr; 5256104Ssteve.reinhardt@amd.com privateFlags.set(VALID_PADDR); 5262663Sstever@eecs.umich.edu } 5272532SN/A 5285735Snate@binkert.org /** 5295744Sgblack@eecs.umich.edu * Generate two requests as if this request had been split into two 5305744Sgblack@eecs.umich.edu * pieces. The original request can't have been translated already. 5315744Sgblack@eecs.umich.edu */ 5325744Sgblack@eecs.umich.edu void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2) 5335744Sgblack@eecs.umich.edu { 5346104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_VADDR)); 5356104Ssteve.reinhardt@amd.com assert(privateFlags.noneSet(VALID_PADDR)); 5366427Ssteve.reinhardt@amd.com assert(split_addr > _vaddr && split_addr < _vaddr + _size); 53712749Sgiacomo.travaglini@arm.com req1 = std::make_shared<Request>(*this); 53812749Sgiacomo.travaglini@arm.com req2 = std::make_shared<Request>(*this); 5396427Ssteve.reinhardt@amd.com req1->_size = split_addr - _vaddr; 5406427Ssteve.reinhardt@amd.com req2->_vaddr = split_addr; 5416427Ssteve.reinhardt@amd.com req2->_size = _size - req1->_size; 5425744Sgblack@eecs.umich.edu } 5435744Sgblack@eecs.umich.edu 5445744Sgblack@eecs.umich.edu /** 5455735Snate@binkert.org * Accessor for paddr. 5465735Snate@binkert.org */ 5476104Ssteve.reinhardt@amd.com bool 54810568Sandreas.hansson@arm.com hasPaddr() const 5496104Ssteve.reinhardt@amd.com { 5506104Ssteve.reinhardt@amd.com return privateFlags.isSet(VALID_PADDR); 5516104Ssteve.reinhardt@amd.com } 5526104Ssteve.reinhardt@amd.com 5535735Snate@binkert.org Addr 55410568Sandreas.hansson@arm.com getPaddr() const 5555735Snate@binkert.org { 5566104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_PADDR)); 5576427Ssteve.reinhardt@amd.com return _paddr; 5585735Snate@binkert.org } 5592663Sstever@eecs.umich.edu 5605735Snate@binkert.org /** 56110020Smatt.horsnell@ARM.com * Time for the TLB/table walker to successfully translate this request. 56210020Smatt.horsnell@ARM.com */ 56310020Smatt.horsnell@ARM.com Tick translateDelta; 56410020Smatt.horsnell@ARM.com 56510020Smatt.horsnell@ARM.com /** 56610020Smatt.horsnell@ARM.com * Access latency to complete this memory transaction not including 56710020Smatt.horsnell@ARM.com * translation time. 56810020Smatt.horsnell@ARM.com */ 56910020Smatt.horsnell@ARM.com Tick accessDelta; 57010020Smatt.horsnell@ARM.com 57110020Smatt.horsnell@ARM.com /** 57210020Smatt.horsnell@ARM.com * Level of the cache hierachy where this request was responded to 57310020Smatt.horsnell@ARM.com * (e.g. 0 = L1; 1 = L2). 57410020Smatt.horsnell@ARM.com */ 57510568Sandreas.hansson@arm.com mutable int depth; 57610020Smatt.horsnell@ARM.com 57710020Smatt.horsnell@ARM.com /** 5785735Snate@binkert.org * Accessor for size. 5795735Snate@binkert.org */ 5806104Ssteve.reinhardt@amd.com bool 58110568Sandreas.hansson@arm.com hasSize() const 5826104Ssteve.reinhardt@amd.com { 5836104Ssteve.reinhardt@amd.com return privateFlags.isSet(VALID_SIZE); 5846104Ssteve.reinhardt@amd.com } 5856104Ssteve.reinhardt@amd.com 58610755Sandreas.hansson@arm.com unsigned 58710568Sandreas.hansson@arm.com getSize() const 5885735Snate@binkert.org { 5896104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_SIZE)); 5906427Ssteve.reinhardt@amd.com return _size; 5915735Snate@binkert.org } 5925735Snate@binkert.org 5932663Sstever@eecs.umich.edu /** Accessor for time. */ 5945735Snate@binkert.org Tick 5956223Snate@binkert.org time() const 5965735Snate@binkert.org { 5976104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 5986223Snate@binkert.org return _time; 5996223Snate@binkert.org } 6006223Snate@binkert.org 60111306Santhony.gutierrez@amd.com /** 60211306Santhony.gutierrez@amd.com * Accessor for atomic-op functor. 60311306Santhony.gutierrez@amd.com */ 60411306Santhony.gutierrez@amd.com bool 60511306Santhony.gutierrez@amd.com hasAtomicOpFunctor() 60611306Santhony.gutierrez@amd.com { 60711306Santhony.gutierrez@amd.com return atomicOpFunctor != NULL; 60811306Santhony.gutierrez@amd.com } 60911306Santhony.gutierrez@amd.com 61011306Santhony.gutierrez@amd.com AtomicOpFunctor * 61111306Santhony.gutierrez@amd.com getAtomicOpFunctor() 61211306Santhony.gutierrez@amd.com { 61311306Santhony.gutierrez@amd.com assert(atomicOpFunctor != NULL); 61411306Santhony.gutierrez@amd.com return atomicOpFunctor; 61511306Santhony.gutierrez@amd.com } 61611306Santhony.gutierrez@amd.com 6172663Sstever@eecs.umich.edu /** Accessor for flags. */ 6185735Snate@binkert.org Flags 6195735Snate@binkert.org getFlags() 6205735Snate@binkert.org { 6216104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 6226427Ssteve.reinhardt@amd.com return _flags; 6235735Snate@binkert.org } 6245735Snate@binkert.org 6256428Ssteve.reinhardt@amd.com /** Note that unlike other accessors, this function sets *specific 62610882Sandreas.hansson@arm.com flags* (ORs them in); it does not assign its argument to the 62710882Sandreas.hansson@arm.com _flags field. Thus this method should rightly be called 62810882Sandreas.hansson@arm.com setFlags() and not just flags(). */ 6295735Snate@binkert.org void 6306427Ssteve.reinhardt@amd.com setFlags(Flags flags) 6315735Snate@binkert.org { 6326104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 6336427Ssteve.reinhardt@amd.com _flags.set(flags); 6345735Snate@binkert.org } 6355735Snate@binkert.org 63611305Sblake.hechtman@amd.com void 63711305Sblake.hechtman@amd.com setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags) 63811305Sblake.hechtman@amd.com { 63911305Sblake.hechtman@amd.com assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR)); 64011305Sblake.hechtman@amd.com _memSpaceConfigFlags.set(extraFlags); 64111305Sblake.hechtman@amd.com } 64211305Sblake.hechtman@amd.com 6432663Sstever@eecs.umich.edu /** Accessor function for vaddr.*/ 64410362Smitch.hayenga@arm.com bool 64510362Smitch.hayenga@arm.com hasVaddr() const 64610362Smitch.hayenga@arm.com { 64710362Smitch.hayenga@arm.com return privateFlags.isSet(VALID_VADDR); 64810362Smitch.hayenga@arm.com } 64910362Smitch.hayenga@arm.com 6505735Snate@binkert.org Addr 65110362Smitch.hayenga@arm.com getVaddr() const 6525735Snate@binkert.org { 6536104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_VADDR)); 6546427Ssteve.reinhardt@amd.com return _vaddr; 6555735Snate@binkert.org } 6562663Sstever@eecs.umich.edu 6578832SAli.Saidi@ARM.com /** Accesssor for the requestor id. */ 6588832SAli.Saidi@ARM.com MasterID 65910568Sandreas.hansson@arm.com masterId() const 6608832SAli.Saidi@ARM.com { 6618832SAli.Saidi@ARM.com return _masterId; 6628832SAli.Saidi@ARM.com } 6638832SAli.Saidi@ARM.com 66410024Sdam.sunwoo@arm.com uint32_t 66510024Sdam.sunwoo@arm.com taskId() const 66610024Sdam.sunwoo@arm.com { 66710024Sdam.sunwoo@arm.com return _taskId; 66810024Sdam.sunwoo@arm.com } 66910024Sdam.sunwoo@arm.com 67010024Sdam.sunwoo@arm.com void 67110024Sdam.sunwoo@arm.com taskId(uint32_t id) { 67210024Sdam.sunwoo@arm.com _taskId = id; 67310024Sdam.sunwoo@arm.com } 67410024Sdam.sunwoo@arm.com 6752663Sstever@eecs.umich.edu /** Accessor function for asid.*/ 6765735Snate@binkert.org int 67710568Sandreas.hansson@arm.com getAsid() const 6785735Snate@binkert.org { 6796104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_VADDR)); 6806427Ssteve.reinhardt@amd.com return _asid; 6815735Snate@binkert.org } 6822663Sstever@eecs.umich.edu 6838551Sdaniel.johnson@arm.com /** Accessor function for asid.*/ 6848551Sdaniel.johnson@arm.com void 6858551Sdaniel.johnson@arm.com setAsid(int asid) 6868551Sdaniel.johnson@arm.com { 6878551Sdaniel.johnson@arm.com _asid = asid; 6888551Sdaniel.johnson@arm.com } 6898551Sdaniel.johnson@arm.com 6909912Sandreas@sandberg.pp.se /** Accessor function for architecture-specific flags.*/ 6919912Sandreas@sandberg.pp.se ArchFlagsType 69210568Sandreas.hansson@arm.com getArchFlags() const 6935735Snate@binkert.org { 6949912Sandreas@sandberg.pp.se assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 6959912Sandreas@sandberg.pp.se return _flags & ARCH_BITS; 6965735Snate@binkert.org } 6973804Ssaidi@eecs.umich.edu 6982679Sktlim@umich.edu /** Accessor function to check if sc result is valid. */ 6995735Snate@binkert.org bool 70010568Sandreas.hansson@arm.com extraDataValid() const 7015735Snate@binkert.org { 7026104Ssteve.reinhardt@amd.com return privateFlags.isSet(VALID_EXTRA_DATA); 7035735Snate@binkert.org } 7045735Snate@binkert.org 7052663Sstever@eecs.umich.edu /** Accessor function for store conditional return value.*/ 7065735Snate@binkert.org uint64_t 7075735Snate@binkert.org getExtraData() const 7085735Snate@binkert.org { 7096104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_EXTRA_DATA)); 7106427Ssteve.reinhardt@amd.com return _extraData; 7115735Snate@binkert.org } 7125735Snate@binkert.org 7132663Sstever@eecs.umich.edu /** Accessor function for store conditional return value.*/ 7145735Snate@binkert.org void 7156427Ssteve.reinhardt@amd.com setExtraData(uint64_t extraData) 7165735Snate@binkert.org { 7176427Ssteve.reinhardt@amd.com _extraData = extraData; 7186104Ssteve.reinhardt@amd.com privateFlags.set(VALID_EXTRA_DATA); 7195735Snate@binkert.org } 7202663Sstever@eecs.umich.edu 7216010Ssteve.reinhardt@amd.com bool 7226010Ssteve.reinhardt@amd.com hasContextId() const 7236010Ssteve.reinhardt@amd.com { 7246104Ssteve.reinhardt@amd.com return privateFlags.isSet(VALID_CONTEXT_ID); 7256010Ssteve.reinhardt@amd.com } 7266010Ssteve.reinhardt@amd.com 7275714Shsul@eecs.umich.edu /** Accessor function for context ID.*/ 72811005Sandreas.sandberg@arm.com ContextID 7295735Snate@binkert.org contextId() const 7305735Snate@binkert.org { 7316104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_CONTEXT_ID)); 7325735Snate@binkert.org return _contextId; 7335735Snate@binkert.org } 7345735Snate@binkert.org 73510052Smitch.hayenga+gem5@gmail.com void 73610052Smitch.hayenga+gem5@gmail.com setPC(Addr pc) 73710052Smitch.hayenga+gem5@gmail.com { 73810052Smitch.hayenga+gem5@gmail.com privateFlags.set(VALID_PC); 73910052Smitch.hayenga+gem5@gmail.com _pc = pc; 74010052Smitch.hayenga+gem5@gmail.com } 74110052Smitch.hayenga+gem5@gmail.com 7425875Ssteve.reinhardt@amd.com bool 7435875Ssteve.reinhardt@amd.com hasPC() const 7445875Ssteve.reinhardt@amd.com { 7456104Ssteve.reinhardt@amd.com return privateFlags.isSet(VALID_PC); 7465875Ssteve.reinhardt@amd.com } 7475875Ssteve.reinhardt@amd.com 7486010Ssteve.reinhardt@amd.com /** Accessor function for pc.*/ 7495735Snate@binkert.org Addr 7505735Snate@binkert.org getPC() const 7515735Snate@binkert.org { 7526104Ssteve.reinhardt@amd.com assert(privateFlags.isSet(VALID_PC)); 7536427Ssteve.reinhardt@amd.com return _pc; 7545735Snate@binkert.org } 7552532SN/A 75610020Smatt.horsnell@ARM.com /** 75710020Smatt.horsnell@ARM.com * Increment/Get the depth at which this request is responded to. 75810020Smatt.horsnell@ARM.com * This currently happens when the request misses in any cache level. 75910020Smatt.horsnell@ARM.com */ 76010568Sandreas.hansson@arm.com void incAccessDepth() const { depth++; } 76110020Smatt.horsnell@ARM.com int getAccessDepth() const { return depth; } 76210020Smatt.horsnell@ARM.com 76310020Smatt.horsnell@ARM.com /** 76410020Smatt.horsnell@ARM.com * Set/Get the time taken for this request to be successfully translated. 76510020Smatt.horsnell@ARM.com */ 76610020Smatt.horsnell@ARM.com void setTranslateLatency() { translateDelta = curTick() - _time; } 76710020Smatt.horsnell@ARM.com Tick getTranslateLatency() const { return translateDelta; } 76810020Smatt.horsnell@ARM.com 76910020Smatt.horsnell@ARM.com /** 77010020Smatt.horsnell@ARM.com * Set/Get the time taken to complete this request's access, not including 77110020Smatt.horsnell@ARM.com * the time to successfully translate the request. 77210020Smatt.horsnell@ARM.com */ 77310020Smatt.horsnell@ARM.com void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; } 77410020Smatt.horsnell@ARM.com Tick getAccessLatency() const { return accessDelta; } 77510020Smatt.horsnell@ARM.com 77611248Sradhika.jagtap@ARM.com /** 77711248Sradhika.jagtap@ARM.com * Accessor for the sequence number of instruction that creates the 77811248Sradhika.jagtap@ARM.com * request. 77911248Sradhika.jagtap@ARM.com */ 78011248Sradhika.jagtap@ARM.com bool 78111248Sradhika.jagtap@ARM.com hasInstSeqNum() const 78211248Sradhika.jagtap@ARM.com { 78311248Sradhika.jagtap@ARM.com return privateFlags.isSet(VALID_INST_SEQ_NUM); 78411248Sradhika.jagtap@ARM.com } 78511248Sradhika.jagtap@ARM.com 78611248Sradhika.jagtap@ARM.com InstSeqNum 78711248Sradhika.jagtap@ARM.com getReqInstSeqNum() const 78811248Sradhika.jagtap@ARM.com { 78911248Sradhika.jagtap@ARM.com assert(privateFlags.isSet(VALID_INST_SEQ_NUM)); 79011248Sradhika.jagtap@ARM.com return _reqInstSeqNum; 79111248Sradhika.jagtap@ARM.com } 79211248Sradhika.jagtap@ARM.com 79311253Sradhika.jagtap@ARM.com void 79411253Sradhika.jagtap@ARM.com setReqInstSeqNum(const InstSeqNum seq_num) 79511253Sradhika.jagtap@ARM.com { 79611253Sradhika.jagtap@ARM.com privateFlags.set(VALID_INST_SEQ_NUM); 79711253Sradhika.jagtap@ARM.com _reqInstSeqNum = seq_num; 79811253Sradhika.jagtap@ARM.com } 79911253Sradhika.jagtap@ARM.com 80011305Sblake.hechtman@amd.com /** Accessor functions for flags. Note that these are for testing 80110882Sandreas.hansson@arm.com only; setting flags should be done via setFlags(). */ 8026427Ssteve.reinhardt@amd.com bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); } 80310824SAndreas.Sandberg@ARM.com bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); } 8046427Ssteve.reinhardt@amd.com bool isInstFetch() const { return _flags.isSet(INST_FETCH); } 8056427Ssteve.reinhardt@amd.com bool isPrefetch() const { return _flags.isSet(PREFETCH); } 8066427Ssteve.reinhardt@amd.com bool isLLSC() const { return _flags.isSet(LLSC); } 8079950Sprakash.ramrakhyani@arm.com bool isPriv() const { return _flags.isSet(PRIVILEGED); } 80810760Ssteve.reinhardt@amd.com bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); } 8096427Ssteve.reinhardt@amd.com bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } 8106427Ssteve.reinhardt@amd.com bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } 8118105Sgblack@eecs.umich.edu bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); } 81210028SGiacomo.Gabrielli@arm.com bool isSecure() const { return _flags.isSet(SECURE); } 81310029SGiacomo.Gabrielli@arm.com bool isPTWalk() const { return _flags.isSet(PT_WALK); } 81411269Sdavid.hashe@amd.com bool isAcquire() const { return _flags.isSet(ACQUIRE); } 81511269Sdavid.hashe@amd.com bool isRelease() const { return _flags.isSet(RELEASE); } 81611305Sblake.hechtman@amd.com bool isKernel() const { return _flags.isSet(KERNEL); } 81711306Santhony.gutierrez@amd.com bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); } 81811306Santhony.gutierrez@amd.com bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); } 81911306Santhony.gutierrez@amd.com 82011306Santhony.gutierrez@amd.com bool 82111306Santhony.gutierrez@amd.com isAtomic() const 82211306Santhony.gutierrez@amd.com { 82311306Santhony.gutierrez@amd.com return _flags.isSet(ATOMIC_RETURN_OP) || 82411306Santhony.gutierrez@amd.com _flags.isSet(ATOMIC_NO_RETURN_OP); 82511306Santhony.gutierrez@amd.com } 82611305Sblake.hechtman@amd.com 82711305Sblake.hechtman@amd.com /** 82812346Snikos.nikoleris@arm.com * Accessor functions for the destination of a memory request. The 82912346Snikos.nikoleris@arm.com * destination flag can specify a point of reference for the 83012346Snikos.nikoleris@arm.com * operation (e.g. a cache block clean to the the point of 83112346Snikos.nikoleris@arm.com * unification). At the moment the destination is only used by the 83212346Snikos.nikoleris@arm.com * cache maintenance operations. 83312346Snikos.nikoleris@arm.com */ 83412346Snikos.nikoleris@arm.com bool isToPOU() const { return _flags.isSet(DST_POU); } 83512346Snikos.nikoleris@arm.com bool isToPOC() const { return _flags.isSet(DST_POC); } 83612346Snikos.nikoleris@arm.com Flags getDest() const { return _flags & DST_BITS; } 83712346Snikos.nikoleris@arm.com 83812346Snikos.nikoleris@arm.com /** 83911305Sblake.hechtman@amd.com * Accessor functions for the memory space configuration flags and used by 84011305Sblake.hechtman@amd.com * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that 84111305Sblake.hechtman@amd.com * these are for testing only; setting extraFlags should be done via 84211305Sblake.hechtman@amd.com * setMemSpaceConfigFlags(). 84311305Sblake.hechtman@amd.com */ 84411305Sblake.hechtman@amd.com bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); } 84511305Sblake.hechtman@amd.com 84611305Sblake.hechtman@amd.com bool 84711305Sblake.hechtman@amd.com isWavefrontScope() const 84811305Sblake.hechtman@amd.com { 84911305Sblake.hechtman@amd.com assert(isScoped()); 85011305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE); 85111305Sblake.hechtman@amd.com } 85211305Sblake.hechtman@amd.com 85311305Sblake.hechtman@amd.com bool 85411305Sblake.hechtman@amd.com isWorkgroupScope() const 85511305Sblake.hechtman@amd.com { 85611305Sblake.hechtman@amd.com assert(isScoped()); 85711305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE); 85811305Sblake.hechtman@amd.com } 85911305Sblake.hechtman@amd.com 86011305Sblake.hechtman@amd.com bool 86111305Sblake.hechtman@amd.com isDeviceScope() const 86211305Sblake.hechtman@amd.com { 86311305Sblake.hechtman@amd.com assert(isScoped()); 86411305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(DEVICE_SCOPE); 86511305Sblake.hechtman@amd.com } 86611305Sblake.hechtman@amd.com 86711305Sblake.hechtman@amd.com bool 86811305Sblake.hechtman@amd.com isSystemScope() const 86911305Sblake.hechtman@amd.com { 87011305Sblake.hechtman@amd.com assert(isScoped()); 87111305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE); 87211305Sblake.hechtman@amd.com } 87311305Sblake.hechtman@amd.com 87411305Sblake.hechtman@amd.com bool 87511305Sblake.hechtman@amd.com isGlobalSegment() const 87611305Sblake.hechtman@amd.com { 87711305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) || 87811305Sblake.hechtman@amd.com (!isGroupSegment() && !isPrivateSegment() && 87911305Sblake.hechtman@amd.com !isKernargSegment() && !isReadonlySegment() && 88011305Sblake.hechtman@amd.com !isSpillSegment() && !isArgSegment()); 88111305Sblake.hechtman@amd.com } 88211305Sblake.hechtman@amd.com 88311305Sblake.hechtman@amd.com bool 88411305Sblake.hechtman@amd.com isGroupSegment() const 88511305Sblake.hechtman@amd.com { 88611305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(GROUP_SEGMENT); 88711305Sblake.hechtman@amd.com } 88811305Sblake.hechtman@amd.com 88911305Sblake.hechtman@amd.com bool 89011305Sblake.hechtman@amd.com isPrivateSegment() const 89111305Sblake.hechtman@amd.com { 89211305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT); 89311305Sblake.hechtman@amd.com } 89411305Sblake.hechtman@amd.com 89511305Sblake.hechtman@amd.com bool 89611305Sblake.hechtman@amd.com isKernargSegment() const 89711305Sblake.hechtman@amd.com { 89811305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT); 89911305Sblake.hechtman@amd.com } 90011305Sblake.hechtman@amd.com 90111305Sblake.hechtman@amd.com bool 90211305Sblake.hechtman@amd.com isReadonlySegment() const 90311305Sblake.hechtman@amd.com { 90411305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(READONLY_SEGMENT); 90511305Sblake.hechtman@amd.com } 90611305Sblake.hechtman@amd.com 90711305Sblake.hechtman@amd.com bool 90811305Sblake.hechtman@amd.com isSpillSegment() const 90911305Sblake.hechtman@amd.com { 91011305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(SPILL_SEGMENT); 91111305Sblake.hechtman@amd.com } 91211305Sblake.hechtman@amd.com 91311305Sblake.hechtman@amd.com bool 91411305Sblake.hechtman@amd.com isArgSegment() const 91511305Sblake.hechtman@amd.com { 91611305Sblake.hechtman@amd.com return _memSpaceConfigFlags.isSet(ARG_SEGMENT); 91711305Sblake.hechtman@amd.com } 91812347Snikos.nikoleris@arm.com 91912347Snikos.nikoleris@arm.com /** 92012347Snikos.nikoleris@arm.com * Accessor functions to determine whether this request is part of 92112347Snikos.nikoleris@arm.com * a cache maintenance operation. At the moment three operations 92212347Snikos.nikoleris@arm.com * are supported: 92312347Snikos.nikoleris@arm.com 92412347Snikos.nikoleris@arm.com * 1) A cache clean operation updates all copies of a memory 92512347Snikos.nikoleris@arm.com * location to the point of reference, 92612347Snikos.nikoleris@arm.com * 2) A cache invalidate operation invalidates all copies of the 92712347Snikos.nikoleris@arm.com * specified block in the memory above the point of reference, 92812347Snikos.nikoleris@arm.com * 3) A clean and invalidate operation is a combination of the two 92912347Snikos.nikoleris@arm.com * operations. 93012347Snikos.nikoleris@arm.com * @{ */ 93112347Snikos.nikoleris@arm.com bool isCacheClean() const { return _flags.isSet(CLEAN); } 93212347Snikos.nikoleris@arm.com bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); } 93312347Snikos.nikoleris@arm.com bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); } 93412347Snikos.nikoleris@arm.com /** @} */ 9352384SN/A}; 9362381SN/A 9372381SN/A#endif // __MEM_REQUEST_HH__ 938