physical.hh revision 7770:6286bb50127e
110388SAndreas.Sandberg@ARM.com/* 210388SAndreas.Sandberg@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 310388SAndreas.Sandberg@ARM.com * All rights reserved. 410388SAndreas.Sandberg@ARM.com * 510388SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 610388SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 710388SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 810388SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 910388SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 1010388SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 1110388SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 1210388SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 1310388SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 1410388SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 1510388SAndreas.Sandberg@ARM.com * 1610388SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710388SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810388SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910388SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010388SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110388SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210388SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310388SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410388SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510388SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610388SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710388SAndreas.Sandberg@ARM.com * 2810388SAndreas.Sandberg@ARM.com * Authors: Ron Dreslinski 2910388SAndreas.Sandberg@ARM.com */ 3010388SAndreas.Sandberg@ARM.com 3110388SAndreas.Sandberg@ARM.com/* @file 3210388SAndreas.Sandberg@ARM.com */ 3310388SAndreas.Sandberg@ARM.com 3410388SAndreas.Sandberg@ARM.com#ifndef __PHYSICAL_MEMORY_HH__ 3510388SAndreas.Sandberg@ARM.com#define __PHYSICAL_MEMORY_HH__ 3610388SAndreas.Sandberg@ARM.com 3710388SAndreas.Sandberg@ARM.com#include <map> 3810388SAndreas.Sandberg@ARM.com#include <string> 3910388SAndreas.Sandberg@ARM.com 4010388SAndreas.Sandberg@ARM.com#include "base/range.hh" 4110388SAndreas.Sandberg@ARM.com#include "mem/mem_object.hh" 4210388SAndreas.Sandberg@ARM.com#include "mem/packet.hh" 4310388SAndreas.Sandberg@ARM.com#include "mem/tport.hh" 4410388SAndreas.Sandberg@ARM.com#include "params/PhysicalMemory.hh" 4510388SAndreas.Sandberg@ARM.com#include "sim/eventq.hh" 4610559Sandreas.hansson@arm.com 4710559Sandreas.hansson@arm.com// 4810388SAndreas.Sandberg@ARM.com// Functional model for a contiguous block of physical memory. (i.e. RAM) 4910388SAndreas.Sandberg@ARM.com// 5010388SAndreas.Sandberg@ARM.comclass PhysicalMemory : public MemObject 5110388SAndreas.Sandberg@ARM.com{ 5210388SAndreas.Sandberg@ARM.com protected: 5310388SAndreas.Sandberg@ARM.com 5410388SAndreas.Sandberg@ARM.com class MemoryPort : public SimpleTimingPort 5510388SAndreas.Sandberg@ARM.com { 5610388SAndreas.Sandberg@ARM.com PhysicalMemory *memory; 5710388SAndreas.Sandberg@ARM.com 5810388SAndreas.Sandberg@ARM.com public: 5910388SAndreas.Sandberg@ARM.com 6010388SAndreas.Sandberg@ARM.com MemoryPort(const std::string &_name, PhysicalMemory *_memory); 6110388SAndreas.Sandberg@ARM.com 6210388SAndreas.Sandberg@ARM.com protected: 6310388SAndreas.Sandberg@ARM.com 6410388SAndreas.Sandberg@ARM.com virtual Tick recvAtomic(PacketPtr pkt); 6510388SAndreas.Sandberg@ARM.com 6610388SAndreas.Sandberg@ARM.com virtual void recvFunctional(PacketPtr pkt); 6710388SAndreas.Sandberg@ARM.com 6810388SAndreas.Sandberg@ARM.com virtual void recvStatusChange(Status status); 6910388SAndreas.Sandberg@ARM.com 7010388SAndreas.Sandberg@ARM.com virtual void getDeviceAddressRanges(AddrRangeList &resp, 7110388SAndreas.Sandberg@ARM.com bool &snoop); 7210388SAndreas.Sandberg@ARM.com 7310388SAndreas.Sandberg@ARM.com virtual unsigned deviceBlockSize() const; 7410388SAndreas.Sandberg@ARM.com }; 7510388SAndreas.Sandberg@ARM.com 7610388SAndreas.Sandberg@ARM.com int numPorts; 7710388SAndreas.Sandberg@ARM.com 7810602SAndreas.Sandberg@ARM.com 7910602SAndreas.Sandberg@ARM.com private: 8010388SAndreas.Sandberg@ARM.com // prevent copying of a MainMemory object 8110388SAndreas.Sandberg@ARM.com PhysicalMemory(const PhysicalMemory &specmem); 8210388SAndreas.Sandberg@ARM.com const PhysicalMemory &operator=(const PhysicalMemory &specmem); 8310388SAndreas.Sandberg@ARM.com 8410388SAndreas.Sandberg@ARM.com protected: 8510388SAndreas.Sandberg@ARM.com 8610388SAndreas.Sandberg@ARM.com class LockedAddr { 8710388SAndreas.Sandberg@ARM.com public: 8810388SAndreas.Sandberg@ARM.com // on alpha, minimum LL/SC granularity is 16 bytes, so lower 8910388SAndreas.Sandberg@ARM.com // bits need to masked off. 9010388SAndreas.Sandberg@ARM.com static const Addr Addr_Mask = 0xf; 9110388SAndreas.Sandberg@ARM.com 9210388SAndreas.Sandberg@ARM.com static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 9310388SAndreas.Sandberg@ARM.com 9410388SAndreas.Sandberg@ARM.com Addr addr; // locked address 9510388SAndreas.Sandberg@ARM.com int contextId; // locking hw context 9610388SAndreas.Sandberg@ARM.com 9710388SAndreas.Sandberg@ARM.com // check for matching execution context 9810388SAndreas.Sandberg@ARM.com bool matchesContext(Request *req) 9910388SAndreas.Sandberg@ARM.com { 10010388SAndreas.Sandberg@ARM.com return (contextId == req->contextId()); 10110388SAndreas.Sandberg@ARM.com } 10210388SAndreas.Sandberg@ARM.com 10310388SAndreas.Sandberg@ARM.com LockedAddr(Request *req) 10410388SAndreas.Sandberg@ARM.com : addr(mask(req->getPaddr())), 10510388SAndreas.Sandberg@ARM.com contextId(req->contextId()) 10610388SAndreas.Sandberg@ARM.com { 10710388SAndreas.Sandberg@ARM.com } 10810388SAndreas.Sandberg@ARM.com // constructor for unserialization use 10910388SAndreas.Sandberg@ARM.com LockedAddr(Addr _addr, int _cid) 11010388SAndreas.Sandberg@ARM.com : addr(_addr), contextId(_cid) 11110388SAndreas.Sandberg@ARM.com { 11210388SAndreas.Sandberg@ARM.com } 11310388SAndreas.Sandberg@ARM.com }; 11410388SAndreas.Sandberg@ARM.com 11510388SAndreas.Sandberg@ARM.com std::list<LockedAddr> lockedAddrList; 11610388SAndreas.Sandberg@ARM.com 11710388SAndreas.Sandberg@ARM.com // helper function for checkLockedAddrs(): we really want to 11810388SAndreas.Sandberg@ARM.com // inline a quick check for an empty locked addr list (hopefully 11910388SAndreas.Sandberg@ARM.com // the common case), and do the full list search (if necessary) in 12010388SAndreas.Sandberg@ARM.com // this out-of-line function 12110388SAndreas.Sandberg@ARM.com bool checkLockedAddrList(PacketPtr pkt); 12210388SAndreas.Sandberg@ARM.com 12310388SAndreas.Sandberg@ARM.com // Record the address of a load-locked operation so that we can 12410388SAndreas.Sandberg@ARM.com // clear the execution context's lock flag if a matching store is 12510388SAndreas.Sandberg@ARM.com // performed 12610672SAndreas.Sandberg@ARM.com void trackLoadLocked(PacketPtr pkt); 12710672SAndreas.Sandberg@ARM.com 12810672SAndreas.Sandberg@ARM.com // Compare a store address with any locked addresses so we can 12910672SAndreas.Sandberg@ARM.com // clear the lock flag appropriately. Return value set to 'false' 13010672SAndreas.Sandberg@ARM.com // if store operation should be suppressed (because it was a 13110388SAndreas.Sandberg@ARM.com // conditional store and the address was no longer locked by the 13210388SAndreas.Sandberg@ARM.com // requesting execution context), 'true' otherwise. Note that 13310388SAndreas.Sandberg@ARM.com // this method must be called on *all* stores since even 13410388SAndreas.Sandberg@ARM.com // non-conditional stores must clear any matching lock addresses. 13510388SAndreas.Sandberg@ARM.com bool writeOK(PacketPtr pkt) { 13610388SAndreas.Sandberg@ARM.com Request *req = pkt->req; 13710388SAndreas.Sandberg@ARM.com if (lockedAddrList.empty()) { 13810388SAndreas.Sandberg@ARM.com // no locked addrs: nothing to check, store_conditional fails 13910388SAndreas.Sandberg@ARM.com bool isLLSC = pkt->isLLSC(); 14010388SAndreas.Sandberg@ARM.com if (isLLSC) { 14110388SAndreas.Sandberg@ARM.com req->setExtraData(0); 14210388SAndreas.Sandberg@ARM.com } 14310388SAndreas.Sandberg@ARM.com return !isLLSC; // only do write if not an sc 14410388SAndreas.Sandberg@ARM.com } else { 14510388SAndreas.Sandberg@ARM.com // iterate over list... 14610388SAndreas.Sandberg@ARM.com return checkLockedAddrList(pkt); 14710388SAndreas.Sandberg@ARM.com } 14810388SAndreas.Sandberg@ARM.com } 14910388SAndreas.Sandberg@ARM.com 15010388SAndreas.Sandberg@ARM.com uint8_t *pmemAddr; 15110388SAndreas.Sandberg@ARM.com Tick lat; 15210388SAndreas.Sandberg@ARM.com Tick lat_var; 15310388SAndreas.Sandberg@ARM.com std::vector<MemoryPort*> ports; 15410388SAndreas.Sandberg@ARM.com typedef std::vector<MemoryPort*>::iterator PortIterator; 15510388SAndreas.Sandberg@ARM.com 15610388SAndreas.Sandberg@ARM.com uint64_t _size; 15710388SAndreas.Sandberg@ARM.com uint64_t _start; 15810388SAndreas.Sandberg@ARM.com public: 15910602SAndreas.Sandberg@ARM.com uint64_t size() { return _size; } 16010602SAndreas.Sandberg@ARM.com uint64_t start() { return _start; } 16110388SAndreas.Sandberg@ARM.com 16210388SAndreas.Sandberg@ARM.com public: 16310388SAndreas.Sandberg@ARM.com typedef PhysicalMemoryParams Params; 16410388SAndreas.Sandberg@ARM.com PhysicalMemory(const Params *p); 16510388SAndreas.Sandberg@ARM.com virtual ~PhysicalMemory(); 16610388SAndreas.Sandberg@ARM.com 16710388SAndreas.Sandberg@ARM.com const Params * 16810388SAndreas.Sandberg@ARM.com params() const 16910388SAndreas.Sandberg@ARM.com { 17010388SAndreas.Sandberg@ARM.com return dynamic_cast<const Params *>(_params); 17110388SAndreas.Sandberg@ARM.com } 17210388SAndreas.Sandberg@ARM.com 17310388SAndreas.Sandberg@ARM.com public: 17410388SAndreas.Sandberg@ARM.com unsigned deviceBlockSize() const; 17510388SAndreas.Sandberg@ARM.com void getAddressRanges(AddrRangeList &resp, bool &snoop); 17610388SAndreas.Sandberg@ARM.com virtual Port *getPort(const std::string &if_name, int idx = -1); 17710388SAndreas.Sandberg@ARM.com void virtual init(); 17810388SAndreas.Sandberg@ARM.com unsigned int drain(Event *de); 17910388SAndreas.Sandberg@ARM.com 18010388SAndreas.Sandberg@ARM.com protected: 18110388SAndreas.Sandberg@ARM.com Tick doAtomicAccess(PacketPtr pkt); 18210388SAndreas.Sandberg@ARM.com void doFunctionalAccess(PacketPtr pkt); 18310388SAndreas.Sandberg@ARM.com virtual Tick calculateLatency(PacketPtr pkt); 18410388SAndreas.Sandberg@ARM.com void recvStatusChange(Port::Status status); 18510388SAndreas.Sandberg@ARM.com 18610388SAndreas.Sandberg@ARM.com public: 18710388SAndreas.Sandberg@ARM.com virtual void serialize(std::ostream &os); 18810388SAndreas.Sandberg@ARM.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 18910388SAndreas.Sandberg@ARM.com 19010388SAndreas.Sandberg@ARM.com}; 19110388SAndreas.Sandberg@ARM.com 19210388SAndreas.Sandberg@ARM.com#endif //__PHYSICAL_MEMORY_HH__ 19310388SAndreas.Sandberg@ARM.com