physical.hh revision 10699:d0004c12d024
172SN/A/* 21762SN/A * Copyright (c) 2012 ARM Limited 372SN/A * All rights reserved 472SN/A * 572SN/A * The license below extends only to copyright in the software and shall 672SN/A * not be construed as granting a license to any other intellectual 772SN/A * property including but not limited to intellectual property relating 872SN/A * to a hardware implementation of the functionality of the software 972SN/A * licensed hereunder. You may use the software subject to the license 1072SN/A * terms below provided that you ensure that this notice is replicated 1172SN/A * unmodified and in its entirety in all distributions of the software, 1272SN/A * modified or unmodified, in source code or in binary form. 1372SN/A * 1472SN/A * Redistribution and use in source and binary forms, with or without 1572SN/A * modification, are permitted provided that the following conditions are 1672SN/A * met: redistributions of source code must retain the above copyright 1772SN/A * notice, this list of conditions and the following disclaimer; 1872SN/A * redistributions in binary form must reproduce the above copyright 1972SN/A * notice, this list of conditions and the following disclaimer in the 2072SN/A * documentation and/or other materials provided with the distribution; 2172SN/A * neither the name of the copyright holders nor the names of its 2272SN/A * contributors may be used to endorse or promote products derived from 2372SN/A * this software without specific prior written permission. 2472SN/A * 2572SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2672SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2972SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3072SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362SN/A * 372SN/A * Authors: Andreas Hansson 382SN/A */ 392SN/A 402SN/A#ifndef __MEM_PHYSICAL_HH__ 412SN/A#define __MEM_PHYSICAL_HH__ 422SN/A 432SN/A#include "base/addr_range_map.hh" 442SN/A#include "mem/packet.hh" 452SN/A 462SN/A/** 472SN/A * Forward declaration to avoid header dependencies. 482SN/A */ 492SN/Aclass AbstractMemory; 502SN/A 512SN/A/** 522SN/A * The physical memory encapsulates all memories in the system and 532SN/A * provides basic functionality for accessing those memories without 542SN/A * going through the memory system and interconnect. 552SN/A * 562SN/A * The physical memory is also responsible for providing the host 572SN/A * system backingstore used by the memories in the simulated guest 582SN/A * system. When the system is created, the physical memory allocates 592SN/A * the backing store based on the address ranges that are populated in 602SN/A * the system, and does so independent of how those map to actual 612SN/A * memory controllers. Thus, the physical memory completely abstracts 622SN/A * the mapping of the backing store of the host system and the address 632SN/A * mapping in the guest system. This enables us to arbitrarily change 642SN/A * the number of memory controllers, and their address mapping, as 652SN/A * long as the ranges stay the same. 662SN/A */ 672SN/Aclass PhysicalMemory : public Serializable 682SN/A{ 692SN/A 702SN/A private: 712SN/A 722SN/A // Name for debugging 732SN/A std::string _name; 742SN/A 752SN/A // Global address map 762SN/A AddrRangeMap<AbstractMemory*> addrMap; 772SN/A 782SN/A // a mutable cache for the last address map iterator that matched 792SN/A // an address 802SN/A mutable AddrRangeMap<AbstractMemory*>::const_iterator rangeCache; 812SN/A 822SN/A // All address-mapped memories 832SN/A std::vector<AbstractMemory*> memories; 842SN/A 852SN/A // The total memory size 862SN/A uint64_t size; 872SN/A 882SN/A // The physical memory used to provide the memory in the simulated 892SN/A // system 902SN/A std::vector<std::pair<AddrRange, uint8_t*>> backingStore; 912SN/A 922SN/A // Prevent copying 932SN/A PhysicalMemory(const PhysicalMemory&); 942SN/A 952SN/A // Prevent assignment 962SN/A PhysicalMemory& operator=(const PhysicalMemory&); 972SN/A 982SN/A /** 992SN/A * Create the memory region providing the backing store for a 1002SN/A * given address range that corresponds to a set of memories in 1012SN/A * the simulated system. 1022SN/A * 1032SN/A * @param range The address range covered 1042SN/A * @param memories The memories this range maps to 1052SN/A */ 1062SN/A void createBackingStore(AddrRange range, 1072SN/A const std::vector<AbstractMemory*>& _memories); 1082SN/A 1092SN/A public: 1102SN/A 1112SN/A /** 1122SN/A * Create a physical memory object, wrapping a number of memories. 1132SN/A */ 1142SN/A PhysicalMemory(const std::string& _name, 1152SN/A const std::vector<AbstractMemory*>& _memories); 1162SN/A 1172SN/A /** 1182SN/A * Unmap all the backing store we have used. 1192SN/A */ 1202SN/A ~PhysicalMemory(); 1211717SN/A 1222SN/A /** 1232SN/A * Return the name for debugging and for creation of sections for 1242521SN/A * checkpointing. 12556SN/A */ 12656SN/A const std::string name() const { return _name; } 12756SN/A 12856SN/A /** 1292521SN/A * Check if a physical address is within a range of a memory that 1302680Sktlim@umich.edu * is part of the global address map. 1311717SN/A * 1322521SN/A * @param addr A physical address 1332521SN/A * @return Whether the address corresponds to a memory 1341717SN/A */ 1352SN/A bool isMemAddr(Addr addr) const; 1362SN/A 1372107SN/A /** 1382SN/A * Get the memory ranges for all memories that are to be reported 1392009SN/A * to the configuration table. The ranges are merged before they 1403536Sgblack@eecs.umich.edu * are returned such that any interleaved ranges appear as a 1412SN/A * single range. 1422SN/A * 1432SN/A * @return All configuration table memory ranges 1442SN/A */ 1453536Sgblack@eecs.umich.edu AddrRangeList getConfAddrRanges() const; 1461910SN/A 1473536Sgblack@eecs.umich.edu /** 1481910SN/A * Get the total physical memory size. 1491910SN/A * 1501910SN/A * @return The sum of all memory sizes 1513536Sgblack@eecs.umich.edu */ 1521910SN/A uint64_t totalSize() const { return size; } 1532SN/A 1542SN/A /** 1552SN/A * Get the pointers to the backing store for external host 1562SN/A * access. Note that memory in the guest should be accessed using 1572SN/A * access() or functionalAccess(). This interface is primarily 1582SN/A * intended for CPU models using hardware virtualization. Note 1592SN/A * that memories that are null are not present, and that the 1602SN/A * backing store may also contain memories that are not part of 1612SN/A * the OS-visible global address map and thus are allowed to 1622SN/A * overlap. 1632SN/A * 1642SN/A * @return Pointers to the memory backing store 1652SN/A */ 1662SN/A std::vector<std::pair<AddrRange, uint8_t*>> getBackingStore() const 1672SN/A { return backingStore; } 1682SN/A 1692SN/A /** 1702SN/A * Perform an untimed memory access and update all the state 1713536Sgblack@eecs.umich.edu * (e.g. locked addresses) and statistics accordingly. The packet 1722SN/A * is turned into a response if required. 1731910SN/A * 1741910SN/A * @param pkt Packet performing the access 1751910SN/A */ 1761910SN/A void access(PacketPtr pkt); 1772SN/A 1782SN/A /** 1792SN/A * Perform an untimed memory read or write without changing 1802SN/A * anything but the memory itself. No stats are affected by this 1812SN/A * access. In addition to normal accesses this also facilitates 1822SN/A * print requests. 1832SN/A * 184507SN/A * @param pkt Packet performing the access 185507SN/A */ 186507SN/A void functionalAccess(PacketPtr pkt); 187507SN/A 188507SN/A /** 189507SN/A * Serialize all the memories in the system. This is independent 1902SN/A * of the logical memory layout, and the serialization only sees 1912SN/A * the contigous backing store, independent of how this maps to 1922SN/A * logical memories in the guest system. 1932SN/A * 194507SN/A * @param os stream to serialize to 1952SN/A */ 1962SN/A void serialize(std::ostream& os); 1972SN/A 1982SN/A /** 1992SN/A * Serialize a specific store. 2001910SN/A * 2012009SN/A * @param store_id Unique identifier of this backing store 2021910SN/A * @param range The address range of this backing store 2031910SN/A * @param pmem The host pointer to this backing store 2041910SN/A */ 2051910SN/A void serializeStore(std::ostream& os, unsigned int store_id, 2062009SN/A AddrRange range, uint8_t* pmem); 2071910SN/A 2081910SN/A /** 2091910SN/A * Unserialize the memories in the system. As with the 2101910SN/A * serialization, this action is independent of how the address 2111910SN/A * ranges are mapped to logical memories in the guest system. 2121910SN/A */ 2132SN/A void unserialize(Checkpoint* cp, const std::string& section); 2142SN/A 2152SN/A /** 2162SN/A * Unserialize a specific backing store, identified by a section. 2172SN/A */ 2182SN/A void unserializeStore(Checkpoint* cp, const std::string& section); 219507SN/A 2202SN/A}; 2212SN/A 2222SN/A#endif //__MEM_PHYSICAL_HH__ 2232SN/A