physical.hh revision 3751
12914Ssaidi@eecs.umich.edu/* 22914Ssaidi@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 32914Ssaidi@eecs.umich.edu * All rights reserved. 42914Ssaidi@eecs.umich.edu * 52914Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62914Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72914Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82914Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92914Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102914Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112914Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122914Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132914Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142914Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152914Ssaidi@eecs.umich.edu * 162914Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172914Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182914Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192914Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202914Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212914Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222914Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232914Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242914Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252914Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262914Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272914Ssaidi@eecs.umich.edu * 282914Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 292914Ssaidi@eecs.umich.edu */ 302914Ssaidi@eecs.umich.edu 312914Ssaidi@eecs.umich.edu/* @file 322914Ssaidi@eecs.umich.edu */ 332914Ssaidi@eecs.umich.edu 342914Ssaidi@eecs.umich.edu#ifndef __PHYSICAL_MEMORY_HH__ 352914Ssaidi@eecs.umich.edu#define __PHYSICAL_MEMORY_HH__ 362914Ssaidi@eecs.umich.edu 372914Ssaidi@eecs.umich.edu#include "base/range.hh" 382914Ssaidi@eecs.umich.edu#include "mem/mem_object.hh" 392914Ssaidi@eecs.umich.edu#include "mem/packet.hh" 402914Ssaidi@eecs.umich.edu#include "mem/tport.hh" 412914Ssaidi@eecs.umich.edu#include "sim/eventq.hh" 422914Ssaidi@eecs.umich.edu#include <map> 432914Ssaidi@eecs.umich.edu#include <string> 442914Ssaidi@eecs.umich.edu 452914Ssaidi@eecs.umich.edu// 462914Ssaidi@eecs.umich.edu// Functional model for a contiguous block of physical memory. (i.e. RAM) 472914Ssaidi@eecs.umich.edu// 482914Ssaidi@eecs.umich.educlass PhysicalMemory : public MemObject 492914Ssaidi@eecs.umich.edu{ 502914Ssaidi@eecs.umich.edu class MemoryPort : public SimpleTimingPort 512914Ssaidi@eecs.umich.edu { 522914Ssaidi@eecs.umich.edu PhysicalMemory *memory; 532914Ssaidi@eecs.umich.edu 542914Ssaidi@eecs.umich.edu public: 552914Ssaidi@eecs.umich.edu 562914Ssaidi@eecs.umich.edu MemoryPort(const std::string &_name, PhysicalMemory *_memory); 572914Ssaidi@eecs.umich.edu 582914Ssaidi@eecs.umich.edu protected: 592914Ssaidi@eecs.umich.edu 602914Ssaidi@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 612914Ssaidi@eecs.umich.edu 622914Ssaidi@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 632914Ssaidi@eecs.umich.edu 642914Ssaidi@eecs.umich.edu virtual void recvStatusChange(Status status); 652914Ssaidi@eecs.umich.edu 662914Ssaidi@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 672914Ssaidi@eecs.umich.edu AddrRangeList &snoop); 682914Ssaidi@eecs.umich.edu 692914Ssaidi@eecs.umich.edu virtual int deviceBlockSize(); 702914Ssaidi@eecs.umich.edu }; 712914Ssaidi@eecs.umich.edu 722914Ssaidi@eecs.umich.edu int numPorts; 732914Ssaidi@eecs.umich.edu 742914Ssaidi@eecs.umich.edu 752914Ssaidi@eecs.umich.edu private: 762914Ssaidi@eecs.umich.edu // prevent copying of a MainMemory object 772914Ssaidi@eecs.umich.edu PhysicalMemory(const PhysicalMemory &specmem); 782914Ssaidi@eecs.umich.edu const PhysicalMemory &operator=(const PhysicalMemory &specmem); 792914Ssaidi@eecs.umich.edu 802914Ssaidi@eecs.umich.edu protected: 812914Ssaidi@eecs.umich.edu 822914Ssaidi@eecs.umich.edu class LockedAddr { 83 public: 84 // on alpha, minimum LL/SC granularity is 16 bytes, so lower 85 // bits need to masked off. 86 static const Addr Addr_Mask = 0xf; 87 88 static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 89 90 Addr addr; // locked address 91 int cpuNum; // locking CPU 92 int threadNum; // locking thread ID within CPU 93 94 // check for matching execution context 95 bool matchesContext(Request *req) 96 { 97 return (cpuNum == req->getCpuNum() && 98 threadNum == req->getThreadNum()); 99 } 100 101 LockedAddr(Request *req) 102 : addr(mask(req->getPaddr())), 103 cpuNum(req->getCpuNum()), 104 threadNum(req->getThreadNum()) 105 { 106 } 107 }; 108 109 std::list<LockedAddr> lockedAddrList; 110 111 // helper function for checkLockedAddrs(): we really want to 112 // inline a quick check for an empty locked addr list (hopefully 113 // the common case), and do the full list search (if necessary) in 114 // this out-of-line function 115 bool checkLockedAddrList(Request *req); 116 117 // Record the address of a load-locked operation so that we can 118 // clear the execution context's lock flag if a matching store is 119 // performed 120 void trackLoadLocked(Request *req); 121 122 // Compare a store address with any locked addresses so we can 123 // clear the lock flag appropriately. Return value set to 'false' 124 // if store operation should be suppressed (because it was a 125 // conditional store and the address was no longer locked by the 126 // requesting execution context), 'true' otherwise. Note that 127 // this method must be called on *all* stores since even 128 // non-conditional stores must clear any matching lock addresses. 129 bool writeOK(Request *req) { 130 if (lockedAddrList.empty()) { 131 // no locked addrs: nothing to check, store_conditional fails 132 bool isLocked = req->isLocked(); 133 if (isLocked) { 134 req->setScResult(0); 135 } 136 return !isLocked; // only do write if not an sc 137 } else { 138 // iterate over list... 139 return checkLockedAddrList(req); 140 } 141 } 142 143 uint8_t *pmemAddr; 144 MemoryPort *port; 145 int pagePtr; 146 Tick lat; 147 148 public: 149 Addr new_page(); 150 uint64_t size() { return params()->addrRange.size(); } 151 152 struct Params 153 { 154 std::string name; 155 Range<Addr> addrRange; 156 Tick latency; 157 bool zero; 158 }; 159 160 protected: 161 Params *_params; 162 163 public: 164 const Params *params() const { return _params; } 165 PhysicalMemory(Params *p); 166 virtual ~PhysicalMemory(); 167 168 public: 169 int deviceBlockSize(); 170 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop); 171 virtual Port *getPort(const std::string &if_name, int idx = -1); 172 void virtual init(); 173 unsigned int drain(Event *de); 174 175 protected: 176 void doFunctionalAccess(PacketPtr pkt); 177 virtual Tick calculateLatency(PacketPtr pkt); 178 void recvStatusChange(Port::Status status); 179 180 public: 181 virtual void serialize(std::ostream &os); 182 virtual void unserialize(Checkpoint *cp, const std::string §ion); 183 184}; 185 186#endif //__PHYSICAL_MEMORY_HH__ 187