physical.hh revision 10905
12199SN/A/* 22199SN/A * Copyright (c) 2012 ARM Limited 32199SN/A * All rights reserved 42199SN/A * 52199SN/A * The license below extends only to copyright in the software and shall 62199SN/A * not be construed as granting a license to any other intellectual 72199SN/A * property including but not limited to intellectual property relating 82199SN/A * to a hardware implementation of the functionality of the software 92199SN/A * licensed hereunder. You may use the software subject to the license 102199SN/A * terms below provided that you ensure that this notice is replicated 112199SN/A * unmodified and in its entirety in all distributions of the software, 122199SN/A * modified or unmodified, in source code or in binary form. 132199SN/A * 142199SN/A * Redistribution and use in source and binary forms, with or without 152199SN/A * modification, are permitted provided that the following conditions are 162199SN/A * met: redistributions of source code must retain the above copyright 172199SN/A * notice, this list of conditions and the following disclaimer; 182199SN/A * redistributions in binary form must reproduce the above copyright 192199SN/A * notice, this list of conditions and the following disclaimer in the 202199SN/A * documentation and/or other materials provided with the distribution; 212199SN/A * neither the name of the copyright holders nor the names of its 222199SN/A * contributors may be used to endorse or promote products derived from 232199SN/A * this software without specific prior written permission. 242199SN/A * 252199SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262199SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292199SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302199SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312202SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322202SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332199SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342584SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352474SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362199SN/A * 372199SN/A * Authors: Andreas Hansson 382474SN/A */ 392199SN/A 407741Sgblack@eecs.umich.edu#ifndef __MEM_PHYSICAL_HH__ 417741Sgblack@eecs.umich.edu#define __MEM_PHYSICAL_HH__ 427741Sgblack@eecs.umich.edu 434111Sgblack@eecs.umich.edu#include "base/addr_range_map.hh" 444111Sgblack@eecs.umich.edu#include "mem/packet.hh" 454111Sgblack@eecs.umich.edu 464111Sgblack@eecs.umich.edu/** 474111Sgblack@eecs.umich.edu * Forward declaration to avoid header dependencies. 484111Sgblack@eecs.umich.edu */ 494188Sgblack@eecs.umich.educlass AbstractMemory; 504188Sgblack@eecs.umich.edu 514188Sgblack@eecs.umich.edu/** 524188Sgblack@eecs.umich.edu * The physical memory encapsulates all memories in the system and 534111Sgblack@eecs.umich.edu * provides basic functionality for accessing those memories without 544188Sgblack@eecs.umich.edu * going through the memory system and interconnect. 554111Sgblack@eecs.umich.edu * 566075Sgblack@eecs.umich.edu * The physical memory is also responsible for providing the host 576075Sgblack@eecs.umich.edu * system backingstore used by the memories in the simulated guest 584111Sgblack@eecs.umich.edu * system. When the system is created, the physical memory allocates 594111Sgblack@eecs.umich.edu * the backing store based on the address ranges that are populated in 602202SN/A * the system, and does so independent of how those map to actual 6111851Sbrandon.potter@amd.com * memory controllers. Thus, the physical memory completely abstracts 622199SN/A * the mapping of the backing store of the host system and the address 632199SN/A * mapping in the guest system. This enables us to arbitrarily change 642199SN/A * the number of memory controllers, and their address mapping, as 6511851Sbrandon.potter@amd.com * long as the ranges stay the same. 662199SN/A */ 677741Sgblack@eecs.umich.educlass PhysicalMemory : public Serializable 687741Sgblack@eecs.umich.edu{ 694111Sgblack@eecs.umich.edu 704188Sgblack@eecs.umich.edu private: 714111Sgblack@eecs.umich.edu 722199SN/A // Name for debugging 7311877Sbrandon.potter@amd.com std::string _name; 744111Sgblack@eecs.umich.edu 752199SN/A // Global address map 764111Sgblack@eecs.umich.edu AddrRangeMap<AbstractMemory*> addrMap; 7711851Sbrandon.potter@amd.com 784111Sgblack@eecs.umich.edu // a mutable cache for the last address map iterator that matched 794111Sgblack@eecs.umich.edu // an address 804111Sgblack@eecs.umich.edu mutable AddrRangeMap<AbstractMemory*>::const_iterator rangeCache; 8111851Sbrandon.potter@amd.com 822199SN/A // All address-mapped memories 837741Sgblack@eecs.umich.edu std::vector<AbstractMemory*> memories; 847741Sgblack@eecs.umich.edu 854111Sgblack@eecs.umich.edu // The total memory size 864111Sgblack@eecs.umich.edu uint64_t size; 874111Sgblack@eecs.umich.edu 884111Sgblack@eecs.umich.edu // Let the user choose if we reserve swap space when calling mmap 8911877Sbrandon.potter@amd.com const bool mmapUsingNoReserve; 902199SN/A 912199SN/A // The physical memory used to provide the memory in the simulated 922561SN/A // system 9311851Sbrandon.potter@amd.com std::vector<std::pair<AddrRange, uint8_t*>> backingStore; 942561SN/A 952474SN/A // Prevent copying 964111Sgblack@eecs.umich.edu PhysicalMemory(const PhysicalMemory&); 97 98 // Prevent assignment 99 PhysicalMemory& operator=(const PhysicalMemory&); 100 101 /** 102 * Create the memory region providing the backing store for a 103 * given address range that corresponds to a set of memories in 104 * the simulated system. 105 * 106 * @param range The address range covered 107 * @param memories The memories this range maps to 108 */ 109 void createBackingStore(AddrRange range, 110 const std::vector<AbstractMemory*>& _memories); 111 112 public: 113 114 /** 115 * Create a physical memory object, wrapping a number of memories. 116 */ 117 PhysicalMemory(const std::string& _name, 118 const std::vector<AbstractMemory*>& _memories, 119 bool mmap_using_noreserve); 120 121 /** 122 * Unmap all the backing store we have used. 123 */ 124 ~PhysicalMemory(); 125 126 /** 127 * Return the name for debugging and for creation of sections for 128 * checkpointing. 129 */ 130 const std::string name() const { return _name; } 131 132 /** 133 * Check if a physical address is within a range of a memory that 134 * is part of the global address map. 135 * 136 * @param addr A physical address 137 * @return Whether the address corresponds to a memory 138 */ 139 bool isMemAddr(Addr addr) const; 140 141 /** 142 * Get the memory ranges for all memories that are to be reported 143 * to the configuration table. The ranges are merged before they 144 * are returned such that any interleaved ranges appear as a 145 * single range. 146 * 147 * @return All configuration table memory ranges 148 */ 149 AddrRangeList getConfAddrRanges() const; 150 151 /** 152 * Get the total physical memory size. 153 * 154 * @return The sum of all memory sizes 155 */ 156 uint64_t totalSize() const { return size; } 157 158 /** 159 * Get the pointers to the backing store for external host 160 * access. Note that memory in the guest should be accessed using 161 * access() or functionalAccess(). This interface is primarily 162 * intended for CPU models using hardware virtualization. Note 163 * that memories that are null are not present, and that the 164 * backing store may also contain memories that are not part of 165 * the OS-visible global address map and thus are allowed to 166 * overlap. 167 * 168 * @return Pointers to the memory backing store 169 */ 170 std::vector<std::pair<AddrRange, uint8_t*>> getBackingStore() const 171 { return backingStore; } 172 173 /** 174 * Perform an untimed memory access and update all the state 175 * (e.g. locked addresses) and statistics accordingly. The packet 176 * is turned into a response if required. 177 * 178 * @param pkt Packet performing the access 179 */ 180 void access(PacketPtr pkt); 181 182 /** 183 * Perform an untimed memory read or write without changing 184 * anything but the memory itself. No stats are affected by this 185 * access. In addition to normal accesses this also facilitates 186 * print requests. 187 * 188 * @param pkt Packet performing the access 189 */ 190 void functionalAccess(PacketPtr pkt); 191 192 /** 193 * Serialize all the memories in the system. This is independent 194 * of the logical memory layout, and the serialization only sees 195 * the contigous backing store, independent of how this maps to 196 * logical memories in the guest system. 197 * 198 * @param os stream to serialize to 199 */ 200 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 201 202 /** 203 * Serialize a specific store. 204 * 205 * @param store_id Unique identifier of this backing store 206 * @param range The address range of this backing store 207 * @param pmem The host pointer to this backing store 208 */ 209 void serializeStore(CheckpointOut &cp, unsigned int store_id, 210 AddrRange range, uint8_t* pmem) const; 211 212 /** 213 * Unserialize the memories in the system. As with the 214 * serialization, this action is independent of how the address 215 * ranges are mapped to logical memories in the guest system. 216 */ 217 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 218 219 /** 220 * Unserialize a specific backing store, identified by a section. 221 */ 222 void unserializeStore(CheckpointIn &cp); 223 224}; 225 226#endif //__MEM_PHYSICAL_HH__ 227