page_table.hh revision 8601
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31/** 32 * @file 33 * Declaration of a non-full system Page Table. 34 */ 35 36#ifndef __MEM_PAGE_TABLE_HH__ 37#define __MEM_PAGE_TABLE_HH__ 38 39#include <string> 40 41#include "arch/isa_traits.hh" 42#include "arch/tlb.hh" 43#include "base/hashmap.hh" 44#include "base/types.hh" 45#include "config/the_isa.hh" 46#include "mem/request.hh" 47#include "sim/serialize.hh" 48 49/** 50 * Page Table Declaration. 51 */ 52class PageTable 53{ 54 protected: 55 typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable; 56 typedef PTable::iterator PTableItr; 57 PTable pTable; 58 59 struct cacheElement { 60 Addr vaddr; 61 TheISA::TlbEntry entry; 62 }; 63 64 struct cacheElement pTableCache[3]; 65 66 const Addr pageSize; 67 const Addr offsetMask; 68 69 const uint64_t pid; 70 const std::string _name; 71 72 public: 73 74 PageTable(const std::string &__name, uint64_t _pid, 75 Addr _pageSize = TheISA::VMPageSize); 76 77 ~PageTable(); 78 79 // for DPRINTF compatibility 80 const std::string name() const { return _name; } 81 82 Addr pageAlign(Addr a) { return (a & ~offsetMask); } 83 Addr pageOffset(Addr a) { return (a & offsetMask); } 84 85 void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false); 86 void remap(Addr vaddr, int64_t size, Addr new_vaddr); 87 void unmap(Addr vaddr, int64_t size); 88 89 /** 90 * Check if any pages in a region are already allocated 91 * @param vaddr The starting virtual address of the region. 92 * @param size The length of the region. 93 * @return True if no pages in the region are mapped. 94 */ 95 bool isUnmapped(Addr vaddr, int64_t size); 96 97 /** 98 * Lookup function 99 * @param vaddr The virtual address. 100 * @return entry The page table entry corresponding to vaddr. 101 */ 102 bool lookup(Addr vaddr, TheISA::TlbEntry &entry); 103 104 /** 105 * Translate function 106 * @param vaddr The virtual address. 107 * @param paddr Physical address from translation. 108 * @return True if translation exists 109 */ 110 bool translate(Addr vaddr, Addr &paddr); 111 112 /** 113 * Simplified translate function (just check for translation) 114 * @param vaddr The virtual address. 115 * @return True if translation exists 116 */ 117 bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); } 118 119 /** 120 * Perform a translation on the memory request, fills in paddr 121 * field of req. 122 * @param req The memory request. 123 */ 124 Fault translate(RequestPtr req); 125 126 /** 127 * Update the page table cache. 128 * @param vaddr virtual address (page aligned) to check 129 * @param pte page table entry to return 130 */ 131 inline void updateCache(Addr vaddr, TheISA::TlbEntry entry) 132 { 133 pTableCache[2].entry = pTableCache[1].entry; 134 pTableCache[2].vaddr = pTableCache[1].vaddr; 135 pTableCache[1].entry = pTableCache[0].entry; 136 pTableCache[1].vaddr = pTableCache[0].vaddr; 137 pTableCache[0].entry = entry; 138 pTableCache[0].vaddr = vaddr; 139 } 140 141 142 void serialize(std::ostream &os); 143 144 void unserialize(Checkpoint *cp, const std::string §ion); 145}; 146 147#endif // __MEM_PAGE_TABLE_HH__ 148