page_table.hh revision 8600:b0d7c64ada19 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31/**
32 * @file
33 * Declaration of a non-full system Page Table.
34 */
35
36#ifndef __MEM_PAGE_TABLE_HH__
37#define __MEM_PAGE_TABLE_HH__
38
39#include <string>
40
41#include "arch/isa_traits.hh"
42#include "arch/tlb.hh"
43#include "base/hashmap.hh"
44#include "base/types.hh"
45#include "config/the_isa.hh"
46#include "mem/request.hh"
47#include "sim/serialize.hh"
48
49class Process;
50
51/**
52 * Page Table Declaration.
53 */
54class PageTable
55{
56  protected:
57    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
58    typedef PTable::iterator PTableItr;
59    PTable pTable;
60
61    struct cacheElement {
62        Addr vaddr;
63        TheISA::TlbEntry entry;
64    };
65
66    struct cacheElement pTableCache[3];
67
68    const Addr pageSize;
69    const Addr offsetMask;
70
71    Process *process;
72
73  public:
74
75    PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
76
77    ~PageTable();
78
79    Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
80    Addr pageOffset(Addr a) { return (a &  offsetMask); }
81
82    void allocate(Addr vaddr, int64_t size, bool clobber = false);
83    void remap(Addr vaddr, int64_t size, Addr new_vaddr);
84    void deallocate(Addr vaddr, int64_t size);
85
86    /**
87     * Check if any pages in a region are already allocated
88     * @param vaddr The starting virtual address of the region.
89     * @param size The length of the region.
90     * @return True if no pages in the region are mapped.
91     */
92    bool isUnmapped(Addr vaddr, int64_t size);
93
94    /**
95     * Lookup function
96     * @param vaddr The virtual address.
97     * @return entry The page table entry corresponding to vaddr.
98     */
99    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
100
101    /**
102     * Translate function
103     * @param vaddr The virtual address.
104     * @param paddr Physical address from translation.
105     * @return True if translation exists
106     */
107    bool translate(Addr vaddr, Addr &paddr);
108
109    /**
110     * Simplified translate function (just check for translation)
111     * @param vaddr The virtual address.
112     * @return True if translation exists
113     */
114    bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
115
116    /**
117     * Perform a translation on the memory request, fills in paddr
118     * field of req.
119     * @param req The memory request.
120     */
121    Fault translate(RequestPtr req);
122
123    /**
124     * Update the page table cache.
125     * @param vaddr virtual address (page aligned) to check
126     * @param pte page table entry to return
127     */
128    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
129    {
130        pTableCache[2].entry = pTableCache[1].entry;
131        pTableCache[2].vaddr = pTableCache[1].vaddr;
132        pTableCache[1].entry = pTableCache[0].entry;
133        pTableCache[1].vaddr = pTableCache[0].vaddr;
134        pTableCache[0].entry = entry;
135        pTableCache[0].vaddr = vaddr;
136    }
137
138
139    void serialize(std::ostream &os);
140
141    void unserialize(Checkpoint *cp, const std::string &section);
142};
143
144#endif // __MEM_PAGE_TABLE_HH__
145