page_table.hh revision 6658:f4de76601762 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31/**
32 * @file
33 * Declaration of a non-full system Page Table.
34 */
35
36#ifndef __MEM_PAGE_TABLE_HH__
37#define __MEM_PAGE_TABLE_HH__
38
39#include <string>
40
41#include "arch/isa_traits.hh"
42#include "arch/tlb.hh"
43#include "base/hashmap.hh"
44#include "base/types.hh"
45#include "config/the_isa.hh"
46#include "mem/request.hh"
47#include "sim/faults.hh"
48#include "sim/serialize.hh"
49
50class Process;
51
52/**
53 * Page Table Declaration.
54 */
55class PageTable
56{
57  protected:
58    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
59    typedef PTable::iterator PTableItr;
60    PTable pTable;
61
62    struct cacheElement {
63        Addr vaddr;
64        TheISA::TlbEntry entry;
65    };
66
67    struct cacheElement pTableCache[3];
68
69    const Addr pageSize;
70    const Addr offsetMask;
71
72    Process *process;
73
74  public:
75
76    PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
77
78    ~PageTable();
79
80    Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
81    Addr pageOffset(Addr a) { return (a &  offsetMask); }
82
83    void allocate(Addr vaddr, int64_t size);
84    void remap(Addr vaddr, int64_t size, Addr new_vaddr);
85    void deallocate(Addr vaddr, int64_t size);
86
87    /**
88     * Lookup function
89     * @param vaddr The virtual address.
90     * @return entry The page table entry corresponding to vaddr.
91     */
92    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
93
94    /**
95     * Translate function
96     * @param vaddr The virtual address.
97     * @param paddr Physical address from translation.
98     * @return True if translation exists
99     */
100    bool translate(Addr vaddr, Addr &paddr);
101
102    /**
103     * Simplified translate function (just check for translation)
104     * @param vaddr The virtual address.
105     * @return True if translation exists
106     */
107    bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
108
109    /**
110     * Perform a translation on the memory request, fills in paddr
111     * field of req.
112     * @param req The memory request.
113     */
114    Fault translate(RequestPtr req);
115
116    /**
117     * Update the page table cache.
118     * @param vaddr virtual address (page aligned) to check
119     * @param pte page table entry to return
120     */
121    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
122    {
123        pTableCache[2].entry = pTableCache[1].entry;
124        pTableCache[2].vaddr = pTableCache[1].vaddr;
125        pTableCache[1].entry = pTableCache[0].entry;
126        pTableCache[1].vaddr = pTableCache[0].vaddr;
127        pTableCache[0].entry = entry;
128        pTableCache[0].vaddr = vaddr;
129    }
130
131
132    void serialize(std::ostream &os);
133
134    void unserialize(Checkpoint *cp, const std::string &section);
135};
136
137#endif // __MEM_PAGE_TABLE_HH__
138