page_table.hh revision 5748:f28f020f3006
112855Sgabeblack@google.com/*
212855Sgabeblack@google.com * Copyright (c) 2003 The Regents of The University of Michigan
312855Sgabeblack@google.com * All rights reserved.
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2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2712855Sgabeblack@google.com *
2812855Sgabeblack@google.com * Authors: Steve Reinhardt
2912855Sgabeblack@google.com */
3012855Sgabeblack@google.com
3112855Sgabeblack@google.com/**
3212855Sgabeblack@google.com * @file
3312855Sgabeblack@google.com * Declaration of a non-full system Page Table.
3412855Sgabeblack@google.com */
3512855Sgabeblack@google.com
3612855Sgabeblack@google.com#ifndef __PAGE_TABLE__
3712855Sgabeblack@google.com#define __PAGE_TABLE__
3812855Sgabeblack@google.com
3912855Sgabeblack@google.com#include <string>
4012855Sgabeblack@google.com
4112855Sgabeblack@google.com#include "sim/faults.hh"
4212855Sgabeblack@google.com#include "arch/isa_traits.hh"
4312855Sgabeblack@google.com#include "arch/tlb.hh"
4412855Sgabeblack@google.com#include "base/hashmap.hh"
4512855Sgabeblack@google.com#include "mem/request.hh"
4612855Sgabeblack@google.com#include "sim/host.hh"
4712855Sgabeblack@google.com#include "sim/serialize.hh"
48
49class Process;
50
51/**
52 * Page Table Declaration.
53 */
54class PageTable
55{
56  protected:
57    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
58    typedef PTable::iterator PTableItr;
59    PTable pTable;
60
61    struct cacheElement {
62        Addr vaddr;
63        TheISA::TlbEntry entry;
64    };
65
66    struct cacheElement pTableCache[3];
67
68    const Addr pageSize;
69    const Addr offsetMask;
70
71    Process *process;
72
73  public:
74
75    PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
76
77    ~PageTable();
78
79    Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
80    Addr pageOffset(Addr a) { return (a &  offsetMask); }
81
82    void allocate(Addr vaddr, int64_t size);
83
84    /**
85     * Lookup function
86     * @param vaddr The virtual address.
87     * @return entry The page table entry corresponding to vaddr.
88     */
89    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
90
91    /**
92     * Translate function
93     * @param vaddr The virtual address.
94     * @param paddr Physical address from translation.
95     * @return True if translation exists
96     */
97    bool translate(Addr vaddr, Addr &paddr);
98
99    /**
100     * Simplified translate function (just check for translation)
101     * @param vaddr The virtual address.
102     * @return True if translation exists
103     */
104    bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
105
106    /**
107     * Perform a translation on the memory request, fills in paddr
108     * field of req.
109     * @param req The memory request.
110     */
111    Fault translate(RequestPtr req);
112
113    /**
114     * Update the page table cache.
115     * @param vaddr virtual address (page aligned) to check
116     * @param pte page table entry to return
117     */
118    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
119    {
120        pTableCache[2].entry = pTableCache[1].entry;
121        pTableCache[2].vaddr = pTableCache[1].vaddr;
122        pTableCache[1].entry = pTableCache[0].entry;
123        pTableCache[1].vaddr = pTableCache[0].vaddr;
124        pTableCache[0].entry = entry;
125        pTableCache[0].vaddr = vaddr;
126    }
127
128
129    void serialize(std::ostream &os);
130
131    void unserialize(Checkpoint *cp, const std::string &section);
132};
133
134#endif
135