page_table.hh revision 5004:7d94cedab264 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31/**
32 * @file
33 * Declaration of a non-full system Page Table.
34 */
35
36#ifndef __PAGE_TABLE__
37#define __PAGE_TABLE__
38
39#include <string>
40
41#include "sim/faults.hh"
42#include "arch/isa_traits.hh"
43#include "arch/tlb.hh"
44#include "base/hashmap.hh"
45#include "mem/request.hh"
46#include "sim/host.hh"
47#include "sim/serialize.hh"
48
49class System;
50
51/**
52 * Page Table Declaration.
53 */
54class PageTable
55{
56  protected:
57    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
58    typedef PTable::iterator PTableItr;
59    PTable pTable;
60
61    struct cacheElement {
62        Addr vaddr;
63        TheISA::TlbEntry entry;
64    };
65
66    struct cacheElement pTableCache[3];
67
68    const Addr pageSize;
69    const Addr offsetMask;
70
71    System *system;
72
73  public:
74
75    PageTable(System *_system, Addr _pageSize = TheISA::VMPageSize);
76
77    ~PageTable();
78
79    Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
80    Addr pageOffset(Addr a) { return (a &  offsetMask); }
81
82    void allocate(Addr vaddr, int64_t size);
83
84    /**
85     * Lookup function
86     * @param vaddr The virtual address.
87     * @return entry The page table entry corresponding to vaddr.
88     */
89    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
90
91    /**
92     * Translate function
93     * @param vaddr The virtual address.
94     * @return Physical address from translation.
95     */
96    bool translate(Addr vaddr, Addr &paddr);
97
98    /**
99     * Perform a translation on the memory request, fills in paddr
100     * field of req.
101     * @param req The memory request.
102     */
103    Fault translate(RequestPtr req);
104
105    /**
106     * Update the page table cache.
107     * @param vaddr virtual address (page aligned) to check
108     * @param pte page table entry to return
109     */
110    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
111    {
112        pTableCache[2].entry = pTableCache[1].entry;
113        pTableCache[2].vaddr = pTableCache[1].vaddr;
114        pTableCache[1].entry = pTableCache[0].entry;
115        pTableCache[1].vaddr = pTableCache[0].vaddr;
116        pTableCache[0].entry = entry;
117        pTableCache[0].vaddr = vaddr;
118    }
119
120
121    void serialize(std::ostream &os);
122
123    void unserialize(Checkpoint *cp, const std::string &section);
124};
125
126#endif
127