page_table.hh revision 10318:98771a936b61 
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2003 The Regents of The University of Michigan
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32/**
33 * @file
34 * Declarations of a non-full system Page Table.
35 */
36
37#ifndef __MEM_PAGE_TABLE_HH__
38#define __MEM_PAGE_TABLE_HH__
39
40#include <string>
41
42#include "arch/isa_traits.hh"
43#include "arch/tlb.hh"
44#include "base/hashmap.hh"
45#include "base/types.hh"
46#include "config/the_isa.hh"
47#include "mem/request.hh"
48#include "sim/serialize.hh"
49#include "sim/system.hh"
50
51class ThreadContext;
52
53/**
54 * Declaration of base class for page table
55 */
56class PageTableBase
57{
58  protected:
59    struct cacheElement {
60        bool valid;
61        Addr vaddr;
62        TheISA::TlbEntry entry;
63    };
64
65    struct cacheElement pTableCache[3];
66
67    const Addr pageSize;
68    const Addr offsetMask;
69
70    const uint64_t pid;
71    const std::string _name;
72
73  public:
74
75    PageTableBase(const std::string &__name, uint64_t _pid,
76              Addr _pageSize = TheISA::PageBytes)
77            : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
78              pid(_pid), _name(__name)
79    {
80        assert(isPowerOf2(pageSize));
81        pTableCache[0].valid = false;
82        pTableCache[1].valid = false;
83        pTableCache[2].valid = false;
84    }
85
86    virtual ~PageTableBase() {};
87
88    virtual void initState(ThreadContext* tc) = 0;
89
90    // for DPRINTF compatibility
91    const std::string name() const { return _name; }
92
93    Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
94    Addr pageOffset(Addr a) { return (a &  offsetMask); }
95
96    virtual void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false) = 0;
97    virtual void remap(Addr vaddr, int64_t size, Addr new_vaddr) = 0;
98    virtual void unmap(Addr vaddr, int64_t size) = 0;
99
100    /**
101     * Check if any pages in a region are already allocated
102     * @param vaddr The starting virtual address of the region.
103     * @param size The length of the region.
104     * @return True if no pages in the region are mapped.
105     */
106    virtual bool isUnmapped(Addr vaddr, int64_t size) = 0;
107
108    /**
109     * Lookup function
110     * @param vaddr The virtual address.
111     * @return entry The page table entry corresponding to vaddr.
112     */
113    virtual bool lookup(Addr vaddr, TheISA::TlbEntry &entry) = 0;
114
115    /**
116     * Translate function
117     * @param vaddr The virtual address.
118     * @param paddr Physical address from translation.
119     * @return True if translation exists
120     */
121    bool translate(Addr vaddr, Addr &paddr);
122
123    /**
124     * Simplified translate function (just check for translation)
125     * @param vaddr The virtual address.
126     * @return True if translation exists
127     */
128    bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
129
130    /**
131     * Perform a translation on the memory request, fills in paddr
132     * field of req.
133     * @param req The memory request.
134     */
135    Fault translate(RequestPtr req);
136
137    /**
138     * Update the page table cache.
139     * @param vaddr virtual address (page aligned) to check
140     * @param pte page table entry to return
141     */
142    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
143    {
144        pTableCache[2].entry = pTableCache[1].entry;
145        pTableCache[2].vaddr = pTableCache[1].vaddr;
146        pTableCache[2].valid = pTableCache[1].valid;
147
148        pTableCache[1].entry = pTableCache[0].entry;
149        pTableCache[1].vaddr = pTableCache[0].vaddr;
150        pTableCache[1].valid = pTableCache[0].valid;
151
152        pTableCache[0].entry = entry;
153        pTableCache[0].vaddr = vaddr;
154        pTableCache[0].valid = true;
155    }
156
157    /**
158     * Erase an entry from the page table cache.
159     * @param vaddr virtual address (page aligned) to check
160     */
161    inline void eraseCacheEntry(Addr vaddr)
162    {
163        // Invalidate cached entries if necessary
164        if (pTableCache[0].valid && pTableCache[0].vaddr == vaddr) {
165            pTableCache[0].valid = false;
166        } else if (pTableCache[1].valid && pTableCache[1].vaddr == vaddr) {
167            pTableCache[1].valid = false;
168        } else if (pTableCache[2].valid && pTableCache[2].vaddr == vaddr) {
169            pTableCache[2].valid = false;
170        }
171    }
172
173    virtual void serialize(std::ostream &os) = 0;
174
175    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
176};
177
178/**
179 * Declaration of functional page table.
180 */
181class FuncPageTable : public PageTableBase
182{
183  private:
184    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
185    typedef PTable::iterator PTableItr;
186    PTable pTable;
187
188  public:
189
190    FuncPageTable(const std::string &__name, uint64_t _pid,
191                  Addr _pageSize = TheISA::PageBytes);
192
193    ~FuncPageTable();
194
195    void initState(ThreadContext* tc)
196    {
197    }
198
199    void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
200    void remap(Addr vaddr, int64_t size, Addr new_vaddr);
201    void unmap(Addr vaddr, int64_t size);
202
203    /**
204     * Check if any pages in a region are already allocated
205     * @param vaddr The starting virtual address of the region.
206     * @param size The length of the region.
207     * @return True if no pages in the region are mapped.
208     */
209    bool isUnmapped(Addr vaddr, int64_t size);
210
211    /**
212     * Lookup function
213     * @param vaddr The virtual address.
214     * @return entry The page table entry corresponding to vaddr.
215     */
216    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
217
218    void serialize(std::ostream &os);
219
220    void unserialize(Checkpoint *cp, const std::string &section);
221};
222
223/**
224 * Faux page table class indended to stop the usage of
225 * an architectural page table, when there is none defined
226 * for a particular ISA.
227 */
228class NoArchPageTable : public FuncPageTable
229{
230  public:
231    NoArchPageTable(const std::string &__name, uint64_t _pid, System *_sys,
232              Addr _pageSize = TheISA::PageBytes) : FuncPageTable(__name, _pid)
233    {
234        fatal("No architectural page table defined for this ISA.\n");
235    }
236};
237
238#endif // __MEM_PAGE_TABLE_HH__
239