page_table.hh revision 9676
12379SN/A/* 22379SN/A * Copyright (c) 2003 The Regents of The University of Michigan 32379SN/A * All rights reserved. 42379SN/A * 52379SN/A * Redistribution and use in source and binary forms, with or without 62379SN/A * modification, are permitted provided that the following conditions are 72379SN/A * met: redistributions of source code must retain the above copyright 82379SN/A * notice, this list of conditions and the following disclaimer; 92379SN/A * redistributions in binary form must reproduce the above copyright 102379SN/A * notice, this list of conditions and the following disclaimer in the 112379SN/A * documentation and/or other materials provided with the distribution; 122379SN/A * neither the name of the copyright holders nor the names of its 132379SN/A * contributors may be used to endorse or promote products derived from 142379SN/A * this software without specific prior written permission. 152379SN/A * 162379SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172379SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182379SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192379SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202379SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212379SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222379SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232379SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242379SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252379SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262379SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292379SN/A */ 302379SN/A 312379SN/A/** 322379SN/A * @file 332379SN/A * Declaration of a non-full system Page Table. 342379SN/A */ 352379SN/A 366216Snate@binkert.org#ifndef __MEM_PAGE_TABLE_HH__ 376216Snate@binkert.org#define __MEM_PAGE_TABLE_HH__ 382379SN/A 392379SN/A#include <string> 402379SN/A 412423SN/A#include "arch/isa_traits.hh" 425004Sgblack@eecs.umich.edu#include "arch/tlb.hh" 432809Ssaidi@eecs.umich.edu#include "base/hashmap.hh" 446216Snate@binkert.org#include "base/types.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 462394SN/A#include "mem/request.hh" 475004Sgblack@eecs.umich.edu#include "sim/serialize.hh" 482379SN/A 492379SN/A/** 502982Sstever@eecs.umich.edu * Page Table Declaration. 512379SN/A */ 522399SN/Aclass PageTable 532379SN/A{ 542379SN/A protected: 555004Sgblack@eecs.umich.edu typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable; 565004Sgblack@eecs.umich.edu typedef PTable::iterator PTableItr; 575004Sgblack@eecs.umich.edu PTable pTable; 582809Ssaidi@eecs.umich.edu 592809Ssaidi@eecs.umich.edu struct cacheElement { 609676Smitch.hayenga+gem5@gmail.com bool valid; 612809Ssaidi@eecs.umich.edu Addr vaddr; 625004Sgblack@eecs.umich.edu TheISA::TlbEntry entry; 635004Sgblack@eecs.umich.edu }; 642809Ssaidi@eecs.umich.edu 652809Ssaidi@eecs.umich.edu struct cacheElement pTableCache[3]; 662379SN/A 672399SN/A const Addr pageSize; 682399SN/A const Addr offsetMask; 692399SN/A 708601Ssteve.reinhardt@amd.com const uint64_t pid; 718601Ssteve.reinhardt@amd.com const std::string _name; 722379SN/A 732379SN/A public: 742379SN/A 758601Ssteve.reinhardt@amd.com PageTable(const std::string &__name, uint64_t _pid, 768601Ssteve.reinhardt@amd.com Addr _pageSize = TheISA::VMPageSize); 772379SN/A 782379SN/A ~PageTable(); 792379SN/A 808601Ssteve.reinhardt@amd.com // for DPRINTF compatibility 818601Ssteve.reinhardt@amd.com const std::string name() const { return _name; } 828601Ssteve.reinhardt@amd.com 832399SN/A Addr pageAlign(Addr a) { return (a & ~offsetMask); } 842399SN/A Addr pageOffset(Addr a) { return (a & offsetMask); } 852379SN/A 868601Ssteve.reinhardt@amd.com void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false); 875877Shsul@eecs.umich.edu void remap(Addr vaddr, int64_t size, Addr new_vaddr); 888601Ssteve.reinhardt@amd.com void unmap(Addr vaddr, int64_t size); 892379SN/A 905004Sgblack@eecs.umich.edu /** 918600Ssteve.reinhardt@amd.com * Check if any pages in a region are already allocated 928600Ssteve.reinhardt@amd.com * @param vaddr The starting virtual address of the region. 938600Ssteve.reinhardt@amd.com * @param size The length of the region. 948600Ssteve.reinhardt@amd.com * @return True if no pages in the region are mapped. 958600Ssteve.reinhardt@amd.com */ 968600Ssteve.reinhardt@amd.com bool isUnmapped(Addr vaddr, int64_t size); 978600Ssteve.reinhardt@amd.com 988600Ssteve.reinhardt@amd.com /** 995004Sgblack@eecs.umich.edu * Lookup function 1005004Sgblack@eecs.umich.edu * @param vaddr The virtual address. 1015004Sgblack@eecs.umich.edu * @return entry The page table entry corresponding to vaddr. 1025004Sgblack@eecs.umich.edu */ 1035004Sgblack@eecs.umich.edu bool lookup(Addr vaddr, TheISA::TlbEntry &entry); 1042399SN/A 1052379SN/A /** 1062379SN/A * Translate function 1072379SN/A * @param vaddr The virtual address. 1085748SSteve.Reinhardt@amd.com * @param paddr Physical address from translation. 1095748SSteve.Reinhardt@amd.com * @return True if translation exists 1102379SN/A */ 1112399SN/A bool translate(Addr vaddr, Addr &paddr); 1122379SN/A 1132379SN/A /** 1145748SSteve.Reinhardt@amd.com * Simplified translate function (just check for translation) 1155748SSteve.Reinhardt@amd.com * @param vaddr The virtual address. 1165748SSteve.Reinhardt@amd.com * @return True if translation exists 1175748SSteve.Reinhardt@amd.com */ 1185748SSteve.Reinhardt@amd.com bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); } 1195748SSteve.Reinhardt@amd.com 1205748SSteve.Reinhardt@amd.com /** 1212399SN/A * Perform a translation on the memory request, fills in paddr 1225004Sgblack@eecs.umich.edu * field of req. 1232379SN/A * @param req The memory request. 1242379SN/A */ 1255004Sgblack@eecs.umich.edu Fault translate(RequestPtr req); 1262379SN/A 1274521Ssaidi@eecs.umich.edu /** 1284521Ssaidi@eecs.umich.edu * Update the page table cache. 1294521Ssaidi@eecs.umich.edu * @param vaddr virtual address (page aligned) to check 1305004Sgblack@eecs.umich.edu * @param pte page table entry to return 1314521Ssaidi@eecs.umich.edu */ 1325004Sgblack@eecs.umich.edu inline void updateCache(Addr vaddr, TheISA::TlbEntry entry) 1334521Ssaidi@eecs.umich.edu { 1345004Sgblack@eecs.umich.edu pTableCache[2].entry = pTableCache[1].entry; 1354521Ssaidi@eecs.umich.edu pTableCache[2].vaddr = pTableCache[1].vaddr; 1369676Smitch.hayenga+gem5@gmail.com pTableCache[2].valid = pTableCache[1].valid; 1379676Smitch.hayenga+gem5@gmail.com 1385004Sgblack@eecs.umich.edu pTableCache[1].entry = pTableCache[0].entry; 1394521Ssaidi@eecs.umich.edu pTableCache[1].vaddr = pTableCache[0].vaddr; 1409676Smitch.hayenga+gem5@gmail.com pTableCache[1].valid = pTableCache[0].valid; 1419676Smitch.hayenga+gem5@gmail.com 1425004Sgblack@eecs.umich.edu pTableCache[0].entry = entry; 1434521Ssaidi@eecs.umich.edu pTableCache[0].vaddr = vaddr; 1449676Smitch.hayenga+gem5@gmail.com pTableCache[0].valid = true; 1454521Ssaidi@eecs.umich.edu } 1464521Ssaidi@eecs.umich.edu 1479676Smitch.hayenga+gem5@gmail.com /** 1489676Smitch.hayenga+gem5@gmail.com * Erase an entry from the page table cache. 1499676Smitch.hayenga+gem5@gmail.com * @param vaddr virtual address (page aligned) to check 1509676Smitch.hayenga+gem5@gmail.com */ 1519676Smitch.hayenga+gem5@gmail.com inline void eraseCacheEntry(Addr vaddr) 1529676Smitch.hayenga+gem5@gmail.com { 1539676Smitch.hayenga+gem5@gmail.com // Invalidate cached entries if necessary 1549676Smitch.hayenga+gem5@gmail.com if (pTableCache[0].valid && pTableCache[0].vaddr == vaddr) { 1559676Smitch.hayenga+gem5@gmail.com pTableCache[0].valid = false; 1569676Smitch.hayenga+gem5@gmail.com } else if (pTableCache[1].valid && pTableCache[1].vaddr == vaddr) { 1579676Smitch.hayenga+gem5@gmail.com pTableCache[1].valid = false; 1589676Smitch.hayenga+gem5@gmail.com } else if (pTableCache[2].valid && pTableCache[2].vaddr == vaddr) { 1599676Smitch.hayenga+gem5@gmail.com pTableCache[2].valid = false; 1609676Smitch.hayenga+gem5@gmail.com } 1619676Smitch.hayenga+gem5@gmail.com } 1624521Ssaidi@eecs.umich.edu 1633311Ssaidi@eecs.umich.edu void serialize(std::ostream &os); 1645004Sgblack@eecs.umich.edu 1653311Ssaidi@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 1662379SN/A}; 1672379SN/A 1686216Snate@binkert.org#endif // __MEM_PAGE_TABLE_HH__ 169