packet.cc revision 3605
12568SN/A/* 22568SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32568SN/A * All rights reserved. 42568SN/A * 52568SN/A * Redistribution and use in source and binary forms, with or without 62568SN/A * modification, are permitted provided that the following conditions are 72568SN/A * met: redistributions of source code must retain the above copyright 82568SN/A * notice, this list of conditions and the following disclaimer; 92568SN/A * redistributions in binary form must reproduce the above copyright 102568SN/A * notice, this list of conditions and the following disclaimer in the 112568SN/A * documentation and/or other materials provided with the distribution; 122568SN/A * neither the name of the copyright holders nor the names of its 132568SN/A * contributors may be used to endorse or promote products derived from 142568SN/A * this software without specific prior written permission. 152568SN/A * 162568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302568SN/A */ 312568SN/A 322568SN/A/** 332568SN/A * @file 342568SN/A * Definition of the Packet Class, a packet is a transaction occuring 352568SN/A * between a single level of the memory heirarchy (ie L1->L2). 362568SN/A */ 373260Ssaidi@eecs.umich.edu 383260Ssaidi@eecs.umich.edu#include <iostream> 393348Sbinkertn@umich.edu 402590SN/A#include "base/misc.hh" 413348Sbinkertn@umich.edu#include "base/trace.hh" 422568SN/A#include "mem/packet.hh" 432568SN/A 442641Sstever@eecs.umich.edustatic const std::string ReadReqString("ReadReq"); 452641Sstever@eecs.umich.edustatic const std::string WriteReqString("WriteReq"); 463262Srdreslin@umich.edustatic const std::string WriteReqNoAckString("WriteReqNoAck|Writeback"); 472641Sstever@eecs.umich.edustatic const std::string ReadRespString("ReadResp"); 482641Sstever@eecs.umich.edustatic const std::string WriteRespString("WriteResp"); 493262Srdreslin@umich.edustatic const std::string SoftPFReqString("SoftPFReq"); 503262Srdreslin@umich.edustatic const std::string SoftPFRespString("SoftPFResp"); 513262Srdreslin@umich.edustatic const std::string HardPFReqString("HardPFReq"); 523262Srdreslin@umich.edustatic const std::string HardPFRespString("HardPFResp"); 533262Srdreslin@umich.edustatic const std::string InvalidateReqString("InvalidateReq"); 543262Srdreslin@umich.edustatic const std::string WriteInvalidateReqString("WriteInvalidateReq"); 553335Srdreslin@umich.edustatic const std::string WriteInvalidateRespString("WriteInvalidateResp"); 563262Srdreslin@umich.edustatic const std::string UpgradeReqString("UpgradeReq"); 573262Srdreslin@umich.edustatic const std::string ReadExReqString("ReadExReq"); 583262Srdreslin@umich.edustatic const std::string ReadExRespString("ReadExResp"); 592641Sstever@eecs.umich.edustatic const std::string OtherCmdString("<other>"); 602641Sstever@eecs.umich.edu 612641Sstever@eecs.umich.educonst std::string & 622641Sstever@eecs.umich.eduPacket::cmdString() const 632641Sstever@eecs.umich.edu{ 642641Sstever@eecs.umich.edu switch (cmd) { 652641Sstever@eecs.umich.edu case ReadReq: return ReadReqString; 662641Sstever@eecs.umich.edu case WriteReq: return WriteReqString; 672641Sstever@eecs.umich.edu case WriteReqNoAck: return WriteReqNoAckString; 682641Sstever@eecs.umich.edu case ReadResp: return ReadRespString; 692641Sstever@eecs.umich.edu case WriteResp: return WriteRespString; 703262Srdreslin@umich.edu case SoftPFReq: return SoftPFReqString; 713262Srdreslin@umich.edu case SoftPFResp: return SoftPFRespString; 723262Srdreslin@umich.edu case HardPFReq: return HardPFReqString; 733262Srdreslin@umich.edu case HardPFResp: return HardPFRespString; 743262Srdreslin@umich.edu case InvalidateReq: return InvalidateReqString; 753262Srdreslin@umich.edu case WriteInvalidateReq:return WriteInvalidateReqString; 763335Srdreslin@umich.edu case WriteInvalidateResp:return WriteInvalidateRespString; 773262Srdreslin@umich.edu case UpgradeReq: return UpgradeReqString; 783262Srdreslin@umich.edu case ReadExReq: return ReadExReqString; 793262Srdreslin@umich.edu case ReadExResp: return ReadExRespString; 802641Sstever@eecs.umich.edu default: return OtherCmdString; 812641Sstever@eecs.umich.edu } 822641Sstever@eecs.umich.edu} 832592SN/A 842811Srdreslin@umich.educonst std::string & 852811Srdreslin@umich.eduPacket::cmdIdxToString(Packet::Command idx) 862811Srdreslin@umich.edu{ 872811Srdreslin@umich.edu switch (idx) { 882811Srdreslin@umich.edu case ReadReq: return ReadReqString; 892811Srdreslin@umich.edu case WriteReq: return WriteReqString; 902811Srdreslin@umich.edu case WriteReqNoAck: return WriteReqNoAckString; 912811Srdreslin@umich.edu case ReadResp: return ReadRespString; 922811Srdreslin@umich.edu case WriteResp: return WriteRespString; 933262Srdreslin@umich.edu case SoftPFReq: return SoftPFReqString; 943262Srdreslin@umich.edu case SoftPFResp: return SoftPFRespString; 953262Srdreslin@umich.edu case HardPFReq: return HardPFReqString; 963262Srdreslin@umich.edu case HardPFResp: return HardPFRespString; 973262Srdreslin@umich.edu case InvalidateReq: return InvalidateReqString; 983262Srdreslin@umich.edu case WriteInvalidateReq:return WriteInvalidateReqString; 993335Srdreslin@umich.edu case WriteInvalidateResp:return WriteInvalidateRespString; 1003262Srdreslin@umich.edu case UpgradeReq: return UpgradeReqString; 1013262Srdreslin@umich.edu case ReadExReq: return ReadExReqString; 1023262Srdreslin@umich.edu case ReadExResp: return ReadExRespString; 1032811Srdreslin@umich.edu default: return OtherCmdString; 1042811Srdreslin@umich.edu } 1052811Srdreslin@umich.edu} 1062811Srdreslin@umich.edu 1072592SN/A/** delete the data pointed to in the data pointer. Ok to call to matter how 1082592SN/A * data was allocted. */ 1092592SN/Avoid 1102641Sstever@eecs.umich.eduPacket::deleteData() 1112641Sstever@eecs.umich.edu{ 1122592SN/A assert(staticData || dynamicData); 1132592SN/A if (staticData) 1142592SN/A return; 1152592SN/A 1162592SN/A if (arrayData) 1172592SN/A delete [] data; 1182592SN/A else 1192592SN/A delete data; 1202592SN/A} 1212592SN/A 1222592SN/A/** If there isn't data in the packet, allocate some. */ 1232592SN/Avoid 1242641Sstever@eecs.umich.eduPacket::allocate() 1252641Sstever@eecs.umich.edu{ 1262592SN/A if (data) 1272592SN/A return; 1282592SN/A assert(!staticData); 1292592SN/A dynamicData = true; 1302592SN/A arrayData = true; 1312641Sstever@eecs.umich.edu data = new uint8_t[getSize()]; 1322592SN/A} 1332592SN/A 1342592SN/A/** Do the packet modify the same addresses. */ 1352592SN/Abool 1363349Sbinkertn@umich.eduPacket::intersect(PacketPtr p) 1372641Sstever@eecs.umich.edu{ 1382641Sstever@eecs.umich.edu Addr s1 = getAddr(); 1393242Sgblack@eecs.umich.edu Addr e1 = getAddr() + getSize() - 1; 1402641Sstever@eecs.umich.edu Addr s2 = p->getAddr(); 1413242Sgblack@eecs.umich.edu Addr e2 = p->getAddr() + p->getSize() - 1; 1422592SN/A 1433242Sgblack@eecs.umich.edu return !(s1 > e2 || e1 < s2); 1442592SN/A} 1452592SN/A 1462641Sstever@eecs.umich.edubool 1473349Sbinkertn@umich.edufixPacket(PacketPtr func, PacketPtr timing) 1482641Sstever@eecs.umich.edu{ 1493260Ssaidi@eecs.umich.edu Addr funcStart = func->getAddr(); 1503260Ssaidi@eecs.umich.edu Addr funcEnd = func->getAddr() + func->getSize() - 1; 1513260Ssaidi@eecs.umich.edu Addr timingStart = timing->getAddr(); 1523260Ssaidi@eecs.umich.edu Addr timingEnd = timing->getAddr() + timing->getSize() - 1; 1533260Ssaidi@eecs.umich.edu 1543342Srdreslin@umich.edu assert(!(funcStart > timingEnd || timingStart > funcEnd)); 1553260Ssaidi@eecs.umich.edu 1563260Ssaidi@eecs.umich.edu if (DTRACE(FunctionalAccess)) { 1573260Ssaidi@eecs.umich.edu DebugOut() << func; 1583260Ssaidi@eecs.umich.edu DebugOut() << timing; 1593260Ssaidi@eecs.umich.edu } 1603260Ssaidi@eecs.umich.edu 1613260Ssaidi@eecs.umich.edu // this packet can't solve our problem, continue on 1623260Ssaidi@eecs.umich.edu if (!timing->hasData()) 1633260Ssaidi@eecs.umich.edu return true; 1643260Ssaidi@eecs.umich.edu 1653260Ssaidi@eecs.umich.edu if (func->isRead()) { 1663260Ssaidi@eecs.umich.edu if (funcStart >= timingStart && funcEnd <= timingEnd) { 1673260Ssaidi@eecs.umich.edu func->allocate(); 1683260Ssaidi@eecs.umich.edu memcpy(func->getPtr<uint8_t>(), timing->getPtr<uint8_t>() + 1693260Ssaidi@eecs.umich.edu funcStart - timingStart, func->getSize()); 1703260Ssaidi@eecs.umich.edu func->result = Packet::Success; 1713605Srdreslin@umich.edu func->flags |= SATISFIED; 1723260Ssaidi@eecs.umich.edu return false; 1733260Ssaidi@eecs.umich.edu } else { 1743260Ssaidi@eecs.umich.edu // In this case the timing packet only partially satisfies the 1753260Ssaidi@eecs.umich.edu // requset, so we would need more information to make this work. 1763260Ssaidi@eecs.umich.edu // Like bytes valid in the packet or something, so the request could 1773260Ssaidi@eecs.umich.edu // continue and get this bit of possibly newer data along with the 1783260Ssaidi@eecs.umich.edu // older data not written to yet. 1793260Ssaidi@eecs.umich.edu panic("Timing packet only partially satisfies the functional" 1803260Ssaidi@eecs.umich.edu "request. Now what?"); 1813260Ssaidi@eecs.umich.edu } 1823260Ssaidi@eecs.umich.edu } else if (func->isWrite()) { 1833260Ssaidi@eecs.umich.edu if (funcStart >= timingStart) { 1843260Ssaidi@eecs.umich.edu memcpy(timing->getPtr<uint8_t>() + (funcStart - timingStart), 1853260Ssaidi@eecs.umich.edu func->getPtr<uint8_t>(), 1863605Srdreslin@umich.edu (std::min(funcEnd, timingEnd) - funcStart) + 1); 1873260Ssaidi@eecs.umich.edu } else { // timingStart > funcStart 1883260Ssaidi@eecs.umich.edu memcpy(timing->getPtr<uint8_t>(), 1893260Ssaidi@eecs.umich.edu func->getPtr<uint8_t>() + (timingStart - funcStart), 1903605Srdreslin@umich.edu (std::min(funcEnd, timingEnd) - timingStart) + 1); 1913260Ssaidi@eecs.umich.edu } 1923260Ssaidi@eecs.umich.edu // we always want to keep going with a write 1933260Ssaidi@eecs.umich.edu return true; 1943260Ssaidi@eecs.umich.edu } else 1953260Ssaidi@eecs.umich.edu panic("Don't know how to handle command type %#x\n", 1963260Ssaidi@eecs.umich.edu func->cmdToIndex()); 1973260Ssaidi@eecs.umich.edu 1982641Sstever@eecs.umich.edu} 1993260Ssaidi@eecs.umich.edu 2003260Ssaidi@eecs.umich.edu 2013260Ssaidi@eecs.umich.edustd::ostream & 2023260Ssaidi@eecs.umich.eduoperator<<(std::ostream &o, const Packet &p) 2033260Ssaidi@eecs.umich.edu{ 2043260Ssaidi@eecs.umich.edu 2053260Ssaidi@eecs.umich.edu o << "[0x"; 2063260Ssaidi@eecs.umich.edu o.setf(std::ios_base::hex, std::ios_base::showbase); 2073260Ssaidi@eecs.umich.edu o << p.getAddr(); 2083260Ssaidi@eecs.umich.edu o.unsetf(std::ios_base::hex| std::ios_base::showbase); 2093260Ssaidi@eecs.umich.edu o << ":"; 2103260Ssaidi@eecs.umich.edu o.setf(std::ios_base::hex, std::ios_base::showbase); 2113260Ssaidi@eecs.umich.edu o << p.getAddr() + p.getSize() - 1 << "] "; 2123260Ssaidi@eecs.umich.edu o.unsetf(std::ios_base::hex| std::ios_base::showbase); 2133260Ssaidi@eecs.umich.edu 2143260Ssaidi@eecs.umich.edu if (p.result == Packet::Success) 2153260Ssaidi@eecs.umich.edu o << "Successful "; 2163260Ssaidi@eecs.umich.edu if (p.result == Packet::BadAddress) 2173260Ssaidi@eecs.umich.edu o << "BadAddress "; 2183260Ssaidi@eecs.umich.edu if (p.result == Packet::Nacked) 2193260Ssaidi@eecs.umich.edu o << "Nacked "; 2203260Ssaidi@eecs.umich.edu if (p.result == Packet::Unknown) 2213260Ssaidi@eecs.umich.edu o << "Inflight "; 2223260Ssaidi@eecs.umich.edu 2233260Ssaidi@eecs.umich.edu if (p.isRead()) 2243260Ssaidi@eecs.umich.edu o << "Read "; 2253260Ssaidi@eecs.umich.edu if (p.isWrite()) 2263260Ssaidi@eecs.umich.edu o << "Read "; 2273260Ssaidi@eecs.umich.edu if (p.isInvalidate()) 2283260Ssaidi@eecs.umich.edu o << "Read "; 2293260Ssaidi@eecs.umich.edu if (p.isRequest()) 2303260Ssaidi@eecs.umich.edu o << "Request "; 2313260Ssaidi@eecs.umich.edu if (p.isResponse()) 2323260Ssaidi@eecs.umich.edu o << "Response "; 2333260Ssaidi@eecs.umich.edu if (p.hasData()) 2343260Ssaidi@eecs.umich.edu o << "w/Data "; 2353260Ssaidi@eecs.umich.edu 2363260Ssaidi@eecs.umich.edu o << std::endl; 2373260Ssaidi@eecs.umich.edu return o; 2383260Ssaidi@eecs.umich.edu} 2393260Ssaidi@eecs.umich.edu 240