packet.cc revision 3262
12568SN/A/* 22568SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32568SN/A * All rights reserved. 42568SN/A * 52568SN/A * Redistribution and use in source and binary forms, with or without 62568SN/A * modification, are permitted provided that the following conditions are 72568SN/A * met: redistributions of source code must retain the above copyright 82568SN/A * notice, this list of conditions and the following disclaimer; 92568SN/A * redistributions in binary form must reproduce the above copyright 102568SN/A * notice, this list of conditions and the following disclaimer in the 112568SN/A * documentation and/or other materials provided with the distribution; 122568SN/A * neither the name of the copyright holders nor the names of its 132568SN/A * contributors may be used to endorse or promote products derived from 142568SN/A * this software without specific prior written permission. 152568SN/A * 162568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302568SN/A */ 312568SN/A 322568SN/A/** 332568SN/A * @file 342568SN/A * Definition of the Packet Class, a packet is a transaction occuring 352568SN/A * between a single level of the memory heirarchy (ie L1->L2). 362568SN/A */ 372590SN/A#include "base/misc.hh" 382568SN/A#include "mem/packet.hh" 392568SN/A 402641Sstever@eecs.umich.edustatic const std::string ReadReqString("ReadReq"); 412641Sstever@eecs.umich.edustatic const std::string WriteReqString("WriteReq"); 423262Srdreslin@umich.edustatic const std::string WriteReqNoAckString("WriteReqNoAck|Writeback"); 432641Sstever@eecs.umich.edustatic const std::string ReadRespString("ReadResp"); 442641Sstever@eecs.umich.edustatic const std::string WriteRespString("WriteResp"); 453262Srdreslin@umich.edustatic const std::string SoftPFReqString("SoftPFReq"); 463262Srdreslin@umich.edustatic const std::string SoftPFRespString("SoftPFResp"); 473262Srdreslin@umich.edustatic const std::string HardPFReqString("HardPFReq"); 483262Srdreslin@umich.edustatic const std::string HardPFRespString("HardPFResp"); 493262Srdreslin@umich.edustatic const std::string InvalidateReqString("InvalidateReq"); 503262Srdreslin@umich.edustatic const std::string WriteInvalidateReqString("WriteInvalidateReq"); 513262Srdreslin@umich.edustatic const std::string UpgradeReqString("UpgradeReq"); 523262Srdreslin@umich.edustatic const std::string ReadExReqString("ReadExReq"); 533262Srdreslin@umich.edustatic const std::string ReadExRespString("ReadExResp"); 542641Sstever@eecs.umich.edustatic const std::string OtherCmdString("<other>"); 552641Sstever@eecs.umich.edu 562641Sstever@eecs.umich.educonst std::string & 572641Sstever@eecs.umich.eduPacket::cmdString() const 582641Sstever@eecs.umich.edu{ 592641Sstever@eecs.umich.edu switch (cmd) { 602641Sstever@eecs.umich.edu case ReadReq: return ReadReqString; 612641Sstever@eecs.umich.edu case WriteReq: return WriteReqString; 622641Sstever@eecs.umich.edu case WriteReqNoAck: return WriteReqNoAckString; 632641Sstever@eecs.umich.edu case ReadResp: return ReadRespString; 642641Sstever@eecs.umich.edu case WriteResp: return WriteRespString; 653262Srdreslin@umich.edu case SoftPFReq: return SoftPFReqString; 663262Srdreslin@umich.edu case SoftPFResp: return SoftPFRespString; 673262Srdreslin@umich.edu case HardPFReq: return HardPFReqString; 683262Srdreslin@umich.edu case HardPFResp: return HardPFRespString; 693262Srdreslin@umich.edu case InvalidateReq: return InvalidateReqString; 703262Srdreslin@umich.edu case WriteInvalidateReq:return WriteInvalidateReqString; 713262Srdreslin@umich.edu case UpgradeReq: return UpgradeReqString; 723262Srdreslin@umich.edu case ReadExReq: return ReadExReqString; 733262Srdreslin@umich.edu case ReadExResp: return ReadExRespString; 742641Sstever@eecs.umich.edu default: return OtherCmdString; 752641Sstever@eecs.umich.edu } 762641Sstever@eecs.umich.edu} 772592SN/A 782811Srdreslin@umich.educonst std::string & 792811Srdreslin@umich.eduPacket::cmdIdxToString(Packet::Command idx) 802811Srdreslin@umich.edu{ 812811Srdreslin@umich.edu switch (idx) { 822811Srdreslin@umich.edu case ReadReq: return ReadReqString; 832811Srdreslin@umich.edu case WriteReq: return WriteReqString; 842811Srdreslin@umich.edu case WriteReqNoAck: return WriteReqNoAckString; 852811Srdreslin@umich.edu case ReadResp: return ReadRespString; 862811Srdreslin@umich.edu case WriteResp: return WriteRespString; 873262Srdreslin@umich.edu case SoftPFReq: return SoftPFReqString; 883262Srdreslin@umich.edu case SoftPFResp: return SoftPFRespString; 893262Srdreslin@umich.edu case HardPFReq: return HardPFReqString; 903262Srdreslin@umich.edu case HardPFResp: return HardPFRespString; 913262Srdreslin@umich.edu case InvalidateReq: return InvalidateReqString; 923262Srdreslin@umich.edu case WriteInvalidateReq:return WriteInvalidateReqString; 933262Srdreslin@umich.edu case UpgradeReq: return UpgradeReqString; 943262Srdreslin@umich.edu case ReadExReq: return ReadExReqString; 953262Srdreslin@umich.edu case ReadExResp: return ReadExRespString; 962811Srdreslin@umich.edu default: return OtherCmdString; 972811Srdreslin@umich.edu } 982811Srdreslin@umich.edu} 992811Srdreslin@umich.edu 1002592SN/A/** delete the data pointed to in the data pointer. Ok to call to matter how 1012592SN/A * data was allocted. */ 1022592SN/Avoid 1032641Sstever@eecs.umich.eduPacket::deleteData() 1042641Sstever@eecs.umich.edu{ 1052592SN/A assert(staticData || dynamicData); 1062592SN/A if (staticData) 1072592SN/A return; 1082592SN/A 1092592SN/A if (arrayData) 1102592SN/A delete [] data; 1112592SN/A else 1122592SN/A delete data; 1132592SN/A} 1142592SN/A 1152592SN/A/** If there isn't data in the packet, allocate some. */ 1162592SN/Avoid 1172641Sstever@eecs.umich.eduPacket::allocate() 1182641Sstever@eecs.umich.edu{ 1192592SN/A if (data) 1202592SN/A return; 1212592SN/A assert(!staticData); 1222592SN/A dynamicData = true; 1232592SN/A arrayData = true; 1242641Sstever@eecs.umich.edu data = new uint8_t[getSize()]; 1252592SN/A} 1262592SN/A 1272592SN/A/** Do the packet modify the same addresses. */ 1282592SN/Abool 1292641Sstever@eecs.umich.eduPacket::intersect(Packet *p) 1302641Sstever@eecs.umich.edu{ 1312641Sstever@eecs.umich.edu Addr s1 = getAddr(); 1323242Sgblack@eecs.umich.edu Addr e1 = getAddr() + getSize() - 1; 1332641Sstever@eecs.umich.edu Addr s2 = p->getAddr(); 1343242Sgblack@eecs.umich.edu Addr e2 = p->getAddr() + p->getSize() - 1; 1352592SN/A 1363242Sgblack@eecs.umich.edu return !(s1 > e2 || e1 < s2); 1372592SN/A} 1382592SN/A 1392641Sstever@eecs.umich.edubool 1402641Sstever@eecs.umich.edufixPacket(Packet *func, Packet *timing) 1412641Sstever@eecs.umich.edu{ 1422641Sstever@eecs.umich.edu panic("Need to implement!"); 1432641Sstever@eecs.umich.edu} 144