packet.cc revision 2811
12568SN/A/* 22568SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32568SN/A * All rights reserved. 42568SN/A * 52568SN/A * Redistribution and use in source and binary forms, with or without 62568SN/A * modification, are permitted provided that the following conditions are 72568SN/A * met: redistributions of source code must retain the above copyright 82568SN/A * notice, this list of conditions and the following disclaimer; 92568SN/A * redistributions in binary form must reproduce the above copyright 102568SN/A * notice, this list of conditions and the following disclaimer in the 112568SN/A * documentation and/or other materials provided with the distribution; 122568SN/A * neither the name of the copyright holders nor the names of its 132568SN/A * contributors may be used to endorse or promote products derived from 142568SN/A * this software without specific prior written permission. 152568SN/A * 162568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302568SN/A */ 312568SN/A 322568SN/A/** 332568SN/A * @file 342568SN/A * Definition of the Packet Class, a packet is a transaction occuring 352568SN/A * between a single level of the memory heirarchy (ie L1->L2). 362568SN/A */ 372590SN/A#include "base/misc.hh" 382568SN/A#include "mem/packet.hh" 392568SN/A 402641Sstever@eecs.umich.edustatic const std::string ReadReqString("ReadReq"); 412641Sstever@eecs.umich.edustatic const std::string WriteReqString("WriteReq"); 422641Sstever@eecs.umich.edustatic const std::string WriteReqNoAckString("WriteReqNoAck"); 432641Sstever@eecs.umich.edustatic const std::string ReadRespString("ReadResp"); 442641Sstever@eecs.umich.edustatic const std::string WriteRespString("WriteResp"); 452641Sstever@eecs.umich.edustatic const std::string OtherCmdString("<other>"); 462641Sstever@eecs.umich.edu 472641Sstever@eecs.umich.educonst std::string & 482641Sstever@eecs.umich.eduPacket::cmdString() const 492641Sstever@eecs.umich.edu{ 502641Sstever@eecs.umich.edu switch (cmd) { 512641Sstever@eecs.umich.edu case ReadReq: return ReadReqString; 522641Sstever@eecs.umich.edu case WriteReq: return WriteReqString; 532641Sstever@eecs.umich.edu case WriteReqNoAck: return WriteReqNoAckString; 542641Sstever@eecs.umich.edu case ReadResp: return ReadRespString; 552641Sstever@eecs.umich.edu case WriteResp: return WriteRespString; 562641Sstever@eecs.umich.edu default: return OtherCmdString; 572641Sstever@eecs.umich.edu } 582641Sstever@eecs.umich.edu} 592592SN/A 602811Srdreslin@umich.educonst std::string & 612811Srdreslin@umich.eduPacket::cmdIdxToString(Packet::Command idx) 622811Srdreslin@umich.edu{ 632811Srdreslin@umich.edu switch (idx) { 642811Srdreslin@umich.edu case ReadReq: return ReadReqString; 652811Srdreslin@umich.edu case WriteReq: return WriteReqString; 662811Srdreslin@umich.edu case WriteReqNoAck: return WriteReqNoAckString; 672811Srdreslin@umich.edu case ReadResp: return ReadRespString; 682811Srdreslin@umich.edu case WriteResp: return WriteRespString; 692811Srdreslin@umich.edu default: return OtherCmdString; 702811Srdreslin@umich.edu } 712811Srdreslin@umich.edu} 722811Srdreslin@umich.edu 732592SN/A/** delete the data pointed to in the data pointer. Ok to call to matter how 742592SN/A * data was allocted. */ 752592SN/Avoid 762641Sstever@eecs.umich.eduPacket::deleteData() 772641Sstever@eecs.umich.edu{ 782592SN/A assert(staticData || dynamicData); 792592SN/A if (staticData) 802592SN/A return; 812592SN/A 822592SN/A if (arrayData) 832592SN/A delete [] data; 842592SN/A else 852592SN/A delete data; 862592SN/A} 872592SN/A 882592SN/A/** If there isn't data in the packet, allocate some. */ 892592SN/Avoid 902641Sstever@eecs.umich.eduPacket::allocate() 912641Sstever@eecs.umich.edu{ 922592SN/A if (data) 932592SN/A return; 942592SN/A assert(!staticData); 952592SN/A dynamicData = true; 962592SN/A arrayData = true; 972641Sstever@eecs.umich.edu data = new uint8_t[getSize()]; 982592SN/A} 992592SN/A 1002592SN/A/** Do the packet modify the same addresses. */ 1012592SN/Abool 1022641Sstever@eecs.umich.eduPacket::intersect(Packet *p) 1032641Sstever@eecs.umich.edu{ 1042641Sstever@eecs.umich.edu Addr s1 = getAddr(); 1052641Sstever@eecs.umich.edu Addr e1 = getAddr() + getSize(); 1062641Sstever@eecs.umich.edu Addr s2 = p->getAddr(); 1072641Sstever@eecs.umich.edu Addr e2 = p->getAddr() + p->getSize(); 1082592SN/A 1092592SN/A if (s1 >= s2 && s1 < e2) 1102592SN/A return true; 1112592SN/A if (e1 >= s2 && e1 < e2) 1122592SN/A return true; 1132592SN/A return false; 1142592SN/A} 1152592SN/A 1162641Sstever@eecs.umich.edubool 1172641Sstever@eecs.umich.edufixPacket(Packet *func, Packet *timing) 1182641Sstever@eecs.umich.edu{ 1192641Sstever@eecs.umich.edu panic("Need to implement!"); 1202641Sstever@eecs.umich.edu} 121