packet.cc revision 12823
12568SN/A/* 212652Sandreas.sandberg@arm.com * Copyright (c) 2011-2018 ARM Limited 38668Sgeoffrey.blake@arm.com * All rights reserved 48668Sgeoffrey.blake@arm.com * 58668Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68668Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78668Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88668Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98668Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108668Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118668Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128668Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138668Sgeoffrey.blake@arm.com * 142568SN/A * Copyright (c) 2006 The Regents of The University of Michigan 1510975Sdavid.hashe@amd.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162568SN/A * All rights reserved. 172568SN/A * 182568SN/A * Redistribution and use in source and binary forms, with or without 192568SN/A * modification, are permitted provided that the following conditions are 202568SN/A * met: redistributions of source code must retain the above copyright 212568SN/A * notice, this list of conditions and the following disclaimer; 222568SN/A * redistributions in binary form must reproduce the above copyright 232568SN/A * notice, this list of conditions and the following disclaimer in the 242568SN/A * documentation and/or other materials provided with the distribution; 252568SN/A * neither the name of the copyright holders nor the names of its 262568SN/A * contributors may be used to endorse or promote products derived from 272568SN/A * this software without specific prior written permission. 282568SN/A * 292568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 422665Ssaidi@eecs.umich.edu * Steve Reinhardt 432568SN/A */ 442568SN/A 452568SN/A/** 462568SN/A * @file 472568SN/A * Definition of the Packet Class, a packet is a transaction occuring 482568SN/A * between a single level of the memory heirarchy (ie L1->L2). 492568SN/A */ 503260Ssaidi@eecs.umich.edu 5111793Sbrandon.potter@amd.com#include "mem/packet.hh" 5211793Sbrandon.potter@amd.com 5312821Srmk35@cl.cam.ac.uk#include <algorithm> 548229Snate@binkert.org#include <cstring> 553260Ssaidi@eecs.umich.edu#include <iostream> 5612822Srmk35@cl.cam.ac.uk#include <sstream> 5712822Srmk35@cl.cam.ac.uk#include <string> 588229Snate@binkert.org 595314Sstever@gmail.com#include "base/cprintf.hh" 6012334Sgabeblack@google.com#include "base/logging.hh" 613348Sbinkertn@umich.edu#include "base/trace.hh" 6212652Sandreas.sandberg@arm.com#include "mem/packet_access.hh" 632568SN/A 644022Sstever@eecs.umich.edu// The one downside to bitsets is that static initializers can get ugly. 654022Sstever@eecs.umich.edu#define SET1(a1) (1 << (a1)) 664022Sstever@eecs.umich.edu#define SET2(a1, a2) (SET1(a1) | SET1(a2)) 674022Sstever@eecs.umich.edu#define SET3(a1, a2, a3) (SET2(a1, a2) | SET1(a3)) 684022Sstever@eecs.umich.edu#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4)) 694022Sstever@eecs.umich.edu#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5)) 704022Sstever@eecs.umich.edu#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6)) 7111600Sandreas.hansson@arm.com#define SET7(a1, a2, a3, a4, a5, a6, a7) (SET6(a1, a2, a3, a4, a5, a6) | \ 7211600Sandreas.hansson@arm.com SET1(a7)) 732641Sstever@eecs.umich.edu 744022Sstever@eecs.umich.educonst MemCmd::CommandInfo 754022Sstever@eecs.umich.eduMemCmd::commandInfo[] = 762641Sstever@eecs.umich.edu{ 774022Sstever@eecs.umich.edu /* InvalidCmd */ 784022Sstever@eecs.umich.edu { 0, InvalidCmd, "InvalidCmd" }, 7910885Sandreas.hansson@arm.com /* ReadReq - Read issued by a non-caching agent such as a CPU or 8010885Sandreas.hansson@arm.com * device, with no restrictions on alignment. */ 814022Sstever@eecs.umich.edu { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" }, 824473Sstever@eecs.umich.edu /* ReadResp */ 834473Sstever@eecs.umich.edu { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" }, 845319Sstever@gmail.com /* ReadRespWithInvalidate */ 855319Sstever@gmail.com { SET4(IsRead, IsResponse, HasData, IsInvalidate), 865319Sstever@gmail.com InvalidCmd, "ReadRespWithInvalidate" }, 874022Sstever@eecs.umich.edu /* WriteReq */ 8811284Sandreas.hansson@arm.com { SET5(IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData), 894022Sstever@eecs.umich.edu WriteResp, "WriteReq" }, 904022Sstever@eecs.umich.edu /* WriteResp */ 9111287Sandreas.hansson@arm.com { SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" }, 9211199Sandreas.hansson@arm.com /* WritebackDirty */ 9311600Sandreas.hansson@arm.com { SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache), 9411199Sandreas.hansson@arm.com InvalidCmd, "WritebackDirty" }, 9511199Sandreas.hansson@arm.com /* WritebackClean - This allows the upstream cache to writeback a 9611199Sandreas.hansson@arm.com * line to the downstream cache without it being considered 9711199Sandreas.hansson@arm.com * dirty. */ 9811600Sandreas.hansson@arm.com { SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache), 9911199Sandreas.hansson@arm.com InvalidCmd, "WritebackClean" }, 10012344Snikos.nikoleris@arm.com /* WriteClean - This allows a cache to write a dirty block to a memory 10112344Snikos.nikoleris@arm.com below without evicting its copy. */ 10212344Snikos.nikoleris@arm.com { SET4(IsWrite, IsRequest, HasData, FromCache), InvalidCmd, "WriteClean" }, 10310883Sali.jafri@arm.com /* CleanEvict */ 10411600Sandreas.hansson@arm.com { SET3(IsRequest, IsEviction, FromCache), InvalidCmd, "CleanEvict" }, 1054022Sstever@eecs.umich.edu /* SoftPFReq */ 1064022Sstever@eecs.umich.edu { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse), 1074022Sstever@eecs.umich.edu SoftPFResp, "SoftPFReq" }, 1084022Sstever@eecs.umich.edu /* HardPFReq */ 10911600Sandreas.hansson@arm.com { SET5(IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache), 1104022Sstever@eecs.umich.edu HardPFResp, "HardPFReq" }, 1114022Sstever@eecs.umich.edu /* SoftPFResp */ 1124022Sstever@eecs.umich.edu { SET4(IsRead, IsResponse, IsSWPrefetch, HasData), 1134022Sstever@eecs.umich.edu InvalidCmd, "SoftPFResp" }, 1144022Sstever@eecs.umich.edu /* HardPFResp */ 1154022Sstever@eecs.umich.edu { SET4(IsRead, IsResponse, IsHWPrefetch, HasData), 1164022Sstever@eecs.umich.edu InvalidCmd, "HardPFResp" }, 11710886Sandreas.hansson@arm.com /* WriteLineReq */ 11811284Sandreas.hansson@arm.com { SET5(IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData), 11910886Sandreas.hansson@arm.com WriteResp, "WriteLineReq" }, 1204022Sstever@eecs.umich.edu /* UpgradeReq */ 12111600Sandreas.hansson@arm.com { SET6(IsInvalidate, NeedsWritable, IsUpgrade, IsRequest, NeedsResponse, 12211600Sandreas.hansson@arm.com FromCache), 1234628Sstever@eecs.umich.edu UpgradeResp, "UpgradeReq" }, 1247465Ssteve.reinhardt@amd.com /* SCUpgradeReq: response could be UpgradeResp or UpgradeFailResp */ 12511600Sandreas.hansson@arm.com { SET7(IsInvalidate, NeedsWritable, IsUpgrade, IsLlsc, 12611600Sandreas.hansson@arm.com IsRequest, NeedsResponse, FromCache), 1277465Ssteve.reinhardt@amd.com UpgradeResp, "SCUpgradeReq" }, 1284628Sstever@eecs.umich.edu /* UpgradeResp */ 12911287Sandreas.hansson@arm.com { SET2(IsUpgrade, IsResponse), 1307465Ssteve.reinhardt@amd.com InvalidCmd, "UpgradeResp" }, 13110325Sgeoffrey.blake@arm.com /* SCUpgradeFailReq: generates UpgradeFailResp but still gets the data */ 13211600Sandreas.hansson@arm.com { SET7(IsRead, NeedsWritable, IsInvalidate, 13311600Sandreas.hansson@arm.com IsLlsc, IsRequest, NeedsResponse, FromCache), 1347465Ssteve.reinhardt@amd.com UpgradeFailResp, "SCUpgradeFailReq" }, 13510325Sgeoffrey.blake@arm.com /* UpgradeFailResp - Behaves like a ReadExReq, but notifies an SC 13610325Sgeoffrey.blake@arm.com * that it has failed, acquires line as Dirty*/ 13711287Sandreas.hansson@arm.com { SET3(IsRead, IsResponse, HasData), 1387465Ssteve.reinhardt@amd.com InvalidCmd, "UpgradeFailResp" }, 13910885Sandreas.hansson@arm.com /* ReadExReq - Read issues by a cache, always cache-line aligned, 14010885Sandreas.hansson@arm.com * and the response is guaranteed to be writeable (exclusive or 14110885Sandreas.hansson@arm.com * even modified) */ 14211600Sandreas.hansson@arm.com { SET6(IsRead, NeedsWritable, IsInvalidate, IsRequest, NeedsResponse, 14311600Sandreas.hansson@arm.com FromCache), 1444022Sstever@eecs.umich.edu ReadExResp, "ReadExReq" }, 14510885Sandreas.hansson@arm.com /* ReadExResp - Response matching a read exclusive, as we check 14610885Sandreas.hansson@arm.com * the need for exclusive also on responses */ 14711287Sandreas.hansson@arm.com { SET3(IsRead, IsResponse, HasData), 1484040Ssaidi@eecs.umich.edu InvalidCmd, "ReadExResp" }, 14910885Sandreas.hansson@arm.com /* ReadCleanReq - Read issued by a cache, always cache-line 15010885Sandreas.hansson@arm.com * aligned, and the response is guaranteed to not contain dirty data 15110885Sandreas.hansson@arm.com * (exclusive or shared).*/ 15211600Sandreas.hansson@arm.com { SET4(IsRead, IsRequest, NeedsResponse, FromCache), 15311600Sandreas.hansson@arm.com ReadResp, "ReadCleanReq" }, 15410885Sandreas.hansson@arm.com /* ReadSharedReq - Read issued by a cache, always cache-line 15510885Sandreas.hansson@arm.com * aligned, response is shared, possibly exclusive, owned or even 15610885Sandreas.hansson@arm.com * modified. */ 15711600Sandreas.hansson@arm.com { SET4(IsRead, IsRequest, NeedsResponse, FromCache), 15811600Sandreas.hansson@arm.com ReadResp, "ReadSharedReq" }, 1595507Sstever@gmail.com /* LoadLockedReq: note that we use plain ReadResp as response, so that 1605507Sstever@gmail.com * we can also use ReadRespWithInvalidate when needed */ 1616076Sgblack@eecs.umich.edu { SET4(IsRead, IsLlsc, IsRequest, NeedsResponse), 1625507Sstever@gmail.com ReadResp, "LoadLockedReq" }, 1634626Sstever@eecs.umich.edu /* StoreCondReq */ 16411284Sandreas.hansson@arm.com { SET6(IsWrite, NeedsWritable, IsLlsc, 1654626Sstever@eecs.umich.edu IsRequest, NeedsResponse, HasData), 1664626Sstever@eecs.umich.edu StoreCondResp, "StoreCondReq" }, 16710325Sgeoffrey.blake@arm.com /* StoreCondFailReq: generates failing StoreCondResp */ 16811284Sandreas.hansson@arm.com { SET6(IsWrite, NeedsWritable, IsLlsc, 1697669Ssteve.reinhardt@amd.com IsRequest, NeedsResponse, HasData), 1707669Ssteve.reinhardt@amd.com StoreCondResp, "StoreCondFailReq" }, 1714626Sstever@eecs.umich.edu /* StoreCondResp */ 17211287Sandreas.hansson@arm.com { SET3(IsWrite, IsLlsc, IsResponse), 1734626Sstever@eecs.umich.edu InvalidCmd, "StoreCondResp" }, 1744040Ssaidi@eecs.umich.edu /* SwapReq -- for Swap ldstub type operations */ 17511284Sandreas.hansson@arm.com { SET6(IsRead, IsWrite, NeedsWritable, IsRequest, HasData, NeedsResponse), 1764040Ssaidi@eecs.umich.edu SwapResp, "SwapReq" }, 1774040Ssaidi@eecs.umich.edu /* SwapResp -- for Swap ldstub type operations */ 17811287Sandreas.hansson@arm.com { SET4(IsRead, IsWrite, IsResponse, HasData), 1794870Sstever@eecs.umich.edu InvalidCmd, "SwapResp" }, 1805650Sgblack@eecs.umich.edu /* IntReq -- for interrupts */ 1815650Sgblack@eecs.umich.edu { SET4(IsWrite, IsRequest, NeedsResponse, HasData), 1826063Sgblack@eecs.umich.edu MessageResp, "MessageReq" }, 1835650Sgblack@eecs.umich.edu /* IntResp -- for interrupts */ 1846063Sgblack@eecs.umich.edu { SET2(IsWrite, IsResponse), InvalidCmd, "MessageResp" }, 18511256Santhony.gutierrez@amd.com /* MemFenceReq -- for synchronization requests */ 18611256Santhony.gutierrez@amd.com {SET2(IsRequest, NeedsResponse), MemFenceResp, "MemFenceReq"}, 18711256Santhony.gutierrez@amd.com /* MemFenceResp -- for synchronization responses */ 18811256Santhony.gutierrez@amd.com {SET1(IsResponse), InvalidCmd, "MemFenceResp"}, 18912347Snikos.nikoleris@arm.com /* Cache Clean Request -- Update with the latest data all existing 19012347Snikos.nikoleris@arm.com copies of the block down to the point indicated by the 19112347Snikos.nikoleris@arm.com request */ 19212347Snikos.nikoleris@arm.com { SET4(IsRequest, IsClean, NeedsResponse, FromCache), 19312347Snikos.nikoleris@arm.com CleanSharedResp, "CleanSharedReq" }, 19412347Snikos.nikoleris@arm.com /* Cache Clean Response - Indicates that all caches up to the 19512347Snikos.nikoleris@arm.com specified point of reference have a up-to-date copy of the 19612347Snikos.nikoleris@arm.com cache block or no copy at all */ 19712347Snikos.nikoleris@arm.com { SET2(IsResponse, IsClean), InvalidCmd, "CleanSharedResp" }, 19812347Snikos.nikoleris@arm.com /* Cache Clean and Invalidate Request -- Invalidate all existing 19912347Snikos.nikoleris@arm.com copies down to the point indicated by the request */ 20012347Snikos.nikoleris@arm.com { SET5(IsRequest, IsInvalidate, IsClean, NeedsResponse, FromCache), 20112347Snikos.nikoleris@arm.com CleanInvalidResp, "CleanInvalidReq" }, 20212347Snikos.nikoleris@arm.com /* Cache Clean and Invalidate Respose -- Indicates that no cache 20312347Snikos.nikoleris@arm.com above the specified point holds the block and that the block 20412347Snikos.nikoleris@arm.com was written to a memory below the specified point. */ 20512347Snikos.nikoleris@arm.com { SET3(IsResponse, IsInvalidate, IsClean), 20612347Snikos.nikoleris@arm.com InvalidCmd, "CleanInvalidResp" }, 2074870Sstever@eecs.umich.edu /* InvalidDestError -- packet dest field invalid */ 2084986Ssaidi@eecs.umich.edu { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" }, 2094870Sstever@eecs.umich.edu /* BadAddressError -- memory address invalid */ 2105314Sstever@gmail.com { SET2(IsResponse, IsError), InvalidCmd, "BadAddressError" }, 2118436SBrad.Beckmann@amd.com /* FunctionalReadError */ 2128436SBrad.Beckmann@amd.com { SET3(IsRead, IsResponse, IsError), InvalidCmd, "FunctionalReadError" }, 2138436SBrad.Beckmann@amd.com /* FunctionalWriteError */ 2148436SBrad.Beckmann@amd.com { SET3(IsWrite, IsResponse, IsError), InvalidCmd, "FunctionalWriteError" }, 2155314Sstever@gmail.com /* PrintReq */ 2168184Ssomayeh@cs.wisc.edu { SET2(IsRequest, IsPrint), InvalidCmd, "PrintReq" }, 2178184Ssomayeh@cs.wisc.edu /* Flush Request */ 21811284Sandreas.hansson@arm.com { SET3(IsRequest, IsFlush, NeedsWritable), InvalidCmd, "FlushReq" }, 2198716Snilay@cs.wisc.edu /* Invalidation Request */ 22011600Sandreas.hansson@arm.com { SET5(IsInvalidate, IsRequest, NeedsWritable, NeedsResponse, FromCache), 22110886Sandreas.hansson@arm.com InvalidateResp, "InvalidateReq" }, 22210886Sandreas.hansson@arm.com /* Invalidation Response */ 22311287Sandreas.hansson@arm.com { SET2(IsInvalidate, IsResponse), 22410886Sandreas.hansson@arm.com InvalidCmd, "InvalidateResp" } 2254022Sstever@eecs.umich.edu}; 2262592SN/A 2273607Srdreslin@umich.edubool 22812823Srmk35@cl.cam.ac.ukPacket::trySatisfyFunctional(Printable *obj, Addr addr, bool is_secure, int size, 22910570Sandreas.hansson@arm.com uint8_t *_data) 2302641Sstever@eecs.umich.edu{ 23112821Srmk35@cl.cam.ac.uk const Addr func_start = getAddr(); 23212821Srmk35@cl.cam.ac.uk const Addr func_end = getAddr() + getSize() - 1; 23312821Srmk35@cl.cam.ac.uk const Addr val_start = addr; 23412821Srmk35@cl.cam.ac.uk const Addr val_end = val_start + size - 1; 2353260Ssaidi@eecs.umich.edu 23610028SGiacomo.Gabrielli@arm.com if (is_secure != _isSecure || func_start > val_end || 23710028SGiacomo.Gabrielli@arm.com val_start > func_end) { 2384626Sstever@eecs.umich.edu // no intersection 2394626Sstever@eecs.umich.edu return false; 2404626Sstever@eecs.umich.edu } 2413260Ssaidi@eecs.umich.edu 2425314Sstever@gmail.com // check print first since it doesn't require data 2435314Sstever@gmail.com if (isPrint()) { 24410570Sandreas.hansson@arm.com assert(!_data); 24510376Sandreas.hansson@arm.com safe_cast<PrintReqState*>(senderState)->printObj(obj); 2465314Sstever@gmail.com return false; 2475314Sstever@gmail.com } 2485314Sstever@gmail.com 24910570Sandreas.hansson@arm.com // we allow the caller to pass NULL to signify the other packet 25010570Sandreas.hansson@arm.com // has no data 25110570Sandreas.hansson@arm.com if (!_data) { 2525314Sstever@gmail.com return false; 2535314Sstever@gmail.com } 2545314Sstever@gmail.com 25512821Srmk35@cl.cam.ac.uk const Addr val_offset = func_start > val_start ? 25612821Srmk35@cl.cam.ac.uk func_start - val_start : 0; 25712821Srmk35@cl.cam.ac.uk const Addr func_offset = func_start < val_start ? 25812821Srmk35@cl.cam.ac.uk val_start - func_start : 0; 25912821Srmk35@cl.cam.ac.uk const Addr overlap_size = std::min(val_end, func_end)+1 - 26012821Srmk35@cl.cam.ac.uk std::max(val_start, func_start); 2613260Ssaidi@eecs.umich.edu 2624626Sstever@eecs.umich.edu if (isRead()) { 26312822Srmk35@cl.cam.ac.uk std::memcpy(getPtr<uint8_t>() + func_offset, 26412821Srmk35@cl.cam.ac.uk _data + val_offset, 26512821Srmk35@cl.cam.ac.uk overlap_size); 2668668Sgeoffrey.blake@arm.com 26712821Srmk35@cl.cam.ac.uk // initialise the tracking of valid bytes if we have not 26812821Srmk35@cl.cam.ac.uk // used it already 26912821Srmk35@cl.cam.ac.uk if (bytesValid.empty()) 27012821Srmk35@cl.cam.ac.uk bytesValid.resize(getSize(), false); 2718668Sgeoffrey.blake@arm.com 27212821Srmk35@cl.cam.ac.uk // track if we are done filling the functional access 27312821Srmk35@cl.cam.ac.uk bool all_bytes_valid = true; 2748668Sgeoffrey.blake@arm.com 27512821Srmk35@cl.cam.ac.uk int i = 0; 27610723Sandreas.hansson@arm.com 27712821Srmk35@cl.cam.ac.uk // check up to func_offset 27812821Srmk35@cl.cam.ac.uk for (; all_bytes_valid && i < func_offset; ++i) 27912821Srmk35@cl.cam.ac.uk all_bytes_valid &= bytesValid[i]; 28010723Sandreas.hansson@arm.com 28112821Srmk35@cl.cam.ac.uk // update the valid bytes 28212821Srmk35@cl.cam.ac.uk for (i = func_offset; i < func_offset + overlap_size; ++i) 28312821Srmk35@cl.cam.ac.uk bytesValid[i] = true; 28410723Sandreas.hansson@arm.com 28512821Srmk35@cl.cam.ac.uk // check the bit after the update we just made 28612821Srmk35@cl.cam.ac.uk for (; all_bytes_valid && i < getSize(); ++i) 28712821Srmk35@cl.cam.ac.uk all_bytes_valid &= bytesValid[i]; 28810723Sandreas.hansson@arm.com 28912821Srmk35@cl.cam.ac.uk return all_bytes_valid; 2904626Sstever@eecs.umich.edu } else if (isWrite()) { 29112822Srmk35@cl.cam.ac.uk std::memcpy(_data + val_offset, 29212821Srmk35@cl.cam.ac.uk getConstPtr<uint8_t>() + func_offset, 29312821Srmk35@cl.cam.ac.uk overlap_size); 2945314Sstever@gmail.com } else { 2954626Sstever@eecs.umich.edu panic("Don't know how to handle command %s\n", cmdString()); 2965314Sstever@gmail.com } 2975314Sstever@gmail.com 2985314Sstever@gmail.com // keep going with request by default 2995314Sstever@gmail.com return false; 3002641Sstever@eecs.umich.edu} 3013260Ssaidi@eecs.umich.edu 3025314Sstever@gmail.comvoid 3039542Sandreas.hansson@arm.comPacket::pushSenderState(Packet::SenderState *sender_state) 3049542Sandreas.hansson@arm.com{ 3059542Sandreas.hansson@arm.com assert(sender_state != NULL); 3069542Sandreas.hansson@arm.com sender_state->predecessor = senderState; 3079542Sandreas.hansson@arm.com senderState = sender_state; 3089542Sandreas.hansson@arm.com} 3099542Sandreas.hansson@arm.com 3109542Sandreas.hansson@arm.comPacket::SenderState * 3119542Sandreas.hansson@arm.comPacket::popSenderState() 3129542Sandreas.hansson@arm.com{ 3139542Sandreas.hansson@arm.com assert(senderState != NULL); 3149542Sandreas.hansson@arm.com SenderState *sender_state = senderState; 3159542Sandreas.hansson@arm.com senderState = sender_state->predecessor; 3169542Sandreas.hansson@arm.com sender_state->predecessor = NULL; 3179542Sandreas.hansson@arm.com return sender_state; 3189542Sandreas.hansson@arm.com} 3199542Sandreas.hansson@arm.com 32012652Sandreas.sandberg@arm.comuint64_t 32112652Sandreas.sandberg@arm.comPacket::getUintX(ByteOrder endian) const 32212652Sandreas.sandberg@arm.com{ 32312652Sandreas.sandberg@arm.com switch(getSize()) { 32412652Sandreas.sandberg@arm.com case 1: 32512652Sandreas.sandberg@arm.com return (uint64_t)get<uint8_t>(endian); 32612652Sandreas.sandberg@arm.com case 2: 32712652Sandreas.sandberg@arm.com return (uint64_t)get<uint16_t>(endian); 32812652Sandreas.sandberg@arm.com case 4: 32912652Sandreas.sandberg@arm.com return (uint64_t)get<uint32_t>(endian); 33012652Sandreas.sandberg@arm.com case 8: 33112652Sandreas.sandberg@arm.com return (uint64_t)get<uint64_t>(endian); 33212652Sandreas.sandberg@arm.com default: 33312652Sandreas.sandberg@arm.com panic("%i isn't a supported word size.\n", getSize()); 33412652Sandreas.sandberg@arm.com } 33512652Sandreas.sandberg@arm.com} 33612652Sandreas.sandberg@arm.com 33712652Sandreas.sandberg@arm.comvoid 33812652Sandreas.sandberg@arm.comPacket::setUintX(uint64_t w, ByteOrder endian) 33912652Sandreas.sandberg@arm.com{ 34012652Sandreas.sandberg@arm.com switch(getSize()) { 34112652Sandreas.sandberg@arm.com case 1: 34212652Sandreas.sandberg@arm.com set<uint8_t>((uint8_t)w, endian); 34312652Sandreas.sandberg@arm.com break; 34412652Sandreas.sandberg@arm.com case 2: 34512652Sandreas.sandberg@arm.com set<uint16_t>((uint16_t)w, endian); 34612652Sandreas.sandberg@arm.com break; 34712652Sandreas.sandberg@arm.com case 4: 34812652Sandreas.sandberg@arm.com set<uint32_t>((uint32_t)w, endian); 34912652Sandreas.sandberg@arm.com break; 35012652Sandreas.sandberg@arm.com case 8: 35112652Sandreas.sandberg@arm.com set<uint64_t>((uint64_t)w, endian); 35212652Sandreas.sandberg@arm.com break; 35312652Sandreas.sandberg@arm.com default: 35412652Sandreas.sandberg@arm.com panic("%i isn't a supported word size.\n", getSize()); 35512652Sandreas.sandberg@arm.com } 35612652Sandreas.sandberg@arm.com 35712652Sandreas.sandberg@arm.com} 35812652Sandreas.sandberg@arm.com 3599542Sandreas.hansson@arm.comvoid 36012822Srmk35@cl.cam.ac.ukPacket::print(std::ostream &o, const int verbosity, 36112822Srmk35@cl.cam.ac.uk const std::string &prefix) const 3623260Ssaidi@eecs.umich.edu{ 36312346Snikos.nikoleris@arm.com ccprintf(o, "%s%s [%x:%x]%s%s%s%s%s%s", prefix, cmdString(), 36411744Snikos.nikoleris@arm.com getAddr(), getAddr() + getSize() - 1, 36511744Snikos.nikoleris@arm.com req->isSecure() ? " (s)" : "", 36611744Snikos.nikoleris@arm.com req->isInstFetch() ? " IF" : "", 36711744Snikos.nikoleris@arm.com req->isUncacheable() ? " UC" : "", 36812346Snikos.nikoleris@arm.com isExpressSnoop() ? " ES" : "", 36912346Snikos.nikoleris@arm.com req->isToPOC() ? " PoC" : "", 37012346Snikos.nikoleris@arm.com req->isToPOU() ? " PoU" : ""); 3713260Ssaidi@eecs.umich.edu} 3723260Ssaidi@eecs.umich.edu 3739663Suri.wiener@arm.comstd::string 3749663Suri.wiener@arm.comPacket::print() const { 37512822Srmk35@cl.cam.ac.uk std::ostringstream str; 3769663Suri.wiener@arm.com print(str); 3779663Suri.wiener@arm.com return str.str(); 3789663Suri.wiener@arm.com} 3799663Suri.wiener@arm.com 38012822Srmk35@cl.cam.ac.ukPacket::PrintReqState::PrintReqState(std::ostream &_os, int _verbosity) 38112822Srmk35@cl.cam.ac.uk : curPrefixPtr(new std::string("")), os(_os), verbosity(_verbosity) 3825314Sstever@gmail.com{ 3835314Sstever@gmail.com labelStack.push_back(LabelStackEntry("", curPrefixPtr)); 3845314Sstever@gmail.com} 3855314Sstever@gmail.com 3865314Sstever@gmail.comPacket::PrintReqState::~PrintReqState() 3875314Sstever@gmail.com{ 3885314Sstever@gmail.com labelStack.pop_back(); 3895314Sstever@gmail.com assert(labelStack.empty()); 3905314Sstever@gmail.com delete curPrefixPtr; 3915314Sstever@gmail.com} 3925314Sstever@gmail.com 3935314Sstever@gmail.comPacket::PrintReqState:: 39412822Srmk35@cl.cam.ac.ukLabelStackEntry::LabelStackEntry(const std::string &_label, 39512822Srmk35@cl.cam.ac.uk std::string *_prefix) 3965314Sstever@gmail.com : label(_label), prefix(_prefix), labelPrinted(false) 3975314Sstever@gmail.com{ 3985314Sstever@gmail.com} 3995314Sstever@gmail.com 4005314Sstever@gmail.comvoid 40112822Srmk35@cl.cam.ac.ukPacket::PrintReqState::pushLabel(const std::string &lbl, 40212822Srmk35@cl.cam.ac.uk const std::string &prefix) 4035314Sstever@gmail.com{ 4045314Sstever@gmail.com labelStack.push_back(LabelStackEntry(lbl, curPrefixPtr)); 40512822Srmk35@cl.cam.ac.uk curPrefixPtr = new std::string(*curPrefixPtr); 4065314Sstever@gmail.com *curPrefixPtr += prefix; 4075314Sstever@gmail.com} 4085314Sstever@gmail.com 4095314Sstever@gmail.comvoid 4105314Sstever@gmail.comPacket::PrintReqState::popLabel() 4115314Sstever@gmail.com{ 4125314Sstever@gmail.com delete curPrefixPtr; 4135314Sstever@gmail.com curPrefixPtr = labelStack.back().prefix; 4145314Sstever@gmail.com labelStack.pop_back(); 4155314Sstever@gmail.com assert(!labelStack.empty()); 4165314Sstever@gmail.com} 4175314Sstever@gmail.com 4185314Sstever@gmail.comvoid 4195314Sstever@gmail.comPacket::PrintReqState::printLabels() 4205314Sstever@gmail.com{ 4215314Sstever@gmail.com if (!labelStack.back().labelPrinted) { 4225314Sstever@gmail.com LabelStack::iterator i = labelStack.begin(); 4235314Sstever@gmail.com LabelStack::iterator end = labelStack.end(); 4245314Sstever@gmail.com while (i != end) { 4255314Sstever@gmail.com if (!i->labelPrinted) { 4265314Sstever@gmail.com ccprintf(os, "%s%s\n", *(i->prefix), i->label); 4275314Sstever@gmail.com i->labelPrinted = true; 4285314Sstever@gmail.com } 4295314Sstever@gmail.com i++; 4305314Sstever@gmail.com } 4315314Sstever@gmail.com } 4325314Sstever@gmail.com} 4335314Sstever@gmail.com 4345314Sstever@gmail.com 4355314Sstever@gmail.comvoid 4365314Sstever@gmail.comPacket::PrintReqState::printObj(Printable *obj) 4375314Sstever@gmail.com{ 4385314Sstever@gmail.com printLabels(); 4395314Sstever@gmail.com obj->print(os, verbosity, curPrefix()); 4405314Sstever@gmail.com} 441