packet.cc revision 12652
16019Shines@cs.fsu.edu/* 29383SAli.Saidi@ARM.com * Copyright (c) 2011-2018 ARM Limited 39383SAli.Saidi@ARM.com * All rights reserved 49383SAli.Saidi@ARM.com * 59383SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 69383SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 79383SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 89383SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 99383SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 109383SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 119383SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 129383SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139383SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2006 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 418209SAli.Saidi@ARM.com * Authors: Ali Saidi 428209SAli.Saidi@ARM.com * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu/** 466019Shines@cs.fsu.edu * @file 476019Shines@cs.fsu.edu * Definition of the Packet Class, a packet is a transaction occuring 486019Shines@cs.fsu.edu * between a single level of the memory heirarchy (ie L1->L2). 496019Shines@cs.fsu.edu */ 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.edu#include "mem/packet.hh" 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edu#include <cstring> 546019Shines@cs.fsu.edu#include <iostream> 558209SAli.Saidi@ARM.com 569383SAli.Saidi@ARM.com#include "base/cprintf.hh" 576019Shines@cs.fsu.edu#include "base/logging.hh" 586019Shines@cs.fsu.edu#include "base/trace.hh" 596019Shines@cs.fsu.edu#include "mem/packet_access.hh" 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.eduusing namespace std; 626019Shines@cs.fsu.edu 639383SAli.Saidi@ARM.com// The one downside to bitsets is that static initializers can get ugly. 649383SAli.Saidi@ARM.com#define SET1(a1) (1 << (a1)) 659383SAli.Saidi@ARM.com#define SET2(a1, a2) (SET1(a1) | SET1(a2)) 669383SAli.Saidi@ARM.com#define SET3(a1, a2, a3) (SET2(a1, a2) | SET1(a3)) 679383SAli.Saidi@ARM.com#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4)) 689383SAli.Saidi@ARM.com#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5)) 699383SAli.Saidi@ARM.com#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6)) 709383SAli.Saidi@ARM.com#define SET7(a1, a2, a3, a4, a5, a6, a7) (SET6(a1, a2, a3, a4, a5, a6) | \ 719383SAli.Saidi@ARM.com SET1(a7)) 729383SAli.Saidi@ARM.com 739383SAli.Saidi@ARM.comconst MemCmd::CommandInfo 749383SAli.Saidi@ARM.comMemCmd::commandInfo[] = 759383SAli.Saidi@ARM.com{ 769383SAli.Saidi@ARM.com /* InvalidCmd */ 779383SAli.Saidi@ARM.com { 0, InvalidCmd, "InvalidCmd" }, 789383SAli.Saidi@ARM.com /* ReadReq - Read issued by a non-caching agent such as a CPU or 796019Shines@cs.fsu.edu * device, with no restrictions on alignment. */ 806019Shines@cs.fsu.edu { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" }, 818209SAli.Saidi@ARM.com /* ReadResp */ 828209SAli.Saidi@ARM.com { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" }, 836019Shines@cs.fsu.edu /* ReadRespWithInvalidate */ 846019Shines@cs.fsu.edu { SET4(IsRead, IsResponse, HasData, IsInvalidate), 856019Shines@cs.fsu.edu InvalidCmd, "ReadRespWithInvalidate" }, 866019Shines@cs.fsu.edu /* WriteReq */ 876019Shines@cs.fsu.edu { SET5(IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData), 886019Shines@cs.fsu.edu WriteResp, "WriteReq" }, 896019Shines@cs.fsu.edu /* WriteResp */ 908209SAli.Saidi@ARM.com { SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" }, 918209SAli.Saidi@ARM.com /* WritebackDirty */ 928209SAli.Saidi@ARM.com { SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache), 938209SAli.Saidi@ARM.com InvalidCmd, "WritebackDirty" }, 948209SAli.Saidi@ARM.com /* WritebackClean - This allows the upstream cache to writeback a 958209SAli.Saidi@ARM.com * line to the downstream cache without it being considered 968209SAli.Saidi@ARM.com * dirty. */ 978209SAli.Saidi@ARM.com { SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache), 988209SAli.Saidi@ARM.com InvalidCmd, "WritebackClean" }, 998209SAli.Saidi@ARM.com /* WriteClean - This allows a cache to write a dirty block to a memory 1008209SAli.Saidi@ARM.com below without evicting its copy. */ 1018209SAli.Saidi@ARM.com { SET4(IsWrite, IsRequest, HasData, FromCache), InvalidCmd, "WriteClean" }, 1028209SAli.Saidi@ARM.com /* CleanEvict */ 1038209SAli.Saidi@ARM.com { SET3(IsRequest, IsEviction, FromCache), InvalidCmd, "CleanEvict" }, 1048209SAli.Saidi@ARM.com /* SoftPFReq */ 1058209SAli.Saidi@ARM.com { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse), 1068209SAli.Saidi@ARM.com SoftPFResp, "SoftPFReq" }, 1078209SAli.Saidi@ARM.com /* HardPFReq */ 1088209SAli.Saidi@ARM.com { SET5(IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache), 1098209SAli.Saidi@ARM.com HardPFResp, "HardPFReq" }, 1108209SAli.Saidi@ARM.com /* SoftPFResp */ 1118209SAli.Saidi@ARM.com { SET4(IsRead, IsResponse, IsSWPrefetch, HasData), 1128209SAli.Saidi@ARM.com InvalidCmd, "SoftPFResp" }, 1138209SAli.Saidi@ARM.com /* HardPFResp */ 1148209SAli.Saidi@ARM.com { SET4(IsRead, IsResponse, IsHWPrefetch, HasData), 1158209SAli.Saidi@ARM.com InvalidCmd, "HardPFResp" }, 1168209SAli.Saidi@ARM.com /* WriteLineReq */ 1178209SAli.Saidi@ARM.com { SET5(IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData), 1186019Shines@cs.fsu.edu WriteResp, "WriteLineReq" }, 1196019Shines@cs.fsu.edu /* UpgradeReq */ 1206019Shines@cs.fsu.edu { SET6(IsInvalidate, NeedsWritable, IsUpgrade, IsRequest, NeedsResponse, 1216019Shines@cs.fsu.edu FromCache), 1226019Shines@cs.fsu.edu UpgradeResp, "UpgradeReq" }, 1236019Shines@cs.fsu.edu /* SCUpgradeReq: response could be UpgradeResp or UpgradeFailResp */ 1246019Shines@cs.fsu.edu { SET7(IsInvalidate, NeedsWritable, IsUpgrade, IsLlsc, 125 IsRequest, NeedsResponse, FromCache), 126 UpgradeResp, "SCUpgradeReq" }, 127 /* UpgradeResp */ 128 { SET2(IsUpgrade, IsResponse), 129 InvalidCmd, "UpgradeResp" }, 130 /* SCUpgradeFailReq: generates UpgradeFailResp but still gets the data */ 131 { SET7(IsRead, NeedsWritable, IsInvalidate, 132 IsLlsc, IsRequest, NeedsResponse, FromCache), 133 UpgradeFailResp, "SCUpgradeFailReq" }, 134 /* UpgradeFailResp - Behaves like a ReadExReq, but notifies an SC 135 * that it has failed, acquires line as Dirty*/ 136 { SET3(IsRead, IsResponse, HasData), 137 InvalidCmd, "UpgradeFailResp" }, 138 /* ReadExReq - Read issues by a cache, always cache-line aligned, 139 * and the response is guaranteed to be writeable (exclusive or 140 * even modified) */ 141 { SET6(IsRead, NeedsWritable, IsInvalidate, IsRequest, NeedsResponse, 142 FromCache), 143 ReadExResp, "ReadExReq" }, 144 /* ReadExResp - Response matching a read exclusive, as we check 145 * the need for exclusive also on responses */ 146 { SET3(IsRead, IsResponse, HasData), 147 InvalidCmd, "ReadExResp" }, 148 /* ReadCleanReq - Read issued by a cache, always cache-line 149 * aligned, and the response is guaranteed to not contain dirty data 150 * (exclusive or shared).*/ 151 { SET4(IsRead, IsRequest, NeedsResponse, FromCache), 152 ReadResp, "ReadCleanReq" }, 153 /* ReadSharedReq - Read issued by a cache, always cache-line 154 * aligned, response is shared, possibly exclusive, owned or even 155 * modified. */ 156 { SET4(IsRead, IsRequest, NeedsResponse, FromCache), 157 ReadResp, "ReadSharedReq" }, 158 /* LoadLockedReq: note that we use plain ReadResp as response, so that 159 * we can also use ReadRespWithInvalidate when needed */ 160 { SET4(IsRead, IsLlsc, IsRequest, NeedsResponse), 161 ReadResp, "LoadLockedReq" }, 162 /* StoreCondReq */ 163 { SET6(IsWrite, NeedsWritable, IsLlsc, 164 IsRequest, NeedsResponse, HasData), 165 StoreCondResp, "StoreCondReq" }, 166 /* StoreCondFailReq: generates failing StoreCondResp */ 167 { SET6(IsWrite, NeedsWritable, IsLlsc, 168 IsRequest, NeedsResponse, HasData), 169 StoreCondResp, "StoreCondFailReq" }, 170 /* StoreCondResp */ 171 { SET3(IsWrite, IsLlsc, IsResponse), 172 InvalidCmd, "StoreCondResp" }, 173 /* SwapReq -- for Swap ldstub type operations */ 174 { SET6(IsRead, IsWrite, NeedsWritable, IsRequest, HasData, NeedsResponse), 175 SwapResp, "SwapReq" }, 176 /* SwapResp -- for Swap ldstub type operations */ 177 { SET4(IsRead, IsWrite, IsResponse, HasData), 178 InvalidCmd, "SwapResp" }, 179 /* IntReq -- for interrupts */ 180 { SET4(IsWrite, IsRequest, NeedsResponse, HasData), 181 MessageResp, "MessageReq" }, 182 /* IntResp -- for interrupts */ 183 { SET2(IsWrite, IsResponse), InvalidCmd, "MessageResp" }, 184 /* MemFenceReq -- for synchronization requests */ 185 {SET2(IsRequest, NeedsResponse), MemFenceResp, "MemFenceReq"}, 186 /* MemFenceResp -- for synchronization responses */ 187 {SET1(IsResponse), InvalidCmd, "MemFenceResp"}, 188 /* Cache Clean Request -- Update with the latest data all existing 189 copies of the block down to the point indicated by the 190 request */ 191 { SET4(IsRequest, IsClean, NeedsResponse, FromCache), 192 CleanSharedResp, "CleanSharedReq" }, 193 /* Cache Clean Response - Indicates that all caches up to the 194 specified point of reference have a up-to-date copy of the 195 cache block or no copy at all */ 196 { SET2(IsResponse, IsClean), InvalidCmd, "CleanSharedResp" }, 197 /* Cache Clean and Invalidate Request -- Invalidate all existing 198 copies down to the point indicated by the request */ 199 { SET5(IsRequest, IsInvalidate, IsClean, NeedsResponse, FromCache), 200 CleanInvalidResp, "CleanInvalidReq" }, 201 /* Cache Clean and Invalidate Respose -- Indicates that no cache 202 above the specified point holds the block and that the block 203 was written to a memory below the specified point. */ 204 { SET3(IsResponse, IsInvalidate, IsClean), 205 InvalidCmd, "CleanInvalidResp" }, 206 /* InvalidDestError -- packet dest field invalid */ 207 { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" }, 208 /* BadAddressError -- memory address invalid */ 209 { SET2(IsResponse, IsError), InvalidCmd, "BadAddressError" }, 210 /* FunctionalReadError */ 211 { SET3(IsRead, IsResponse, IsError), InvalidCmd, "FunctionalReadError" }, 212 /* FunctionalWriteError */ 213 { SET3(IsWrite, IsResponse, IsError), InvalidCmd, "FunctionalWriteError" }, 214 /* PrintReq */ 215 { SET2(IsRequest, IsPrint), InvalidCmd, "PrintReq" }, 216 /* Flush Request */ 217 { SET3(IsRequest, IsFlush, NeedsWritable), InvalidCmd, "FlushReq" }, 218 /* Invalidation Request */ 219 { SET5(IsInvalidate, IsRequest, NeedsWritable, NeedsResponse, FromCache), 220 InvalidateResp, "InvalidateReq" }, 221 /* Invalidation Response */ 222 { SET2(IsInvalidate, IsResponse), 223 InvalidCmd, "InvalidateResp" } 224}; 225 226bool 227Packet::checkFunctional(Printable *obj, Addr addr, bool is_secure, int size, 228 uint8_t *_data) 229{ 230 Addr func_start = getAddr(); 231 Addr func_end = getAddr() + getSize() - 1; 232 Addr val_start = addr; 233 Addr val_end = val_start + size - 1; 234 235 if (is_secure != _isSecure || func_start > val_end || 236 val_start > func_end) { 237 // no intersection 238 return false; 239 } 240 241 // check print first since it doesn't require data 242 if (isPrint()) { 243 assert(!_data); 244 safe_cast<PrintReqState*>(senderState)->printObj(obj); 245 return false; 246 } 247 248 // we allow the caller to pass NULL to signify the other packet 249 // has no data 250 if (!_data) { 251 return false; 252 } 253 254 // offset of functional request into supplied value (could be 255 // negative if partial overlap) 256 int offset = func_start - val_start; 257 258 if (isRead()) { 259 if (func_start >= val_start && func_end <= val_end) { 260 memcpy(getPtr<uint8_t>(), _data + offset, getSize()); 261 if (bytesValid.empty()) 262 bytesValid.resize(getSize(), true); 263 // complete overlap, and as the current packet is a read 264 // we are done 265 return true; 266 } else { 267 // Offsets and sizes to copy in case of partial overlap 268 int func_offset; 269 int val_offset; 270 int overlap_size; 271 272 // calculate offsets and copy sizes for the two byte arrays 273 if (val_start < func_start && val_end <= func_end) { 274 // the one we are checking against starts before and 275 // ends before or the same 276 val_offset = func_start - val_start; 277 func_offset = 0; 278 overlap_size = val_end - func_start; 279 } else if (val_start >= func_start && val_end > func_end) { 280 // the one we are checking against starts after or the 281 // same, and ends after 282 val_offset = 0; 283 func_offset = val_start - func_start; 284 overlap_size = func_end - val_start; 285 } else if (val_start >= func_start && val_end <= func_end) { 286 // the one we are checking against is completely 287 // subsumed in the current packet, possibly starting 288 // and ending at the same address 289 val_offset = 0; 290 func_offset = val_start - func_start; 291 overlap_size = size; 292 } else if (val_start < func_start && val_end > func_end) { 293 // the current packet is completely subsumed in the 294 // one we are checking against 295 val_offset = func_start - val_start; 296 func_offset = 0; 297 overlap_size = func_end - func_start; 298 } else { 299 panic("Missed a case for checkFunctional with " 300 " %s 0x%x size %d, against 0x%x size %d\n", 301 cmdString(), getAddr(), getSize(), addr, size); 302 } 303 304 // copy partial data into the packet's data array 305 uint8_t *dest = getPtr<uint8_t>() + func_offset; 306 uint8_t *src = _data + val_offset; 307 memcpy(dest, src, overlap_size); 308 309 // initialise the tracking of valid bytes if we have not 310 // used it already 311 if (bytesValid.empty()) 312 bytesValid.resize(getSize(), false); 313 314 // track if we are done filling the functional access 315 bool all_bytes_valid = true; 316 317 int i = 0; 318 319 // check up to func_offset 320 for (; all_bytes_valid && i < func_offset; ++i) 321 all_bytes_valid &= bytesValid[i]; 322 323 // update the valid bytes 324 for (i = func_offset; i < func_offset + overlap_size; ++i) 325 bytesValid[i] = true; 326 327 // check the bit after the update we just made 328 for (; all_bytes_valid && i < getSize(); ++i) 329 all_bytes_valid &= bytesValid[i]; 330 331 return all_bytes_valid; 332 } 333 } else if (isWrite()) { 334 if (offset >= 0) { 335 memcpy(_data + offset, getConstPtr<uint8_t>(), 336 (min(func_end, val_end) - func_start) + 1); 337 } else { 338 // val_start > func_start 339 memcpy(_data, getConstPtr<uint8_t>() - offset, 340 (min(func_end, val_end) - val_start) + 1); 341 } 342 } else { 343 panic("Don't know how to handle command %s\n", cmdString()); 344 } 345 346 // keep going with request by default 347 return false; 348} 349 350void 351Packet::pushSenderState(Packet::SenderState *sender_state) 352{ 353 assert(sender_state != NULL); 354 sender_state->predecessor = senderState; 355 senderState = sender_state; 356} 357 358Packet::SenderState * 359Packet::popSenderState() 360{ 361 assert(senderState != NULL); 362 SenderState *sender_state = senderState; 363 senderState = sender_state->predecessor; 364 sender_state->predecessor = NULL; 365 return sender_state; 366} 367 368uint64_t 369Packet::getUintX(ByteOrder endian) const 370{ 371 switch(getSize()) { 372 case 1: 373 return (uint64_t)get<uint8_t>(endian); 374 case 2: 375 return (uint64_t)get<uint16_t>(endian); 376 case 4: 377 return (uint64_t)get<uint32_t>(endian); 378 case 8: 379 return (uint64_t)get<uint64_t>(endian); 380 default: 381 panic("%i isn't a supported word size.\n", getSize()); 382 } 383} 384 385void 386Packet::setUintX(uint64_t w, ByteOrder endian) 387{ 388 switch(getSize()) { 389 case 1: 390 set<uint8_t>((uint8_t)w, endian); 391 break; 392 case 2: 393 set<uint16_t>((uint16_t)w, endian); 394 break; 395 case 4: 396 set<uint32_t>((uint32_t)w, endian); 397 break; 398 case 8: 399 set<uint64_t>((uint64_t)w, endian); 400 break; 401 default: 402 panic("%i isn't a supported word size.\n", getSize()); 403 } 404 405} 406 407void 408Packet::print(ostream &o, const int verbosity, const string &prefix) const 409{ 410 ccprintf(o, "%s%s [%x:%x]%s%s%s%s%s%s", prefix, cmdString(), 411 getAddr(), getAddr() + getSize() - 1, 412 req->isSecure() ? " (s)" : "", 413 req->isInstFetch() ? " IF" : "", 414 req->isUncacheable() ? " UC" : "", 415 isExpressSnoop() ? " ES" : "", 416 req->isToPOC() ? " PoC" : "", 417 req->isToPOU() ? " PoU" : ""); 418} 419 420std::string 421Packet::print() const { 422 ostringstream str; 423 print(str); 424 return str.str(); 425} 426 427Packet::PrintReqState::PrintReqState(ostream &_os, int _verbosity) 428 : curPrefixPtr(new string("")), os(_os), verbosity(_verbosity) 429{ 430 labelStack.push_back(LabelStackEntry("", curPrefixPtr)); 431} 432 433Packet::PrintReqState::~PrintReqState() 434{ 435 labelStack.pop_back(); 436 assert(labelStack.empty()); 437 delete curPrefixPtr; 438} 439 440Packet::PrintReqState:: 441LabelStackEntry::LabelStackEntry(const string &_label, string *_prefix) 442 : label(_label), prefix(_prefix), labelPrinted(false) 443{ 444} 445 446void 447Packet::PrintReqState::pushLabel(const string &lbl, const string &prefix) 448{ 449 labelStack.push_back(LabelStackEntry(lbl, curPrefixPtr)); 450 curPrefixPtr = new string(*curPrefixPtr); 451 *curPrefixPtr += prefix; 452} 453 454void 455Packet::PrintReqState::popLabel() 456{ 457 delete curPrefixPtr; 458 curPrefixPtr = labelStack.back().prefix; 459 labelStack.pop_back(); 460 assert(!labelStack.empty()); 461} 462 463void 464Packet::PrintReqState::printLabels() 465{ 466 if (!labelStack.back().labelPrinted) { 467 LabelStack::iterator i = labelStack.begin(); 468 LabelStack::iterator end = labelStack.end(); 469 while (i != end) { 470 if (!i->labelPrinted) { 471 ccprintf(os, "%s%s\n", *(i->prefix), i->label); 472 i->labelPrinted = true; 473 } 474 i++; 475 } 476 } 477} 478 479 480void 481Packet::PrintReqState::printObj(Printable *obj) 482{ 483 printLabels(); 484 obj->print(os, verbosity, curPrefix()); 485} 486