noncoherent_xbar.hh revision 9712 
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Ali Saidi
42 *          Andreas Hansson
43 *          William Wang
44 */
45
46/**
47 * @file
48 * Declaration of a non-coherent bus.
49 */
50
51#ifndef __MEM_NONCOHERENT_BUS_HH__
52#define __MEM_NONCOHERENT_BUS_HH__
53
54#include "mem/bus.hh"
55#include "params/NoncoherentBus.hh"
56
57/**
58 * A non-coherent bus connects a number of non-snooping masters and
59 * slaves, and routes the request and response packets based on the
60 * address. The request packets issued by the master connected to a
61 * non-coherent bus could still snoop in caches attached to a coherent
62 * bus, as is the case with the I/O bus and memory bus in most system
63 * configurations. No snoops will, however, reach any master on the
64 * non-coherent bus itself.
65 *
66 * The non-coherent bus can be used as a template for modelling PCI,
67 * PCIe, and non-coherent AMBA and OCP buses, and is typically used
68 * for the I/O buses.
69 */
70class NoncoherentBus : public BaseBus
71{
72
73  protected:
74
75    /**
76     * Declare the two layers of this bus, one for requests and one
77     * for responses.
78     */
79    Layer<SlavePort> reqLayer;
80    Layer<MasterPort> respLayer;
81
82    /**
83     * Declaration of the non-coherent bus slave port type, one will
84     * be instantiated for each of the master ports connecting to the
85     * bus.
86     */
87    class NoncoherentBusSlavePort : public SlavePort
88    {
89      private:
90
91        /** A reference to the bus to which this port belongs. */
92        NoncoherentBus &bus;
93
94      public:
95
96        NoncoherentBusSlavePort(const std::string &_name,
97                                NoncoherentBus &_bus, PortID _id)
98            : SlavePort(_name, &_bus, _id), bus(_bus)
99        { }
100
101      protected:
102
103        /**
104         * When receiving a timing request, pass it to the bus.
105         */
106        virtual bool recvTimingReq(PacketPtr pkt)
107        { return bus.recvTimingReq(pkt, id); }
108
109        /**
110         * When receiving an atomic request, pass it to the bus.
111         */
112        virtual Tick recvAtomic(PacketPtr pkt)
113        { return bus.recvAtomic(pkt, id); }
114
115        /**
116         * When receiving a functional request, pass it to the bus.
117         */
118        virtual void recvFunctional(PacketPtr pkt)
119        { bus.recvFunctional(pkt, id); }
120
121        /**
122         * When receiving a retry, pass it to the bus.
123         */
124        virtual void recvRetry()
125        { panic("Bus slave ports always succeed and should never retry.\n"); }
126
127        /**
128         * Return the union of all adress ranges seen by this bus.
129         */
130        virtual AddrRangeList getAddrRanges() const
131        { return bus.getAddrRanges(); }
132
133        /**
134         * Get the maximum block size as seen by the bus.
135         */
136        virtual unsigned deviceBlockSize() const
137        { return bus.deviceBlockSize(); }
138
139    };
140
141    /**
142     * Declaration of the bus master port type, one will be
143     * instantiated for each of the slave ports connecting to the
144     * bus.
145     */
146    class NoncoherentBusMasterPort : public MasterPort
147    {
148      private:
149
150        /** A reference to the bus to which this port belongs. */
151        NoncoherentBus &bus;
152
153      public:
154
155        NoncoherentBusMasterPort(const std::string &_name,
156                                 NoncoherentBus &_bus, PortID _id)
157            : MasterPort(_name, &_bus, _id), bus(_bus)
158        { }
159
160      protected:
161
162        /**
163         * When receiving a timing response, pass it to the bus.
164         */
165        virtual bool recvTimingResp(PacketPtr pkt)
166        { return bus.recvTimingResp(pkt, id); }
167
168        /** When reciving a range change from the peer port (at id),
169            pass it to the bus. */
170        virtual void recvRangeChange()
171        { bus.recvRangeChange(id); }
172
173        /** When reciving a retry from the peer port (at id),
174            pass it to the bus. */
175        virtual void recvRetry()
176        { bus.recvRetry(id); }
177
178        /**
179         * Get the maximum block size as seen by the bus.
180         */
181        virtual unsigned deviceBlockSize() const
182        { return bus.deviceBlockSize(); }
183
184    };
185
186    /** Function called by the port when the bus is recieving a Timing
187      request packet.*/
188    virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
189
190    /** Function called by the port when the bus is recieving a Timing
191      response packet.*/
192    virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
193
194    /** Timing function called by port when it is once again able to process
195     * requests. */
196    void recvRetry(PortID master_port_id);
197
198    /** Function called by the port when the bus is recieving a Atomic
199      transaction.*/
200    Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
201
202    /** Function called by the port when the bus is recieving a Functional
203        transaction.*/
204    void recvFunctional(PacketPtr pkt, PortID slave_port_id);
205
206  public:
207
208    NoncoherentBus(const NoncoherentBusParams *p);
209
210    unsigned int drain(DrainManager *dm);
211
212    /**
213     * stats
214     */
215    virtual void regStats();
216    Stats::Scalar dataThroughBus;
217};
218
219#endif //__MEM_NONCOHERENT_BUS_HH__
220