noncoherent_xbar.hh revision 9036
12810SN/A/* 28856Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Ron Dreslinski 414458SN/A * Ali Saidi 424458SN/A * Andreas Hansson 432810SN/A * William Wang 442810SN/A */ 452810SN/A 462810SN/A/** 472810SN/A * @file 482810SN/A * Declaration of a non-coherent bus. 492810SN/A */ 502810SN/A 512810SN/A#ifndef __MEM_NONCOHERENT_BUS_HH__ 522810SN/A#define __MEM_NONCOHERENT_BUS_HH__ 537676Snate@binkert.org 547676Snate@binkert.org#include "mem/bus.hh" 557676Snate@binkert.org#include "params/NoncoherentBus.hh" 562810SN/A 572810SN/A/** 582825SN/A * A non-coherent bus connects a number of non-snooping masters and 592810SN/A * slaves, and routes the request and response packets based on the 602810SN/A * address. The request packets issued by the master connected to a 616215Snate@binkert.org * non-coherent bus could still snoop in caches attached to a coherent 628232Snate@binkert.org * bus, as is the case with the I/O bus and memory bus in most system 638232Snate@binkert.org * configurations. No snoops will, however, reach any master on the 645338Sstever@gmail.com * non-coherent bus itself. 652810SN/A * 662810SN/A * The non-coherent bus can be used as a template for modelling PCI, 678914Sandreas.hansson@arm.com * PCIe, and non-coherent AMBA and OCP buses, and is typically used 688229Snate@binkert.org * for the I/O buses. 695034SN/A */ 702811SN/Aclass NoncoherentBus : public BaseBus 718786Sgblack@eecs.umich.edu{ 724626SN/A 738833Sdam.sunwoo@arm.com protected: 742810SN/A 753194SN/A /** 762810SN/A * Declaration of the non-coherent bus slave port type, one will 772810SN/A * be instantiated for each of the master ports connecting to the 782810SN/A * bus. 792810SN/A */ 802810SN/A class NoncoherentBusSlavePort : public SlavePort 814628SN/A { 824628SN/A private: 834628SN/A 844628SN/A /** A reference to the bus to which this port belongs. */ 854628SN/A NoncoherentBus &bus; 864628SN/A 874628SN/A public: 884628SN/A 898737Skoansin.tan@gmail.com NoncoherentBusSlavePort(const std::string &_name, 904628SN/A NoncoherentBus &_bus, PortID _id) 914628SN/A : SlavePort(_name, &_bus, _id), bus(_bus) 924628SN/A { } 934628SN/A 944628SN/A protected: 954628SN/A 964628SN/A /** 974628SN/A * When receiving a timing request, pass it to the bus. 984628SN/A */ 994628SN/A virtual bool recvTimingReq(PacketPtr pkt) 1004628SN/A { return bus.recvTimingReq(pkt, id); } 1014628SN/A 1024628SN/A /** 1034628SN/A * When receiving an atomic request, pass it to the bus. 1044628SN/A */ 1054628SN/A virtual Tick recvAtomic(PacketPtr pkt) 1064628SN/A { return bus.recvAtomic(pkt, id); } 1074628SN/A 1084628SN/A /** 1094628SN/A * When receiving a functional request, pass it to the bus. 1108737Skoansin.tan@gmail.com */ 1114628SN/A virtual void recvFunctional(PacketPtr pkt) 1128856Sandreas.hansson@arm.com { bus.recvFunctional(pkt, id); } 1138856Sandreas.hansson@arm.com 1148856Sandreas.hansson@arm.com /** 1158856Sandreas.hansson@arm.com * When receiving a retry, pass it to the bus. 1168856Sandreas.hansson@arm.com */ 1178856Sandreas.hansson@arm.com virtual void recvRetry() 1188856Sandreas.hansson@arm.com { panic("Bus slave ports always succeed and should never retry.\n"); } 1198856Sandreas.hansson@arm.com 1208856Sandreas.hansson@arm.com /** 1218922Swilliam.wang@arm.com * Return the union of all adress ranges seen by this bus. 1222810SN/A */ 1238856Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() 1242844SN/A { return bus.getAddrRanges(); } 1258856Sandreas.hansson@arm.com 1268856Sandreas.hansson@arm.com /** 1278856Sandreas.hansson@arm.com * Get the maximum block size as seen by the bus. 1288856Sandreas.hansson@arm.com */ 1298856Sandreas.hansson@arm.com virtual unsigned deviceBlockSize() const 1308856Sandreas.hansson@arm.com { return bus.findBlockSize(); } 1318856Sandreas.hansson@arm.com 1328856Sandreas.hansson@arm.com }; 1338856Sandreas.hansson@arm.com 1348914Sandreas.hansson@arm.com /** 1358856Sandreas.hansson@arm.com * Declaration of the bus master port type, one will be 1368856Sandreas.hansson@arm.com * instantiated for each of the slave ports connecting to the 1373738SN/A * bus. 1384458SN/A */ 1398856Sandreas.hansson@arm.com class NoncoherentBusMasterPort : public MasterPort 1408975Sandreas.hansson@arm.com { 1418922Swilliam.wang@arm.com private: 1428914Sandreas.hansson@arm.com 1432810SN/A /** A reference to the bus to which this port belongs. */ 1448856Sandreas.hansson@arm.com NoncoherentBus &bus; 1458856Sandreas.hansson@arm.com 1468856Sandreas.hansson@arm.com public: 1478914Sandreas.hansson@arm.com 1488856Sandreas.hansson@arm.com NoncoherentBusMasterPort(const std::string &_name, 1498922Swilliam.wang@arm.com NoncoherentBus &_bus, PortID _id) 1508856Sandreas.hansson@arm.com : MasterPort(_name, &_bus, _id), bus(_bus) 1513013SN/A { } 1528856Sandreas.hansson@arm.com 1538856Sandreas.hansson@arm.com protected: 1548856Sandreas.hansson@arm.com 1558856Sandreas.hansson@arm.com /** 1568856Sandreas.hansson@arm.com * When receiving a timing response, pass it to the bus. 1578856Sandreas.hansson@arm.com */ 1588856Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt) 1598856Sandreas.hansson@arm.com { return bus.recvTimingResp(pkt, id); } 1608922Swilliam.wang@arm.com 1618856Sandreas.hansson@arm.com /** When reciving a range change from the peer port (at id), 1625314SN/A pass it to the bus. */ 1632811SN/A virtual void recvRangeChange() 1648856Sandreas.hansson@arm.com { bus.recvRangeChange(id); } 1658856Sandreas.hansson@arm.com 1662810SN/A /** When reciving a retry from the peer port (at id), 1672810SN/A pass it to the bus. */ 1688856Sandreas.hansson@arm.com virtual void recvRetry() 1692810SN/A { bus.recvRetry(); } 1702810SN/A 1718856Sandreas.hansson@arm.com /** 1728856Sandreas.hansson@arm.com * Get the maximum block size as seen by the bus. 1738856Sandreas.hansson@arm.com */ 1748856Sandreas.hansson@arm.com virtual unsigned deviceBlockSize() const 1753606SN/A { return bus.findBlockSize(); } 1768914Sandreas.hansson@arm.com 1778975Sandreas.hansson@arm.com }; 1788914Sandreas.hansson@arm.com 1792810SN/A /** Function called by the port when the bus is recieving a Timing 1802810SN/A request packet.*/ 1812897SN/A bool recvTimingReq(PacketPtr pkt, PortID slave_port_id); 1822897SN/A 1838856Sandreas.hansson@arm.com /** Function called by the port when the bus is recieving a Timing 1844458SN/A response packet.*/ 1859087Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt, PortID master_port_id); 1868856Sandreas.hansson@arm.com 1872811SN/A /** Function called by the port when the bus is recieving a Atomic 1882810SN/A transaction.*/ 1898856Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt, PortID slave_port_id); 1908856Sandreas.hansson@arm.com 1913338SN/A /** Function called by the port when the bus is recieving a Functional 1924626SN/A transaction.*/ 1934626SN/A void recvFunctional(PacketPtr pkt, PortID slave_port_id); 1944626SN/A 1954626SN/A public: 1964626SN/A 1974626SN/A NoncoherentBus(const NoncoherentBusParams *p); 1984626SN/A 1994626SN/A}; 2004628SN/A 2014628SN/A#endif //__MEM_NONCOHERENT_BUS_HH__ 2024628SN/A