noncoherent_xbar.cc revision 10888
12497SN/A/*
210719SMarco.Balboni@ARM.com * Copyright (c) 2011-2015 ARM Limited
38711SN/A * All rights reserved
48711SN/A *
58711SN/A * The license below extends only to copyright in the software and shall
68711SN/A * not be construed as granting a license to any other intellectual
78711SN/A * property including but not limited to intellectual property relating
88711SN/A * to a hardware implementation of the functionality of the software
98711SN/A * licensed hereunder.  You may use the software subject to the license
108711SN/A * terms below provided that you ensure that this notice is replicated
118711SN/A * unmodified and in its entirety in all distributions of the software,
128711SN/A * modified or unmodified, in source code or in binary form.
138711SN/A *
142497SN/A * Copyright (c) 2006 The Regents of The University of Michigan
152497SN/A * All rights reserved.
162497SN/A *
172497SN/A * Redistribution and use in source and binary forms, with or without
182497SN/A * modification, are permitted provided that the following conditions are
192497SN/A * met: redistributions of source code must retain the above copyright
202497SN/A * notice, this list of conditions and the following disclaimer;
212497SN/A * redistributions in binary form must reproduce the above copyright
222497SN/A * notice, this list of conditions and the following disclaimer in the
232497SN/A * documentation and/or other materials provided with the distribution;
242497SN/A * neither the name of the copyright holders nor the names of its
252497SN/A * contributors may be used to endorse or promote products derived from
262497SN/A * this software without specific prior written permission.
272497SN/A *
282497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665SN/A *
402665SN/A * Authors: Ali Saidi
418715SN/A *          Andreas Hansson
428922SN/A *          William Wang
432497SN/A */
442497SN/A
452497SN/A/**
462982SN/A * @file
4710405Sandreas.hansson@arm.com * Definition of a non-coherent crossbar object.
482497SN/A */
492497SN/A
502846SN/A#include "base/misc.hh"
512548SN/A#include "base/trace.hh"
5210405Sandreas.hansson@arm.com#include "debug/NoncoherentXBar.hh"
5310405Sandreas.hansson@arm.com#include "debug/XBar.hh"
5410405Sandreas.hansson@arm.com#include "mem/noncoherent_xbar.hh"
552497SN/A
5610405Sandreas.hansson@arm.comNoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams *p)
5710405Sandreas.hansson@arm.com    : BaseXBar(p)
587523SN/A{
598851SN/A    // create the ports based on the size of the master and slave
608948SN/A    // vector ports, and the presence of the default port, the ports
618948SN/A    // are enumerated starting from zero
628851SN/A    for (int i = 0; i < p->port_master_connection_count; ++i) {
639095SN/A        std::string portName = csprintf("%s.master[%d]", name(), i);
6410405Sandreas.hansson@arm.com        MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this, i);
658922SN/A        masterPorts.push_back(bp);
669715SN/A        reqLayers.push_back(new ReqLayer(*bp, *this,
679715SN/A                                         csprintf(".reqLayer%d", i)));
688851SN/A    }
698851SN/A
708948SN/A    // see if we have a default slave device connected and if so add
718948SN/A    // our corresponding master port
728915SN/A    if (p->port_default_connection_count) {
739031SN/A        defaultPortID = masterPorts.size();
749095SN/A        std::string portName = name() + ".default";
7510405Sandreas.hansson@arm.com        MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this,
769036SN/A                                                      defaultPortID);
778922SN/A        masterPorts.push_back(bp);
789715SN/A        reqLayers.push_back(new ReqLayer(*bp, *this, csprintf(".reqLayer%d",
799715SN/A                                                              defaultPortID)));
808915SN/A    }
818915SN/A
828948SN/A    // create the slave ports, once again starting at zero
838851SN/A    for (int i = 0; i < p->port_slave_connection_count; ++i) {
849095SN/A        std::string portName = csprintf("%s.slave[%d]", name(), i);
8510888Sandreas.hansson@arm.com        QueuedSlavePort* bp = new NoncoherentXBarSlavePort(portName, *this, i);
868922SN/A        slavePorts.push_back(bp);
879715SN/A        respLayers.push_back(new RespLayer(*bp, *this,
889715SN/A                                           csprintf(".respLayer%d", i)));
898851SN/A    }
908851SN/A
917523SN/A    clearPortCache();
927523SN/A}
937523SN/A
9410405Sandreas.hansson@arm.comNoncoherentXBar::~NoncoherentXBar()
959715SN/A{
9610405Sandreas.hansson@arm.com    for (auto l: reqLayers)
9710405Sandreas.hansson@arm.com        delete l;
9810405Sandreas.hansson@arm.com    for (auto l: respLayers)
9910405Sandreas.hansson@arm.com        delete l;
1009715SN/A}
1019715SN/A
1028948SN/Abool
10310405Sandreas.hansson@arm.comNoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
1043244SN/A{
1058975SN/A    // determine the source port based on the id
1069032SN/A    SlavePort *src_port = slavePorts[slave_port_id];
1073244SN/A
10810405Sandreas.hansson@arm.com    // we should never see express snoops on a non-coherent crossbar
1099036SN/A    assert(!pkt->isExpressSnoop());
1109036SN/A
1119612SN/A    // determine the destination based on the address
1129712SN/A    PortID master_port_id = findPort(pkt->getAddr());
1139612SN/A
11410405Sandreas.hansson@arm.com    // test if the layer should be considered occupied for the current
1159036SN/A    // port
1169715SN/A    if (!reqLayers[master_port_id]->tryTiming(src_port)) {
11710405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x BUSY\n",
1188949SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1193244SN/A        return false;
1203244SN/A    }
1213244SN/A
12210405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x\n",
1238949SN/A            src_port->name(), pkt->cmdString(), pkt->getAddr());
1245197SN/A
1259712SN/A    // store size and command as they might be modified when
1269712SN/A    // forwarding the packet
1279712SN/A    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
1289712SN/A    unsigned int pkt_cmd = pkt->cmdToIndex();
1299712SN/A
13010719SMarco.Balboni@ARM.com    // store the old header delay so we can restore it if needed
13110719SMarco.Balboni@ARM.com    Tick old_header_delay = pkt->headerDelay;
13210719SMarco.Balboni@ARM.com
13310719SMarco.Balboni@ARM.com    // a request sees the frontend and forward latency
13410719SMarco.Balboni@ARM.com    Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
13510719SMarco.Balboni@ARM.com
13610719SMarco.Balboni@ARM.com    // set the packet header and payload delay
13710719SMarco.Balboni@ARM.com    calcPacketTiming(pkt, xbar_delay);
13810719SMarco.Balboni@ARM.com
13910719SMarco.Balboni@ARM.com    // determine how long to be crossbar layer is busy
14010719SMarco.Balboni@ARM.com    Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
1418915SN/A
14210656Sandreas.hansson@arm.com    // before forwarding the packet (and possibly altering it),
14310656Sandreas.hansson@arm.com    // remember if we are expecting a response
14410656Sandreas.hansson@arm.com    const bool expect_response = pkt->needsResponse() &&
14510656Sandreas.hansson@arm.com        !pkt->memInhibitAsserted();
14610656Sandreas.hansson@arm.com
1479612SN/A    // since it is a normal request, attempt to send the packet
1489712SN/A    bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
1498948SN/A
1508975SN/A    if (!success)  {
1518975SN/A        // inhibited packets should never be forced to retry
1528975SN/A        assert(!pkt->memInhibitAsserted());
1538948SN/A
15410405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x RETRY\n",
1558975SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1568948SN/A
15710719SMarco.Balboni@ARM.com        // restore the header delay as it is additive
15810719SMarco.Balboni@ARM.com        pkt->headerDelay = old_header_delay;
1599549SN/A
1609547SN/A        // occupy until the header is sent
1619715SN/A        reqLayers[master_port_id]->failedTiming(src_port,
16210719SMarco.Balboni@ARM.com                                                clockEdge(Cycles(1)));
1638948SN/A
1648975SN/A        return false;
1658975SN/A    }
1668975SN/A
16710656Sandreas.hansson@arm.com    // remember where to route the response to
16810656Sandreas.hansson@arm.com    if (expect_response) {
16910656Sandreas.hansson@arm.com        assert(routeTo.find(pkt->req) == routeTo.end());
17010656Sandreas.hansson@arm.com        routeTo[pkt->req] = slave_port_id;
17110656Sandreas.hansson@arm.com    }
17210656Sandreas.hansson@arm.com
1739715SN/A    reqLayers[master_port_id]->succeededTiming(packetFinishTime);
1748975SN/A
1759712SN/A    // stats updates
1769712SN/A    pktCount[slave_port_id][master_port_id]++;
17710405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
1789712SN/A    transDist[pkt_cmd]++;
1799712SN/A
1808975SN/A    return true;
1818975SN/A}
1828975SN/A
1838975SN/Abool
18410405Sandreas.hansson@arm.comNoncoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
1858975SN/A{
1868975SN/A    // determine the source port based on the id
1879032SN/A    MasterPort *src_port = masterPorts[master_port_id];
1888975SN/A
18910656Sandreas.hansson@arm.com    // determine the destination
19010656Sandreas.hansson@arm.com    const auto route_lookup = routeTo.find(pkt->req);
19110656Sandreas.hansson@arm.com    assert(route_lookup != routeTo.end());
19210656Sandreas.hansson@arm.com    const PortID slave_port_id = route_lookup->second;
19310572Sandreas.hansson@arm.com    assert(slave_port_id != InvalidPortID);
19410572Sandreas.hansson@arm.com    assert(slave_port_id < respLayers.size());
1959713SN/A
19610405Sandreas.hansson@arm.com    // test if the layer should be considered occupied for the current
1979033SN/A    // port
1989715SN/A    if (!respLayers[slave_port_id]->tryTiming(src_port)) {
19910405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x BUSY\n",
2008975SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
2018975SN/A        return false;
2028975SN/A    }
2038975SN/A
20410405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x\n",
2058975SN/A            src_port->name(), pkt->cmdString(), pkt->getAddr());
2068975SN/A
2079712SN/A    // store size and command as they might be modified when
2089712SN/A    // forwarding the packet
2099712SN/A    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
2109712SN/A    unsigned int pkt_cmd = pkt->cmdToIndex();
2119712SN/A
21210719SMarco.Balboni@ARM.com    // a response sees the response latency
21310719SMarco.Balboni@ARM.com    Tick xbar_delay = responseLatency * clockPeriod();
21410719SMarco.Balboni@ARM.com
21510719SMarco.Balboni@ARM.com    // set the packet header and payload delay
21610719SMarco.Balboni@ARM.com    calcPacketTiming(pkt, xbar_delay);
21710719SMarco.Balboni@ARM.com
21810719SMarco.Balboni@ARM.com    // determine how long to be crossbar layer is busy
21910719SMarco.Balboni@ARM.com    Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
2208975SN/A
22110888Sandreas.hansson@arm.com    // send the packet through the destination slave port, and pay for
22210888Sandreas.hansson@arm.com    // any outstanding latency
22310888Sandreas.hansson@arm.com    Tick latency = pkt->headerDelay;
22410888Sandreas.hansson@arm.com    pkt->headerDelay = 0;
22510888Sandreas.hansson@arm.com    slavePorts[slave_port_id]->schedTimingResp(pkt, curTick() + latency);
2268975SN/A
22710656Sandreas.hansson@arm.com    // remove the request from the routing table
22810656Sandreas.hansson@arm.com    routeTo.erase(route_lookup);
22910656Sandreas.hansson@arm.com
2309715SN/A    respLayers[slave_port_id]->succeededTiming(packetFinishTime);
2318975SN/A
2329712SN/A    // stats updates
2339712SN/A    pktCount[slave_port_id][master_port_id]++;
23410405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
2359712SN/A    transDist[pkt_cmd]++;
2369712SN/A
2378975SN/A    return true;
2388975SN/A}
2398975SN/A
2409092SN/Avoid
24110713Sandreas.hansson@arm.comNoncoherentXBar::recvReqRetry(PortID master_port_id)
2429092SN/A{
2439093SN/A    // responses never block on forwarding them, so the retry will
2449093SN/A    // always be coming from a port to which we tried to forward a
2459093SN/A    // request
2469715SN/A    reqLayers[master_port_id]->recvRetry();
2479092SN/A}
2489092SN/A
2499036SN/ATick
25010405Sandreas.hansson@arm.comNoncoherentXBar::recvAtomic(PacketPtr pkt, PortID slave_port_id)
2518975SN/A{
25210405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
2539032SN/A            slavePorts[slave_port_id]->name(), pkt->getAddr(),
2548949SN/A            pkt->cmdString());
2558915SN/A
25610405Sandreas.hansson@arm.com    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
25710405Sandreas.hansson@arm.com    unsigned int pkt_cmd = pkt->cmdToIndex();
2589712SN/A
2599036SN/A    // determine the destination port
26010405Sandreas.hansson@arm.com    PortID master_port_id = findPort(pkt->getAddr());
26110405Sandreas.hansson@arm.com
26210405Sandreas.hansson@arm.com    // stats updates for the request
26310405Sandreas.hansson@arm.com    pktCount[slave_port_id][master_port_id]++;
26410405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
26510405Sandreas.hansson@arm.com    transDist[pkt_cmd]++;
2668948SN/A
2678948SN/A    // forward the request to the appropriate destination
26810405Sandreas.hansson@arm.com    Tick response_latency = masterPorts[master_port_id]->sendAtomic(pkt);
2698948SN/A
2709712SN/A    // add the response data
27110405Sandreas.hansson@arm.com    if (pkt->isResponse()) {
27210405Sandreas.hansson@arm.com        pkt_size = pkt->hasData() ? pkt->getSize() : 0;
27310405Sandreas.hansson@arm.com        pkt_cmd = pkt->cmdToIndex();
27410405Sandreas.hansson@arm.com
27510405Sandreas.hansson@arm.com        // stats updates
27610405Sandreas.hansson@arm.com        pktCount[slave_port_id][master_port_id]++;
27710405Sandreas.hansson@arm.com        pktSize[slave_port_id][master_port_id] += pkt_size;
27810405Sandreas.hansson@arm.com        transDist[pkt_cmd]++;
27910405Sandreas.hansson@arm.com    }
2809712SN/A
2819547SN/A    // @todo: Not setting first-word time
28210694SMarco.Balboni@ARM.com    pkt->payloadDelay = response_latency;
2838948SN/A    return response_latency;
2848948SN/A}
2858948SN/A
2862497SN/Avoid
28710405Sandreas.hansson@arm.comNoncoherentXBar::recvFunctional(PacketPtr pkt, PortID slave_port_id)
2882497SN/A{
2898663SN/A    if (!pkt->isPrint()) {
2908663SN/A        // don't do DPRINTFs on PrintReq as it clutters up the output
29110405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar,
2928949SN/A                "recvFunctional: packet src %s addr 0x%x cmd %s\n",
2939032SN/A                slavePorts[slave_port_id]->name(), pkt->getAddr(),
2948663SN/A                pkt->cmdString());
2958663SN/A    }
2968663SN/A
29710888Sandreas.hansson@arm.com    // since our slave ports are queued ports we need to check them as well
29810888Sandreas.hansson@arm.com    for (const auto& p : slavePorts) {
29910888Sandreas.hansson@arm.com        // if we find a response that has the data, then the
30010888Sandreas.hansson@arm.com        // downstream caches/memories may be out of date, so simply stop
30110888Sandreas.hansson@arm.com        // here
30210888Sandreas.hansson@arm.com        if (p->checkFunctional(pkt)) {
30310888Sandreas.hansson@arm.com            if (pkt->needsResponse())
30410888Sandreas.hansson@arm.com                pkt->makeResponse();
30510888Sandreas.hansson@arm.com            return;
30610888Sandreas.hansson@arm.com        }
30710888Sandreas.hansson@arm.com    }
30810888Sandreas.hansson@arm.com
3099036SN/A    // determine the destination port
3109036SN/A    PortID dest_id = findPort(pkt->getAddr());
3114912SN/A
3129036SN/A    // forward the request to the appropriate destination
3139036SN/A    masterPorts[dest_id]->sendFunctional(pkt);
3148948SN/A}
3158948SN/A
3169092SN/Aunsigned int
31710405Sandreas.hansson@arm.comNoncoherentXBar::drain(DrainManager *dm)
3189092SN/A{
3199093SN/A    // sum up the individual layers
3209715SN/A    unsigned int total = 0;
32110405Sandreas.hansson@arm.com    for (auto l: reqLayers)
32210405Sandreas.hansson@arm.com        total += l->drain(dm);
32310405Sandreas.hansson@arm.com    for (auto l: respLayers)
32410405Sandreas.hansson@arm.com        total += l->drain(dm);
3259715SN/A    return total;
3269092SN/A}
3279092SN/A
32810405Sandreas.hansson@arm.comNoncoherentXBar*
32910405Sandreas.hansson@arm.comNoncoherentXBarParams::create()
3308948SN/A{
33110405Sandreas.hansson@arm.com    return new NoncoherentXBar(this);
3328948SN/A}
3339712SN/A
3349712SN/Avoid
33510405Sandreas.hansson@arm.comNoncoherentXBar::regStats()
3369712SN/A{
33710405Sandreas.hansson@arm.com    // register the stats of the base class and our layers
33810405Sandreas.hansson@arm.com    BaseXBar::regStats();
33910405Sandreas.hansson@arm.com    for (auto l: reqLayers)
34010405Sandreas.hansson@arm.com        l->regStats();
34110405Sandreas.hansson@arm.com    for (auto l: respLayers)
34210405Sandreas.hansson@arm.com        l->regStats();
3439712SN/A}
344