noncoherent_xbar.cc revision 10656
12497SN/A/*
210405Sandreas.hansson@arm.com * Copyright (c) 2011-2014 ARM Limited
38711SN/A * All rights reserved
48711SN/A *
58711SN/A * The license below extends only to copyright in the software and shall
68711SN/A * not be construed as granting a license to any other intellectual
78711SN/A * property including but not limited to intellectual property relating
88711SN/A * to a hardware implementation of the functionality of the software
98711SN/A * licensed hereunder.  You may use the software subject to the license
108711SN/A * terms below provided that you ensure that this notice is replicated
118711SN/A * unmodified and in its entirety in all distributions of the software,
128711SN/A * modified or unmodified, in source code or in binary form.
138711SN/A *
142497SN/A * Copyright (c) 2006 The Regents of The University of Michigan
152497SN/A * All rights reserved.
162497SN/A *
172497SN/A * Redistribution and use in source and binary forms, with or without
182497SN/A * modification, are permitted provided that the following conditions are
192497SN/A * met: redistributions of source code must retain the above copyright
202497SN/A * notice, this list of conditions and the following disclaimer;
212497SN/A * redistributions in binary form must reproduce the above copyright
222497SN/A * notice, this list of conditions and the following disclaimer in the
232497SN/A * documentation and/or other materials provided with the distribution;
242497SN/A * neither the name of the copyright holders nor the names of its
252497SN/A * contributors may be used to endorse or promote products derived from
262497SN/A * this software without specific prior written permission.
272497SN/A *
282497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665SN/A *
402665SN/A * Authors: Ali Saidi
418715SN/A *          Andreas Hansson
428922SN/A *          William Wang
432497SN/A */
442497SN/A
452497SN/A/**
462982SN/A * @file
4710405Sandreas.hansson@arm.com * Definition of a non-coherent crossbar object.
482497SN/A */
492497SN/A
502846SN/A#include "base/misc.hh"
512548SN/A#include "base/trace.hh"
5210405Sandreas.hansson@arm.com#include "debug/NoncoherentXBar.hh"
5310405Sandreas.hansson@arm.com#include "debug/XBar.hh"
5410405Sandreas.hansson@arm.com#include "mem/noncoherent_xbar.hh"
552497SN/A
5610405Sandreas.hansson@arm.comNoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams *p)
5710405Sandreas.hansson@arm.com    : BaseXBar(p)
587523SN/A{
598851SN/A    // create the ports based on the size of the master and slave
608948SN/A    // vector ports, and the presence of the default port, the ports
618948SN/A    // are enumerated starting from zero
628851SN/A    for (int i = 0; i < p->port_master_connection_count; ++i) {
639095SN/A        std::string portName = csprintf("%s.master[%d]", name(), i);
6410405Sandreas.hansson@arm.com        MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this, i);
658922SN/A        masterPorts.push_back(bp);
669715SN/A        reqLayers.push_back(new ReqLayer(*bp, *this,
679715SN/A                                         csprintf(".reqLayer%d", i)));
688851SN/A    }
698851SN/A
708948SN/A    // see if we have a default slave device connected and if so add
718948SN/A    // our corresponding master port
728915SN/A    if (p->port_default_connection_count) {
739031SN/A        defaultPortID = masterPorts.size();
749095SN/A        std::string portName = name() + ".default";
7510405Sandreas.hansson@arm.com        MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this,
769036SN/A                                                      defaultPortID);
778922SN/A        masterPorts.push_back(bp);
789715SN/A        reqLayers.push_back(new ReqLayer(*bp, *this, csprintf(".reqLayer%d",
799715SN/A                                                              defaultPortID)));
808915SN/A    }
818915SN/A
828948SN/A    // create the slave ports, once again starting at zero
838851SN/A    for (int i = 0; i < p->port_slave_connection_count; ++i) {
849095SN/A        std::string portName = csprintf("%s.slave[%d]", name(), i);
8510405Sandreas.hansson@arm.com        SlavePort* bp = new NoncoherentXBarSlavePort(portName, *this, i);
868922SN/A        slavePorts.push_back(bp);
879715SN/A        respLayers.push_back(new RespLayer(*bp, *this,
889715SN/A                                           csprintf(".respLayer%d", i)));
898851SN/A    }
908851SN/A
917523SN/A    clearPortCache();
927523SN/A}
937523SN/A
9410405Sandreas.hansson@arm.comNoncoherentXBar::~NoncoherentXBar()
959715SN/A{
9610405Sandreas.hansson@arm.com    for (auto l: reqLayers)
9710405Sandreas.hansson@arm.com        delete l;
9810405Sandreas.hansson@arm.com    for (auto l: respLayers)
9910405Sandreas.hansson@arm.com        delete l;
1009715SN/A}
1019715SN/A
1028948SN/Abool
10310405Sandreas.hansson@arm.comNoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
1043244SN/A{
1058975SN/A    // determine the source port based on the id
1069032SN/A    SlavePort *src_port = slavePorts[slave_port_id];
1073244SN/A
10810405Sandreas.hansson@arm.com    // we should never see express snoops on a non-coherent crossbar
1099036SN/A    assert(!pkt->isExpressSnoop());
1109036SN/A
1119612SN/A    // determine the destination based on the address
1129712SN/A    PortID master_port_id = findPort(pkt->getAddr());
1139612SN/A
11410405Sandreas.hansson@arm.com    // test if the layer should be considered occupied for the current
1159036SN/A    // port
1169715SN/A    if (!reqLayers[master_port_id]->tryTiming(src_port)) {
11710405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x BUSY\n",
1188949SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1193244SN/A        return false;
1203244SN/A    }
1213244SN/A
12210405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x\n",
1238949SN/A            src_port->name(), pkt->cmdString(), pkt->getAddr());
1245197SN/A
1259712SN/A    // store size and command as they might be modified when
1269712SN/A    // forwarding the packet
1279712SN/A    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
1289712SN/A    unsigned int pkt_cmd = pkt->cmdToIndex();
1299712SN/A
1309547SN/A    calcPacketTiming(pkt);
13110405Sandreas.hansson@arm.com    Tick packetFinishTime = pkt->lastWordDelay + curTick();
1328915SN/A
13310656Sandreas.hansson@arm.com    // before forwarding the packet (and possibly altering it),
13410656Sandreas.hansson@arm.com    // remember if we are expecting a response
13510656Sandreas.hansson@arm.com    const bool expect_response = pkt->needsResponse() &&
13610656Sandreas.hansson@arm.com        !pkt->memInhibitAsserted();
13710656Sandreas.hansson@arm.com
1389612SN/A    // since it is a normal request, attempt to send the packet
1399712SN/A    bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
1408948SN/A
1418975SN/A    if (!success)  {
1428975SN/A        // inhibited packets should never be forced to retry
1438975SN/A        assert(!pkt->memInhibitAsserted());
1448948SN/A
14510405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x RETRY\n",
1468975SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1478948SN/A
1489549SN/A        // undo the calculation so we can check for 0 again
14910405Sandreas.hansson@arm.com        pkt->firstWordDelay = pkt->lastWordDelay = 0;
1509549SN/A
1519547SN/A        // occupy until the header is sent
1529715SN/A        reqLayers[master_port_id]->failedTiming(src_port,
1539715SN/A                                                clockEdge(headerCycles));
1548948SN/A
1558975SN/A        return false;
1568975SN/A    }
1578975SN/A
15810656Sandreas.hansson@arm.com    // remember where to route the response to
15910656Sandreas.hansson@arm.com    if (expect_response) {
16010656Sandreas.hansson@arm.com        assert(routeTo.find(pkt->req) == routeTo.end());
16110656Sandreas.hansson@arm.com        routeTo[pkt->req] = slave_port_id;
16210656Sandreas.hansson@arm.com    }
16310656Sandreas.hansson@arm.com
1649715SN/A    reqLayers[master_port_id]->succeededTiming(packetFinishTime);
1658975SN/A
1669712SN/A    // stats updates
1679712SN/A    pktCount[slave_port_id][master_port_id]++;
16810405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
1699712SN/A    transDist[pkt_cmd]++;
1709712SN/A
1718975SN/A    return true;
1728975SN/A}
1738975SN/A
1748975SN/Abool
17510405Sandreas.hansson@arm.comNoncoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
1768975SN/A{
1778975SN/A    // determine the source port based on the id
1789032SN/A    MasterPort *src_port = masterPorts[master_port_id];
1798975SN/A
18010656Sandreas.hansson@arm.com    // determine the destination
18110656Sandreas.hansson@arm.com    const auto route_lookup = routeTo.find(pkt->req);
18210656Sandreas.hansson@arm.com    assert(route_lookup != routeTo.end());
18310656Sandreas.hansson@arm.com    const PortID slave_port_id = route_lookup->second;
18410572Sandreas.hansson@arm.com    assert(slave_port_id != InvalidPortID);
18510572Sandreas.hansson@arm.com    assert(slave_port_id < respLayers.size());
1869713SN/A
18710405Sandreas.hansson@arm.com    // test if the layer should be considered occupied for the current
1889033SN/A    // port
1899715SN/A    if (!respLayers[slave_port_id]->tryTiming(src_port)) {
19010405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x BUSY\n",
1918975SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1928975SN/A        return false;
1938975SN/A    }
1948975SN/A
19510405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x\n",
1968975SN/A            src_port->name(), pkt->cmdString(), pkt->getAddr());
1978975SN/A
1989712SN/A    // store size and command as they might be modified when
1999712SN/A    // forwarding the packet
2009712SN/A    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
2019712SN/A    unsigned int pkt_cmd = pkt->cmdToIndex();
2029712SN/A
2038975SN/A    calcPacketTiming(pkt);
20410405Sandreas.hansson@arm.com    Tick packetFinishTime = pkt->lastWordDelay + curTick();
2058975SN/A
2069712SN/A    // send the packet through the destination slave port
2079713SN/A    bool success M5_VAR_USED = slavePorts[slave_port_id]->sendTimingResp(pkt);
2088975SN/A
2098975SN/A    // currently it is illegal to block responses... can lead to
2108975SN/A    // deadlock
2118975SN/A    assert(success);
2128975SN/A
21310656Sandreas.hansson@arm.com    // remove the request from the routing table
21410656Sandreas.hansson@arm.com    routeTo.erase(route_lookup);
21510656Sandreas.hansson@arm.com
2169715SN/A    respLayers[slave_port_id]->succeededTiming(packetFinishTime);
2178975SN/A
2189712SN/A    // stats updates
2199712SN/A    pktCount[slave_port_id][master_port_id]++;
22010405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
2219712SN/A    transDist[pkt_cmd]++;
2229712SN/A
2238975SN/A    return true;
2248975SN/A}
2258975SN/A
2269092SN/Avoid
22710405Sandreas.hansson@arm.comNoncoherentXBar::recvRetry(PortID master_port_id)
2289092SN/A{
2299093SN/A    // responses never block on forwarding them, so the retry will
2309093SN/A    // always be coming from a port to which we tried to forward a
2319093SN/A    // request
2329715SN/A    reqLayers[master_port_id]->recvRetry();
2339092SN/A}
2349092SN/A
2359036SN/ATick
23610405Sandreas.hansson@arm.comNoncoherentXBar::recvAtomic(PacketPtr pkt, PortID slave_port_id)
2378975SN/A{
23810405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
2399032SN/A            slavePorts[slave_port_id]->name(), pkt->getAddr(),
2408949SN/A            pkt->cmdString());
2418915SN/A
24210405Sandreas.hansson@arm.com    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
24310405Sandreas.hansson@arm.com    unsigned int pkt_cmd = pkt->cmdToIndex();
2449712SN/A
2459036SN/A    // determine the destination port
24610405Sandreas.hansson@arm.com    PortID master_port_id = findPort(pkt->getAddr());
24710405Sandreas.hansson@arm.com
24810405Sandreas.hansson@arm.com    // stats updates for the request
24910405Sandreas.hansson@arm.com    pktCount[slave_port_id][master_port_id]++;
25010405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
25110405Sandreas.hansson@arm.com    transDist[pkt_cmd]++;
2528948SN/A
2538948SN/A    // forward the request to the appropriate destination
25410405Sandreas.hansson@arm.com    Tick response_latency = masterPorts[master_port_id]->sendAtomic(pkt);
2558948SN/A
2569712SN/A    // add the response data
25710405Sandreas.hansson@arm.com    if (pkt->isResponse()) {
25810405Sandreas.hansson@arm.com        pkt_size = pkt->hasData() ? pkt->getSize() : 0;
25910405Sandreas.hansson@arm.com        pkt_cmd = pkt->cmdToIndex();
26010405Sandreas.hansson@arm.com
26110405Sandreas.hansson@arm.com        // stats updates
26210405Sandreas.hansson@arm.com        pktCount[slave_port_id][master_port_id]++;
26310405Sandreas.hansson@arm.com        pktSize[slave_port_id][master_port_id] += pkt_size;
26410405Sandreas.hansson@arm.com        transDist[pkt_cmd]++;
26510405Sandreas.hansson@arm.com    }
2669712SN/A
2679547SN/A    // @todo: Not setting first-word time
26810405Sandreas.hansson@arm.com    pkt->lastWordDelay = response_latency;
2698948SN/A    return response_latency;
2708948SN/A}
2718948SN/A
2722497SN/Avoid
27310405Sandreas.hansson@arm.comNoncoherentXBar::recvFunctional(PacketPtr pkt, PortID slave_port_id)
2742497SN/A{
2758663SN/A    if (!pkt->isPrint()) {
2768663SN/A        // don't do DPRINTFs on PrintReq as it clutters up the output
27710405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar,
2788949SN/A                "recvFunctional: packet src %s addr 0x%x cmd %s\n",
2799032SN/A                slavePorts[slave_port_id]->name(), pkt->getAddr(),
2808663SN/A                pkt->cmdString());
2818663SN/A    }
2828663SN/A
2839036SN/A    // determine the destination port
2849036SN/A    PortID dest_id = findPort(pkt->getAddr());
2854912SN/A
2869036SN/A    // forward the request to the appropriate destination
2879036SN/A    masterPorts[dest_id]->sendFunctional(pkt);
2888948SN/A}
2898948SN/A
2909092SN/Aunsigned int
29110405Sandreas.hansson@arm.comNoncoherentXBar::drain(DrainManager *dm)
2929092SN/A{
2939093SN/A    // sum up the individual layers
2949715SN/A    unsigned int total = 0;
29510405Sandreas.hansson@arm.com    for (auto l: reqLayers)
29610405Sandreas.hansson@arm.com        total += l->drain(dm);
29710405Sandreas.hansson@arm.com    for (auto l: respLayers)
29810405Sandreas.hansson@arm.com        total += l->drain(dm);
2999715SN/A    return total;
3009092SN/A}
3019092SN/A
30210405Sandreas.hansson@arm.comNoncoherentXBar*
30310405Sandreas.hansson@arm.comNoncoherentXBarParams::create()
3048948SN/A{
30510405Sandreas.hansson@arm.com    return new NoncoherentXBar(this);
3068948SN/A}
3079712SN/A
3089712SN/Avoid
30910405Sandreas.hansson@arm.comNoncoherentXBar::regStats()
3109712SN/A{
31110405Sandreas.hansson@arm.com    // register the stats of the base class and our layers
31210405Sandreas.hansson@arm.com    BaseXBar::regStats();
31310405Sandreas.hansson@arm.com    for (auto l: reqLayers)
31410405Sandreas.hansson@arm.com        l->regStats();
31510405Sandreas.hansson@arm.com    for (auto l: respLayers)
31610405Sandreas.hansson@arm.com        l->regStats();
3179712SN/A}
318