multi_level_page_table.hh revision 11168:f98eb2da15a4
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2014 Advanced Micro Devices, Inc. 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68856Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78856Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98856Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118856Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128856Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138856Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Alexandru Dutu 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Declaration of a multi-level page table. 342810SN/A */ 352810SN/A 362810SN/A#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 372810SN/A#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 382810SN/A 392810SN/A#include <string> 402810SN/A 412810SN/A#include "arch/isa_traits.hh" 422810SN/A#include "arch/tlb.hh" 432810SN/A#include "base/types.hh" 442810SN/A#include "config/the_isa.hh" 452810SN/A#include "mem/page_table.hh" 462810SN/A#include "sim/serialize.hh" 472810SN/A#include "sim/system.hh" 488232Snate@binkert.org 499152Satgutier@umich.edu/** 509795Sandreas.hansson@arm.com * This class implements an in-memory multi-level page table that can be 519795Sandreas.hansson@arm.com * configured to follow ISA specifications. It can be used instead of the 5210263Satgutier@umich.edu * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU) 535338Sstever@gmail.com * to do a normal page table walk. 549795Sandreas.hansson@arm.com * 555338Sstever@gmail.com * To reduce memory required to store the page table, a multi-level page 568786Sgblack@eecs.umich.edu * table stores its translations similarly with a radix tree. Let n be 572810SN/A * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies 582810SN/A * the number of entries for each level as base 2 logarithm values. A 592810SN/A * multi-level page table will store its translations at level 0 (the 608856Sandreas.hansson@arm.com * leaves of the tree) and it will be layed out in memory in the 618856Sandreas.hansson@arm.com * following way: 628856Sandreas.hansson@arm.com * 638922Swilliam.wang@arm.com * +------------------------------+ 648914Sandreas.hansson@arm.com * level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln| 658856Sandreas.hansson@arm.com * +------------------------------+ 668856Sandreas.hansson@arm.com * / \ 674475SN/A * +------------------------+ +------------------------+ 685034SN/A * level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1| 695034SN/A * +------------------------+ +------------------------+ 7010360Sandreas.hansson@arm.com * / \ / \ 7110622Smitch.hayenga@arm.com * . 7210622Smitch.hayenga@arm.com * . 734628SN/A * . 749814Sandreas.hansson@arm.com * / / \ 7510693SMarco.Balboni@ARM.com * +------------------+ +------------+ +------------+ 7610693SMarco.Balboni@ARM.com * level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1| 7710693SMarco.Balboni@ARM.com * +------------------+ +------------+ +------------+ 789263Smrinmoy.ghosh@arm.com * , where 795034SN/A * +------------------------------+ 806122SSteve.Reinhardt@amd.com * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk| 818134SAli.Saidi@ARM.com * +------------------------------+ 824626SN/A * is a level k entry that holds 2^Lk entries in Lk-1 level. 8310360Sandreas.hansson@arm.com * 844626SN/A * Essentially, a level n entry will contain 2^Ln level n-1 entries, 855034SN/A * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc. 868883SAli.Saidi@ARM.com * 878833Sdam.sunwoo@arm.com * The virtual address is split into offsets that index into the 884458SN/A * different levels of the page table. 892810SN/A * 902810SN/A * +--------------------------------+ 913013SN/A * |LnOffset|...|L1Offset|PageOffset| 928856Sandreas.hansson@arm.com * +--------------------------------+ 932810SN/A * 943013SN/A * For example L0Offset will be formed by the bits in range 9510714Sandreas.hansson@arm.com * [log2(PageOffset), log2(PageOffset)+L0]. 962810SN/A * 979614Srene.dejong@arm.com * For every level of the page table, from n to 1, the base address 989614Srene.dejong@arm.com * of the entry is loaded, the offset in the virtual address for 999614Srene.dejong@arm.com * that particular level is used to index into the entry which 10010345SCurtis.Dunham@arm.com * will reveal the memory address of the entry in the next level. 10110714Sandreas.hansson@arm.com * 10210345SCurtis.Dunham@arm.com * @see MultiLevelPageTable 1039614Srene.dejong@arm.com */ 1042810SN/Atemplate <class ISAOps> 1052810SN/Aclass MultiLevelPageTable : public PageTableBase 1062810SN/A{ 1078856Sandreas.hansson@arm.com /** 1082810SN/A * ISA specific operations 1093013SN/A */ 11010714Sandreas.hansson@arm.com ISAOps pTableISAOps; 1113013SN/A 1128856Sandreas.hansson@arm.com /** 11310714Sandreas.hansson@arm.com * Pointer to System object 1148922Swilliam.wang@arm.com */ 1152897SN/A System *system; 1162810SN/A 1172810SN/A /** 11810344Sandreas.hansson@arm.com * Physical address to the last level of the page table 11910344Sandreas.hansson@arm.com */ 12010344Sandreas.hansson@arm.com Addr basePtr; 12110714Sandreas.hansson@arm.com 12210344Sandreas.hansson@arm.com /** 12310344Sandreas.hansson@arm.com * Vector with sizes of all levels in base 2 logarithmic 12410344Sandreas.hansson@arm.com */ 12510713Sandreas.hansson@arm.com const std::vector<uint8_t> logLevelSize; 12610344Sandreas.hansson@arm.com 1272844SN/A /** 1282810SN/A * Number of levels contained by the page table 1292858SN/A */ 1302858SN/A const uint64_t numLevels; 1318856Sandreas.hansson@arm.com 1328922Swilliam.wang@arm.com /** 1338711Sandreas.hansson@arm.com * Method for walking the page table 1342858SN/A * 1352858SN/A * @param vaddr Virtual address that is being looked-up 1369294Sandreas.hansson@arm.com * @param allocate Specifies whether memory should be allocated while 1379294Sandreas.hansson@arm.com * walking the page table 1388922Swilliam.wang@arm.com * @return PTE_addr The address of the found PTE 1398922Swilliam.wang@arm.com * @retval true if the page table walk has succeded, false otherwhise 1408922Swilliam.wang@arm.com */ 1418922Swilliam.wang@arm.com bool walk(Addr vaddr, bool allocate, Addr &PTE_addr); 1428922Swilliam.wang@arm.com 1438922Swilliam.wang@arm.compublic: 1448922Swilliam.wang@arm.com MultiLevelPageTable(const std::string &__name, uint64_t _pid, 1458922Swilliam.wang@arm.com System *_sys); 1469294Sandreas.hansson@arm.com ~MultiLevelPageTable(); 1479294Sandreas.hansson@arm.com 1488922Swilliam.wang@arm.com void initState(ThreadContext* tc); 1498922Swilliam.wang@arm.com 1508922Swilliam.wang@arm.com void map(Addr vaddr, Addr paddr, int64_t size, 1518922Swilliam.wang@arm.com uint64_t flags = 0); 1528922Swilliam.wang@arm.com void remap(Addr vaddr, int64_t size, Addr new_vaddr); 1538922Swilliam.wang@arm.com void unmap(Addr vaddr, int64_t size); 1548922Swilliam.wang@arm.com bool isUnmapped(Addr vaddr, int64_t size); 1554628SN/A bool lookup(Addr vaddr, TheISA::TlbEntry &entry); 15610821Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15710821Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 15810821Sandreas.hansson@arm.com}; 15910821Sandreas.hansson@arm.com#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 16010821Sandreas.hansson@arm.com