multi_level_page_table.hh revision 11168
12SN/A/* 21762SN/A * Copyright (c) 2014 Advanced Micro Devices, Inc. 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Alexandru Dutu 292665Ssaidi@eecs.umich.edu */ 302665Ssaidi@eecs.umich.edu 312SN/A/** 322SN/A * @file 332SN/A * Declaration of a multi-level page table. 342SN/A */ 352SN/A 362655Sstever@eecs.umich.edu#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 372655Sstever@eecs.umich.edu#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 382SN/A 392SN/A#include <string> 401399SN/A 411396SN/A#include "arch/isa_traits.hh" 422SN/A#include "arch/tlb.hh" 432SN/A#include "base/types.hh" 442729Ssaidi@eecs.umich.edu#include "config/the_isa.hh" 452SN/A#include "mem/page_table.hh" 461310SN/A#include "sim/serialize.hh" 472SN/A#include "sim/system.hh" 482SN/A 492SN/A/** 502667Sstever@eecs.umich.edu * This class implements an in-memory multi-level page table that can be 5156SN/A * configured to follow ISA specifications. It can be used instead of the 52146SN/A * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU) 531388SN/A * to do a normal page table walk. 5456SN/A * 5556SN/A * To reduce memory required to store the page table, a multi-level page 561311SN/A * table stores its translations similarly with a radix tree. Let n be 57400SN/A * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies 583356Sbinkertn@umich.edu * the number of entries for each level as base 2 logarithm values. A 591717SN/A * multi-level page table will store its translations at level 0 (the 601717SN/A * leaves of the tree) and it will be layed out in memory in the 612738Sstever@eecs.umich.edu * following way: 622738Sstever@eecs.umich.edu * 63146SN/A * +------------------------------+ 64146SN/A * level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln| 65146SN/A * +------------------------------+ 662797Sktlim@umich.edu * / \ 6756SN/A * +------------------------+ +------------------------+ 6856SN/A * level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1| 6956SN/A * +------------------------+ +------------------------+ 703202Shsul@eecs.umich.edu * / \ / \ 71695SN/A * . 72695SN/A * . 731696SN/A * . 742SN/A * / / \ 752SN/A * +------------------+ +------------+ +------------+ 762SN/A * level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1| 772SN/A * +------------------+ +------------+ +------------+ 782SN/A * , where 792SN/A * +------------------------------+ 80329SN/A * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk| 812SN/A * +------------------------------+ 822SN/A * is a level k entry that holds 2^Lk entries in Lk-1 level. 832SN/A * 842SN/A * Essentially, a level n entry will contain 2^Ln level n-1 entries, 852SN/A * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc. 862SN/A * 872SN/A * The virtual address is split into offsets that index into the 882SN/A * different levels of the page table. 892SN/A * 902SN/A * +--------------------------------+ 912SN/A * |LnOffset|...|L1Offset|PageOffset| 922SN/A * +--------------------------------+ 93329SN/A * 94329SN/A * For example L0Offset will be formed by the bits in range 95329SN/A * [log2(PageOffset), log2(PageOffset)+L0]. 96329SN/A * 97329SN/A * For every level of the page table, from n to 1, the base address 98329SN/A * of the entry is loaded, the offset in the virtual address for 99329SN/A * that particular level is used to index into the entry which 1002SN/A * will reveal the memory address of the entry in the next level. 1012SN/A * 1022SN/A * @see MultiLevelPageTable 1032SN/A */ 1042SN/Atemplate <class ISAOps> 1052SN/Aclass MultiLevelPageTable : public PageTableBase 1062SN/A{ 1072SN/A /** 108764SN/A * ISA specific operations 109764SN/A */ 110764SN/A ISAOps pTableISAOps; 111764SN/A 112764SN/A /** 113764SN/A * Pointer to System object 114764SN/A */ 115764SN/A System *system; 116764SN/A 117764SN/A /** 118764SN/A * Physical address to the last level of the page table 119764SN/A */ 1203624Sbinkertn@umich.edu Addr basePtr; 1213624Sbinkertn@umich.edu 1223645Sbinkertn@umich.edu /** 1233624Sbinkertn@umich.edu * Vector with sizes of all levels in base 2 logarithmic 1242SN/A */ 1252SN/A const std::vector<uint8_t> logLevelSize; 1262SN/A 1272SN/A /** 1282SN/A * Number of levels contained by the page table 1292SN/A */ 130329SN/A const uint64_t numLevels; 131329SN/A 132329SN/A /** 133764SN/A * Method for walking the page table 1342SN/A * 1352655Sstever@eecs.umich.edu * @param vaddr Virtual address that is being looked-up 1362667Sstever@eecs.umich.edu * @param allocate Specifies whether memory should be allocated while 1372667Sstever@eecs.umich.edu * walking the page table 1382889Sbinkertn@umich.edu * @return PTE_addr The address of the found PTE 1392889Sbinkertn@umich.edu * @retval true if the page table walk has succeded, false otherwhise 1402889Sbinkertn@umich.edu */ 1412889Sbinkertn@umich.edu bool walk(Addr vaddr, bool allocate, Addr &PTE_addr); 1422667Sstever@eecs.umich.edu 1432667Sstever@eecs.umich.edupublic: 1442667Sstever@eecs.umich.edu MultiLevelPageTable(const std::string &__name, uint64_t _pid, 1452889Sbinkertn@umich.edu System *_sys); 1462889Sbinkertn@umich.edu ~MultiLevelPageTable(); 1472667Sstever@eecs.umich.edu 1482667Sstever@eecs.umich.edu void initState(ThreadContext* tc); 1492889Sbinkertn@umich.edu 1502667Sstever@eecs.umich.edu void map(Addr vaddr, Addr paddr, int64_t size, 1512667Sstever@eecs.umich.edu uint64_t flags = 0); 1523356Sbinkertn@umich.edu void remap(Addr vaddr, int64_t size, Addr new_vaddr); 1533356Sbinkertn@umich.edu void unmap(Addr vaddr, int64_t size); 1543356Sbinkertn@umich.edu bool isUnmapped(Addr vaddr, int64_t size); 1553356Sbinkertn@umich.edu bool lookup(Addr vaddr, TheISA::TlbEntry &entry); 1563356Sbinkertn@umich.edu void serialize(CheckpointOut &cp) const override; 1572667Sstever@eecs.umich.edu void unserialize(CheckpointIn &cp) override; 1582655Sstever@eecs.umich.edu}; 1592655Sstever@eecs.umich.edu#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 1601311SN/A