mem_checker_monitor.hh revision 10612:6332c9d471a8 
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 *          Andreas Hansson
39 *          Marco Elver
40 */
41
42#ifndef __MEM_MEM_CHECKER_MONITOR_HH__
43#define __MEM_MEM_CHECKER_MONITOR_HH__
44
45#include "base/statistics.hh"
46#include "mem/mem_checker.hh"
47#include "mem/mem_object.hh"
48#include "params/MemCheckerMonitor.hh"
49#include "sim/system.hh"
50
51/**
52 * Implements a MemChecker monitor, to be inserted between two ports.
53 */
54class MemCheckerMonitor : public MemObject
55{
56  public:
57
58    /** Parameters of memchecker monitor */
59    typedef MemCheckerMonitorParams Params;
60    const Params* params() const
61    { return reinterpret_cast<const Params*>(_params); }
62
63    /**
64     * Constructor based on the Python params
65     *
66     * @param params Python parameters
67     */
68    MemCheckerMonitor(Params* params);
69
70    /** Destructor */
71    ~MemCheckerMonitor();
72
73    virtual BaseMasterPort& getMasterPort(const std::string& if_name,
74                                          PortID idx = InvalidPortID);
75
76    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
77                                        PortID idx = InvalidPortID);
78
79    virtual void init();
80
81  private:
82
83    struct MemCheckerMonitorSenderState : public Packet::SenderState
84    {
85        MemCheckerMonitorSenderState(MemChecker::Serial _serial)
86            : serial(_serial)
87        {}
88
89        MemChecker::Serial serial;
90    };
91
92    /**
93     * This is the master port of the communication monitor. All recv
94     * functions call a function in MemCheckerMonitor, where the
95     * send function of the slave port is called. Besides this, these
96     * functions can also perform actions for capturing statistics.
97     */
98    class MonitorMasterPort : public MasterPort
99    {
100
101      public:
102
103        MonitorMasterPort(const std::string& _name, MemCheckerMonitor& _mon)
104            : MasterPort(_name, &_mon), mon(_mon)
105        { }
106
107      protected:
108
109        void recvFunctionalSnoop(PacketPtr pkt)
110        {
111            mon.recvFunctionalSnoop(pkt);
112        }
113
114        Tick recvAtomicSnoop(PacketPtr pkt)
115        {
116            return mon.recvAtomicSnoop(pkt);
117        }
118
119        bool recvTimingResp(PacketPtr pkt)
120        {
121            return mon.recvTimingResp(pkt);
122        }
123
124        void recvTimingSnoopReq(PacketPtr pkt)
125        {
126            mon.recvTimingSnoopReq(pkt);
127        }
128
129        void recvRangeChange()
130        {
131            mon.recvRangeChange();
132        }
133
134        bool isSnooping() const
135        {
136            return mon.isSnooping();
137        }
138
139        void recvRetry()
140        {
141            mon.recvRetryMaster();
142        }
143
144      private:
145
146        MemCheckerMonitor& mon;
147
148    };
149
150    /** Instance of master port, facing the memory side */
151    MonitorMasterPort masterPort;
152
153    /**
154     * This is the slave port of the communication monitor. All recv
155     * functions call a function in MemCheckerMonitor, where the
156     * send function of the master port is called. Besides this, these
157     * functions can also perform actions for capturing statistics.
158     */
159    class MonitorSlavePort : public SlavePort
160    {
161
162      public:
163
164        MonitorSlavePort(const std::string& _name, MemCheckerMonitor& _mon)
165            : SlavePort(_name, &_mon), mon(_mon)
166        { }
167
168      protected:
169
170        void recvFunctional(PacketPtr pkt)
171        {
172            mon.recvFunctional(pkt);
173        }
174
175        Tick recvAtomic(PacketPtr pkt)
176        {
177            return mon.recvAtomic(pkt);
178        }
179
180        bool recvTimingReq(PacketPtr pkt)
181        {
182            return mon.recvTimingReq(pkt);
183        }
184
185        bool recvTimingSnoopResp(PacketPtr pkt)
186        {
187            return mon.recvTimingSnoopResp(pkt);
188        }
189
190        AddrRangeList getAddrRanges() const
191        {
192            return mon.getAddrRanges();
193        }
194
195        void recvRetry()
196        {
197            mon.recvRetrySlave();
198        }
199
200      private:
201
202        MemCheckerMonitor& mon;
203
204    };
205
206    /** Instance of slave port, i.e. on the CPU side */
207    MonitorSlavePort slavePort;
208
209    void recvFunctional(PacketPtr pkt);
210
211    void recvFunctionalSnoop(PacketPtr pkt);
212
213    Tick recvAtomic(PacketPtr pkt);
214
215    Tick recvAtomicSnoop(PacketPtr pkt);
216
217    bool recvTimingReq(PacketPtr pkt);
218
219    bool recvTimingResp(PacketPtr pkt);
220
221    void recvTimingSnoopReq(PacketPtr pkt);
222
223    bool recvTimingSnoopResp(PacketPtr pkt);
224
225    AddrRangeList getAddrRanges() const;
226
227    bool isSnooping() const;
228
229    void recvRetryMaster();
230
231    void recvRetrySlave();
232
233    void recvRangeChange();
234
235    bool warnOnly;
236
237    MemChecker *memchecker;
238};
239
240#endif //__MEM_MEM_CHECKER_MONITOR_HH__
241