hmc_controller.hh revision 12492
19651SAndreas.Sandberg@ARM.com/* 29651SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2013 ARM Limited 39651SAndreas.Sandberg@ARM.com * All rights reserved 49651SAndreas.Sandberg@ARM.com * 59651SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69651SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79651SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89651SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99651SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109651SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119651SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129651SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139651SAndreas.Sandberg@ARM.com * 149651SAndreas.Sandberg@ARM.com * Copyright (c) 2015 The University of Bologna 159651SAndreas.Sandberg@ARM.com * All rights reserved. 169651SAndreas.Sandberg@ARM.com * 179651SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 189651SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 199651SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 209651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 219651SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 229651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 239651SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 249651SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 259651SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 269651SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 279651SAndreas.Sandberg@ARM.com * 289651SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299651SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309651SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319651SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329651SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339651SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349651SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359651SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369651SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379651SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389651SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399651SAndreas.Sandberg@ARM.com * 409651SAndreas.Sandberg@ARM.com * Authors: Erfan Azarkhish 419651SAndreas.Sandberg@ARM.com */ 429651SAndreas.Sandberg@ARM.com 4310114Sandreas@sandberg.pp.se 4410114Sandreas@sandberg.pp.se/** 4510114Sandreas@sandberg.pp.se * @file 469651SAndreas.Sandberg@ARM.com * HMCController declaration 4711629Smichael.lebeane@amd.com */ 489651SAndreas.Sandberg@ARM.com 499651SAndreas.Sandberg@ARM.com#ifndef __MEM_HMC_CONTROLLER_HH__ 509651SAndreas.Sandberg@ARM.com#define __MEM_HMC_CONTROLLER_HH__ 519651SAndreas.Sandberg@ARM.com 529651SAndreas.Sandberg@ARM.com#include "mem/noncoherent_xbar.hh" 539651SAndreas.Sandberg@ARM.com#include "mem/port.hh" 549651SAndreas.Sandberg@ARM.com#include "params/HMCController.hh" 559651SAndreas.Sandberg@ARM.com 5610114Sandreas@sandberg.pp.se/** 5710114Sandreas@sandberg.pp.se * HMC Controller, in general, is responsible for translating the host 589892Sandreas@sandberg.pp.se * protocol (AXI for example) to serial links protocol. Plus, it should have 599651SAndreas.Sandberg@ARM.com * large internal buffers to hide the access latency of the cube. It is also 609651SAndreas.Sandberg@ARM.com * inferred from the standard [1] and the literature [2] that serial links 619651SAndreas.Sandberg@ARM.com * share the same address range and packets can travel over any of them, so a 629651SAndreas.Sandberg@ARM.com * load distribution mechanism is required. 639651SAndreas.Sandberg@ARM.com * This model simply queues the incoming transactions (using a Bridge) and 649651SAndreas.Sandberg@ARM.com * schedules them to the serial links using a simple round robin mechanism to 659651SAndreas.Sandberg@ARM.com * balance the load among them. More advanced global scheduling policies and 669651SAndreas.Sandberg@ARM.com * reordering and steering of transactions can be added to this model if 679651SAndreas.Sandberg@ARM.com * required [3]. 689651SAndreas.Sandberg@ARM.com * [1] http://www.hybridmemorycube.org/specification-download/ 699651SAndreas.Sandberg@ARM.com * [2] Low-Power Hybrid Memory Cubes With Link Power Manageme and Two-Level 709651SAndreas.Sandberg@ARM.com * Prefetching (J. Ahn et. al) 719651SAndreas.Sandberg@ARM.com * [3] The Open-Silicon HMC Controller IP 729651SAndreas.Sandberg@ARM.com * http://www.open-silicon.com/open-silicon-ips/hmc/ 739651SAndreas.Sandberg@ARM.com */ 749651SAndreas.Sandberg@ARM.com 759651SAndreas.Sandberg@ARM.comclass HMCController : public NoncoherentXBar 769651SAndreas.Sandberg@ARM.com{ 779651SAndreas.Sandberg@ARM.compublic: 789651SAndreas.Sandberg@ARM.com 799651SAndreas.Sandberg@ARM.com HMCController(const HMCControllerParams *p); 809651SAndreas.Sandberg@ARM.com 819651SAndreas.Sandberg@ARM.comprivate: 829651SAndreas.Sandberg@ARM.com 839651SAndreas.Sandberg@ARM.com // Receive range change only on one of the ports (because they all have 8411341Sandreas.hansson@arm.com // the same range) 8511341Sandreas.hansson@arm.com virtual void recvRangeChange(PortID master_port_id); 8611341Sandreas.hansson@arm.com 879651SAndreas.Sandberg@ARM.com // Receive a request and distribute it among slave ports 8811168Sandreas.hansson@arm.com // Simply forwards the packet to the next serial link based on a 8911168Sandreas.hansson@arm.com // Round-robin counter 909651SAndreas.Sandberg@ARM.com virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id); 9111168Sandreas.hansson@arm.com 9211168Sandreas.hansson@arm.com int n_master_ports; 9311363Sandreas@sandberg.pp.se 949651SAndreas.Sandberg@ARM.com // The round-robin counter 9511341Sandreas.hansson@arm.com int rr_counter; 9611341Sandreas.hansson@arm.com /** 979651SAndreas.Sandberg@ARM.com * Function for rotating the round robin counter 9811341Sandreas.hansson@arm.com * @return the next value of the counter 999651SAndreas.Sandberg@ARM.com */ 10011341Sandreas.hansson@arm.com int rotate_counter(); 10111341Sandreas.hansson@arm.com}; 1029651SAndreas.Sandberg@ARM.com 10311168Sandreas.hansson@arm.com#endif //__MEM_HMC_CONTROLLER_HH__ 10411341Sandreas.hansson@arm.com