drampower.cc revision 11229
110431SOmar.Naji@arm.com/* 211229Sandreas.hansson@arm.com * Copyright (c) 2014 ARM Limited 310431SOmar.Naji@arm.com * All rights reserved 410431SOmar.Naji@arm.com * 510431SOmar.Naji@arm.com * The license below extends only to copyright in the software and shall 610431SOmar.Naji@arm.com * not be construed as granting a license to any other intellectual 710431SOmar.Naji@arm.com * property including but not limited to intellectual property relating 810431SOmar.Naji@arm.com * to a hardware implementation of the functionality of the software 910431SOmar.Naji@arm.com * licensed hereunder. You may use the software subject to the license 1010431SOmar.Naji@arm.com * terms below provided that you ensure that this notice is replicated 1110431SOmar.Naji@arm.com * unmodified and in its entirety in all distributions of the software, 1210431SOmar.Naji@arm.com * modified or unmodified, in source code or in binary form. 1311229Sandreas.hansson@arm.com * 1410431SOmar.Naji@arm.com * Redistribution and use in source and binary forms, with or without 1510431SOmar.Naji@arm.com * modification, are permitted provided that the following conditions are 1610431SOmar.Naji@arm.com * met: redistributions of source code must retain the above copyright 1710431SOmar.Naji@arm.com * notice, this list of conditions and the following disclaimer; 1810431SOmar.Naji@arm.com * redistributions in binary form must reproduce the above copyright 1910431SOmar.Naji@arm.com * notice, this list of conditions and the following disclaimer in the 2010431SOmar.Naji@arm.com * documentation and/or other materials provided with the distribution; 2110431SOmar.Naji@arm.com * neither the name of the copyright holders nor the names of its 2210431SOmar.Naji@arm.com * contributors may be used to endorse or promote products derived from 2310431SOmar.Naji@arm.com * this software without specific prior written permission. 2410431SOmar.Naji@arm.com * 2510431SOmar.Naji@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610431SOmar.Naji@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710431SOmar.Naji@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810431SOmar.Naji@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910431SOmar.Naji@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3011229Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110431SOmar.Naji@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210431SOmar.Naji@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310431SOmar.Naji@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3411229Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510431SOmar.Naji@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610431SOmar.Naji@arm.com * 3710431SOmar.Naji@arm.com * Authors: Omar Naji 3810431SOmar.Naji@arm.com */ 3910431SOmar.Naji@arm.com 4010431SOmar.Naji@arm.com#include "base/intmath.hh" 4110431SOmar.Naji@arm.com#include "mem/drampower.hh" 4210431SOmar.Naji@arm.com#include "sim/core.hh" 4310431SOmar.Naji@arm.com 4410431SOmar.Naji@arm.comusing namespace Data; 4510431SOmar.Naji@arm.com 4610431SOmar.Naji@arm.comDRAMPower::DRAMPower(const DRAMCtrlParams* p, bool include_io) : 4710431SOmar.Naji@arm.com powerlib(libDRAMPower(getMemSpec(p), include_io)) 4810431SOmar.Naji@arm.com{ 4910431SOmar.Naji@arm.com} 5010431SOmar.Naji@arm.com 5110431SOmar.Naji@arm.comData::MemArchitectureSpec 5210431SOmar.Naji@arm.comDRAMPower::getArchParams(const DRAMCtrlParams* p) 5310431SOmar.Naji@arm.com{ 5410431SOmar.Naji@arm.com Data::MemArchitectureSpec archSpec; 5510431SOmar.Naji@arm.com archSpec.burstLength = p->burst_length; 5610431SOmar.Naji@arm.com archSpec.nbrOfBanks = p->banks_per_rank; 5710431SOmar.Naji@arm.com // One DRAMPower instance per rank, hence set this to 1 5810431SOmar.Naji@arm.com archSpec.nbrOfRanks = 1; 5910431SOmar.Naji@arm.com archSpec.dataRate = getDataRate(p); 6010431SOmar.Naji@arm.com // For now we can ignore the number of columns and rows as they 6110431SOmar.Naji@arm.com // are not used in the power calculation. 6210431SOmar.Naji@arm.com archSpec.nbrOfColumns = 0; 6310431SOmar.Naji@arm.com archSpec.nbrOfRows = 0; 6410431SOmar.Naji@arm.com archSpec.width = p->device_bus_width; 6510431SOmar.Naji@arm.com archSpec.nbrOfBankGroups = p->bank_groups_per_rank; 6610431SOmar.Naji@arm.com archSpec.dll = p->dll; 6710431SOmar.Naji@arm.com archSpec.twoVoltageDomains = hasTwoVDD(p); 6810431SOmar.Naji@arm.com // Keep this disabled for now until the model is firmed up. 6910431SOmar.Naji@arm.com archSpec.termination = false; 7010431SOmar.Naji@arm.com return archSpec; 7110431SOmar.Naji@arm.com} 7210431SOmar.Naji@arm.com 7310431SOmar.Naji@arm.comData::MemTimingSpec 7410431SOmar.Naji@arm.comDRAMPower::getTimingParams(const DRAMCtrlParams* p) 7510431SOmar.Naji@arm.com{ 7610431SOmar.Naji@arm.com // Set the values that are used for power calculations and ignore 7710431SOmar.Naji@arm.com // the ones only used by the controller functionality in DRAMPower 7810431SOmar.Naji@arm.com 7910431SOmar.Naji@arm.com // All DRAMPower timings are in clock cycles 8010431SOmar.Naji@arm.com Data::MemTimingSpec timingSpec; 8110431SOmar.Naji@arm.com timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK); 8210431SOmar.Naji@arm.com timingSpec.RCD = divCeil(p->tRCD, p->tCK); 8310431SOmar.Naji@arm.com timingSpec.RL = divCeil(p->tCL, p->tCK); 8410431SOmar.Naji@arm.com timingSpec.RP = divCeil(p->tRP, p->tCK); 8510431SOmar.Naji@arm.com timingSpec.RFC = divCeil(p->tRFC, p->tCK); 8610431SOmar.Naji@arm.com timingSpec.RAS = divCeil(p->tRAS, p->tCK); 8710431SOmar.Naji@arm.com // Write latency is read latency - 1 cycle 8810431SOmar.Naji@arm.com // Source: B.Jacob Memory Systems Cache, DRAM, Disk 8910431SOmar.Naji@arm.com timingSpec.WL = timingSpec.RL - 1; 9010431SOmar.Naji@arm.com timingSpec.DQSCK = 0; // ignore for now 9110431SOmar.Naji@arm.com timingSpec.RTP = divCeil(p->tRTP, p->tCK); 9210431SOmar.Naji@arm.com timingSpec.WR = divCeil(p->tWR, p->tCK); 9310431SOmar.Naji@arm.com timingSpec.XP = divCeil(p->tXP, p->tCK); 9410431SOmar.Naji@arm.com timingSpec.XPDLL = divCeil(p->tXPDLL, p->tCK); 9510431SOmar.Naji@arm.com timingSpec.XS = divCeil(p->tXS, p->tCK); 9610431SOmar.Naji@arm.com timingSpec.XSDLL = divCeil(p->tXSDLL, p->tCK); 9710431SOmar.Naji@arm.com 9810431SOmar.Naji@arm.com // Clock period in ns 9910431SOmar.Naji@arm.com timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns)); 10010431SOmar.Naji@arm.com assert(timingSpec.clkPeriod != 0); 10110431SOmar.Naji@arm.com timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000; 10210431SOmar.Naji@arm.com return timingSpec; 10310431SOmar.Naji@arm.com} 10410431SOmar.Naji@arm.com 10510431SOmar.Naji@arm.comData::MemPowerSpec 10610431SOmar.Naji@arm.comDRAMPower::getPowerParams(const DRAMCtrlParams* p) 10710431SOmar.Naji@arm.com{ 10810431SOmar.Naji@arm.com // All DRAMPower currents are in mA 10910431SOmar.Naji@arm.com Data::MemPowerSpec powerSpec; 11010431SOmar.Naji@arm.com powerSpec.idd0 = p->IDD0 * 1000; 11110431SOmar.Naji@arm.com powerSpec.idd02 = p->IDD02 * 1000; 11210431SOmar.Naji@arm.com powerSpec.idd2p0 = p->IDD2P0 * 1000; 11310431SOmar.Naji@arm.com powerSpec.idd2p02 = p->IDD2P02 * 1000; 11410431SOmar.Naji@arm.com powerSpec.idd2p1 = p->IDD2P1 * 1000; 11510431SOmar.Naji@arm.com powerSpec.idd2p12 = p->IDD2P12 * 1000; 11610431SOmar.Naji@arm.com powerSpec.idd2n = p->IDD2N * 1000; 11710431SOmar.Naji@arm.com powerSpec.idd2n2 = p->IDD2N2 * 1000; 11810431SOmar.Naji@arm.com powerSpec.idd3p0 = p->IDD3P0 * 1000; 11910431SOmar.Naji@arm.com powerSpec.idd3p02 = p->IDD3P02 * 1000; 12010431SOmar.Naji@arm.com powerSpec.idd3p1 = p->IDD3P1 * 1000; 12110431SOmar.Naji@arm.com powerSpec.idd3p12 = p->IDD3P12 * 1000; 12210431SOmar.Naji@arm.com powerSpec.idd3n = p->IDD3N * 1000; 12310431SOmar.Naji@arm.com powerSpec.idd3n2 = p->IDD3N2 * 1000; 12410431SOmar.Naji@arm.com powerSpec.idd4r = p->IDD4R * 1000; 12510431SOmar.Naji@arm.com powerSpec.idd4r2 = p->IDD4R2 * 1000; 12610431SOmar.Naji@arm.com powerSpec.idd4w = p->IDD4W * 1000; 12710431SOmar.Naji@arm.com powerSpec.idd4w2 = p->IDD4W2 * 1000; 12810431SOmar.Naji@arm.com powerSpec.idd5 = p->IDD5 * 1000; 12910431SOmar.Naji@arm.com powerSpec.idd52 = p->IDD52 * 1000; 13010431SOmar.Naji@arm.com powerSpec.idd6 = p->IDD6 * 1000; 13110431SOmar.Naji@arm.com powerSpec.idd62 = p->IDD62 * 1000; 13210431SOmar.Naji@arm.com powerSpec.vdd = p->VDD; 13310431SOmar.Naji@arm.com powerSpec.vdd2 = p->VDD2; 13410431SOmar.Naji@arm.com return powerSpec; 13510431SOmar.Naji@arm.com} 13610431SOmar.Naji@arm.com 13710431SOmar.Naji@arm.comData::MemorySpecification 13810431SOmar.Naji@arm.comDRAMPower::getMemSpec(const DRAMCtrlParams* p) 13910431SOmar.Naji@arm.com{ 14010431SOmar.Naji@arm.com Data::MemorySpecification memSpec; 14110431SOmar.Naji@arm.com memSpec.memArchSpec = getArchParams(p); 14210431SOmar.Naji@arm.com memSpec.memTimingSpec = getTimingParams(p); 14310431SOmar.Naji@arm.com memSpec.memPowerSpec = getPowerParams(p); 14410431SOmar.Naji@arm.com return memSpec; 14510431SOmar.Naji@arm.com} 14610431SOmar.Naji@arm.com 14710431SOmar.Naji@arm.combool 14810431SOmar.Naji@arm.comDRAMPower::hasTwoVDD(const DRAMCtrlParams* p) 14910431SOmar.Naji@arm.com{ 15010431SOmar.Naji@arm.com return p->VDD2 == 0 ? false : true; 15110431SOmar.Naji@arm.com} 15210431SOmar.Naji@arm.com 15310431SOmar.Naji@arm.comuint8_t 15410431SOmar.Naji@arm.comDRAMPower::getDataRate(const DRAMCtrlParams* p) 15510431SOmar.Naji@arm.com{ 15610431SOmar.Naji@arm.com uint32_t burst_cycles = divCeil(p->tBURST, p->tCK); 15710431SOmar.Naji@arm.com uint8_t data_rate = p->burst_length / burst_cycles; 15810561SOmar.Naji@arm.com // 4 for GDDR5 15910561SOmar.Naji@arm.com if (data_rate != 1 && data_rate != 2 && data_rate != 4) 16010561SOmar.Naji@arm.com fatal("Got unexpected data rate %d, should be 1 or 2 or 4\n"); 16110431SOmar.Naji@arm.com return data_rate; 16210431SOmar.Naji@arm.com} 163