dram_ctrl.cc revision 9824
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 * Ani Udipi 39 */ 40 41#include "base/trace.hh" 42#include "debug/Drain.hh" 43#include "debug/DRAM.hh" 44#include "debug/DRAMWR.hh" 45#include "mem/simple_dram.hh" 46#include "sim/system.hh" 47 48using namespace std; 49 50SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) : 51 AbstractMemory(p), 52 port(name() + ".port", *this), 53 retryRdReq(false), retryWrReq(false), 54 rowHitFlag(false), stopReads(false), actTicks(p->activation_limit, 0), 55 writeEvent(this), respondEvent(this), 56 refreshEvent(this), nextReqEvent(this), drainManager(NULL), 57 bytesPerCacheLine(0), 58 linesPerRowBuffer(p->lines_per_rowbuffer), 59 ranksPerChannel(p->ranks_per_channel), 60 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 61 readBufferSize(p->read_buffer_size), 62 writeBufferSize(p->write_buffer_size), 63 writeThresholdPerc(p->write_thresh_perc), 64 tWTR(p->tWTR), tBURST(p->tBURST), 65 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), 66 tRFC(p->tRFC), tREFI(p->tREFI), 67 tXAW(p->tXAW), activationLimit(p->activation_limit), 68 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 69 pageMgmt(p->page_policy), 70 frontendLatency(p->static_frontend_latency), 71 backendLatency(p->static_backend_latency), 72 busBusyUntil(0), writeStartTime(0), 73 prevArrival(0), numReqs(0) 74{ 75 // create the bank states based on the dimensions of the ranks and 76 // banks 77 banks.resize(ranksPerChannel); 78 for (size_t c = 0; c < ranksPerChannel; ++c) { 79 banks[c].resize(banksPerRank); 80 } 81 82 // round the write threshold percent to a whole number of entries 83 // in the buffer 84 writeThreshold = writeBufferSize * writeThresholdPerc / 100.0; 85} 86 87void 88SimpleDRAM::init() 89{ 90 if (!port.isConnected()) { 91 fatal("SimpleDRAM %s is unconnected!\n", name()); 92 } else { 93 port.sendRangeChange(); 94 } 95 96 // get the burst size from the connected port as it is currently 97 // assumed to be equal to the cache line size 98 bytesPerCacheLine = _system->cacheLineSize(); 99 100 // we could deal with plenty options here, but for now do a quick 101 // sanity check 102 if (bytesPerCacheLine != 64 && bytesPerCacheLine != 32) 103 panic("Unexpected burst size %d", bytesPerCacheLine); 104 105 // determine the rows per bank by looking at the total capacity 106 uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 107 108 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 109 AbstractMemory::size()); 110 rowsPerBank = capacity / (bytesPerCacheLine * linesPerRowBuffer * 111 banksPerRank * ranksPerChannel); 112 113 if (range.interleaved()) { 114 if (channels != range.stripes()) 115 panic("%s has %d interleaved address stripes but %d channel(s)\n", 116 name(), range.stripes(), channels); 117 118 if (addrMapping == Enums::RaBaChCo) { 119 if (bytesPerCacheLine * linesPerRowBuffer != 120 range.granularity()) { 121 panic("Interleaving of %s doesn't match RaBaChCo address map\n", 122 name()); 123 } 124 } else if (addrMapping == Enums::RaBaCoCh) { 125 if (bytesPerCacheLine != range.granularity()) { 126 panic("Interleaving of %s doesn't match RaBaCoCh address map\n", 127 name()); 128 } 129 } else if (addrMapping == Enums::CoRaBaCh) { 130 if (bytesPerCacheLine != range.granularity()) 131 panic("Interleaving of %s doesn't match CoRaBaCh address map\n", 132 name()); 133 } 134 } 135} 136 137void 138SimpleDRAM::startup() 139{ 140 // print the configuration of the controller 141 printParams(); 142 143 // kick off the refresh 144 schedule(refreshEvent, curTick() + tREFI); 145} 146 147Tick 148SimpleDRAM::recvAtomic(PacketPtr pkt) 149{ 150 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 151 152 // do the actual memory access and turn the packet into a response 153 access(pkt); 154 155 Tick latency = 0; 156 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 157 // this value is not supposed to be accurate, just enough to 158 // keep things going, mimic a closed page 159 latency = tRP + tRCD + tCL; 160 } 161 return latency; 162} 163 164bool 165SimpleDRAM::readQueueFull() const 166{ 167 DPRINTF(DRAM, "Read queue limit %d current size %d\n", 168 readBufferSize, readQueue.size() + respQueue.size()); 169 170 return (readQueue.size() + respQueue.size()) == readBufferSize; 171} 172 173bool 174SimpleDRAM::writeQueueFull() const 175{ 176 DPRINTF(DRAM, "Write queue limit %d current size %d\n", 177 writeBufferSize, writeQueue.size()); 178 return writeQueue.size() == writeBufferSize; 179} 180 181SimpleDRAM::DRAMPacket* 182SimpleDRAM::decodeAddr(PacketPtr pkt) 183{ 184 // decode the address based on the address mapping scheme, with 185 // Ra, Co, Ba and Ch denoting rank, column, bank and channel, 186 // respectively 187 uint8_t rank; 188 uint16_t bank; 189 uint16_t row; 190 191 Addr addr = pkt->getAddr(); 192 193 // truncate the address to the access granularity 194 addr = addr / bytesPerCacheLine; 195 196 // we have removed the lowest order address bits that denote the 197 // position within the cache line 198 if (addrMapping == Enums::RaBaChCo) { 199 // the lowest order bits denote the column to ensure that 200 // sequential cache lines occupy the same row 201 addr = addr / linesPerRowBuffer; 202 203 // take out the channel part of the address 204 addr = addr / channels; 205 206 // after the channel bits, get the bank bits to interleave 207 // over the banks 208 bank = addr % banksPerRank; 209 addr = addr / banksPerRank; 210 211 // after the bank, we get the rank bits which thus interleaves 212 // over the ranks 213 rank = addr % ranksPerChannel; 214 addr = addr / ranksPerChannel; 215 216 // lastly, get the row bits 217 row = addr % rowsPerBank; 218 addr = addr / rowsPerBank; 219 } else if (addrMapping == Enums::RaBaCoCh) { 220 // take out the channel part of the address 221 addr = addr / channels; 222 223 // next, the column 224 addr = addr / linesPerRowBuffer; 225 226 // after the column bits, we get the bank bits to interleave 227 // over the banks 228 bank = addr % banksPerRank; 229 addr = addr / banksPerRank; 230 231 // after the bank, we get the rank bits which thus interleaves 232 // over the ranks 233 rank = addr % ranksPerChannel; 234 addr = addr / ranksPerChannel; 235 236 // lastly, get the row bits 237 row = addr % rowsPerBank; 238 addr = addr / rowsPerBank; 239 } else if (addrMapping == Enums::CoRaBaCh) { 240 // optimise for closed page mode and utilise maximum 241 // parallelism of the DRAM (at the cost of power) 242 243 // take out the channel part of the address, not that this has 244 // to match with how accesses are interleaved between the 245 // controllers in the address mapping 246 addr = addr / channels; 247 248 // start with the bank bits, as this provides the maximum 249 // opportunity for parallelism between requests 250 bank = addr % banksPerRank; 251 addr = addr / banksPerRank; 252 253 // next get the rank bits 254 rank = addr % ranksPerChannel; 255 addr = addr / ranksPerChannel; 256 257 // next the column bits which we do not need to keep track of 258 // and simply skip past 259 addr = addr / linesPerRowBuffer; 260 261 // lastly, get the row bits 262 row = addr % rowsPerBank; 263 addr = addr / rowsPerBank; 264 } else 265 panic("Unknown address mapping policy chosen!"); 266 267 assert(rank < ranksPerChannel); 268 assert(bank < banksPerRank); 269 assert(row < rowsPerBank); 270 271 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 272 pkt->getAddr(), rank, bank, row); 273 274 // create the corresponding DRAM packet with the entry time and 275 // ready time set to the current tick, the latter will be updated 276 // later 277 return new DRAMPacket(pkt, rank, bank, row, pkt->getAddr(), 278 banks[rank][bank]); 279} 280 281void 282SimpleDRAM::addToReadQueue(PacketPtr pkt) 283{ 284 // only add to the read queue here. whenever the request is 285 // eventually done, set the readyTime, and call schedule() 286 assert(!pkt->isWrite()); 287 288 // First check write buffer to see if the data is already at 289 // the controller 290 list<DRAMPacket*>::const_iterator i; 291 Addr addr = pkt->getAddr(); 292 293 // @todo: add size check 294 for (i = writeQueue.begin(); i != writeQueue.end(); ++i) { 295 if ((*i)->addr == addr){ 296 servicedByWrQ++; 297 DPRINTF(DRAM, "Read to %lld serviced by write queue\n", addr); 298 bytesRead += bytesPerCacheLine; 299 bytesConsumedRd += pkt->getSize(); 300 accessAndRespond(pkt, frontendLatency); 301 return; 302 } 303 } 304 305 DRAMPacket* dram_pkt = decodeAddr(pkt); 306 307 assert(readQueue.size() + respQueue.size() < readBufferSize); 308 rdQLenPdf[readQueue.size() + respQueue.size()]++; 309 310 DPRINTF(DRAM, "Adding to read queue\n"); 311 312 readQueue.push_back(dram_pkt); 313 314 // Update stats 315 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 316 assert(bank_id < ranksPerChannel * banksPerRank); 317 perBankRdReqs[bank_id]++; 318 319 avgRdQLen = readQueue.size() + respQueue.size(); 320 321 // If we are not already scheduled to get the read request out of 322 // the queue, do so now 323 if (!nextReqEvent.scheduled() && !stopReads) { 324 DPRINTF(DRAM, "Request scheduled immediately\n"); 325 schedule(nextReqEvent, curTick()); 326 } 327} 328 329void 330SimpleDRAM::processWriteEvent() 331{ 332 assert(!writeQueue.empty()); 333 uint32_t numWritesThisTime = 0; 334 335 DPRINTF(DRAMWR, "Beginning DRAM Writes\n"); 336 Tick temp1 M5_VAR_USED = std::max(curTick(), busBusyUntil); 337 Tick temp2 M5_VAR_USED = std::max(curTick(), maxBankFreeAt()); 338 339 // @todo: are there any dangers with the untimed while loop? 340 while (!writeQueue.empty()) { 341 if (numWritesThisTime > writeThreshold) { 342 DPRINTF(DRAMWR, "Hit write threshold %d\n", writeThreshold); 343 break; 344 } 345 346 chooseNextWrite(); 347 DRAMPacket* dram_pkt = writeQueue.front(); 348 // What's the earliest the request can be put on the bus 349 Tick schedTime = std::max(curTick(), busBusyUntil); 350 351 DPRINTF(DRAMWR, "Asking for latency estimate at %lld\n", 352 schedTime + tBURST); 353 354 pair<Tick, Tick> lat = estimateLatency(dram_pkt, schedTime + tBURST); 355 Tick accessLat = lat.second; 356 357 // look at the rowHitFlag set by estimateLatency 358 if (rowHitFlag) 359 writeRowHits++; 360 361 Bank& bank = dram_pkt->bank_ref; 362 363 if (pageMgmt == Enums::open) { 364 bank.openRow = dram_pkt->row; 365 bank.freeAt = schedTime + tBURST + std::max(accessLat, tCL); 366 busBusyUntil = bank.freeAt - tCL; 367 bank.bytesAccessed += bytesPerCacheLine; 368 369 if (!rowHitFlag) { 370 bank.tRASDoneAt = bank.freeAt + tRP; 371 recordActivate(bank.freeAt - tCL - tRCD); 372 busBusyUntil = bank.freeAt - tCL - tRCD; 373 374 // sample the number of bytes accessed and reset it as 375 // we are now closing this row 376 bytesPerActivate.sample(bank.bytesAccessed); 377 bank.bytesAccessed = 0; 378 } 379 } else if (pageMgmt == Enums::close) { 380 bank.freeAt = schedTime + tBURST + accessLat + tRP + tRP; 381 // Work backwards from bank.freeAt to determine activate time 382 recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD); 383 busBusyUntil = bank.freeAt - tRP - tRP - tCL - tRCD; 384 DPRINTF(DRAMWR, "processWriteEvent::bank.freeAt for " 385 "banks_id %d is %lld\n", 386 dram_pkt->rank * banksPerRank + dram_pkt->bank, 387 bank.freeAt); 388 bytesPerActivate.sample(bytesPerCacheLine); 389 } else 390 panic("Unknown page management policy chosen\n"); 391 392 DPRINTF(DRAMWR, "Done writing to address %lld\n", dram_pkt->addr); 393 394 DPRINTF(DRAMWR, "schedtime is %lld, tBURST is %lld, " 395 "busbusyuntil is %lld\n", 396 schedTime, tBURST, busBusyUntil); 397 398 writeQueue.pop_front(); 399 delete dram_pkt; 400 401 numWritesThisTime++; 402 } 403 404 DPRINTF(DRAMWR, "Completed %d writes, bus busy for %lld ticks,"\ 405 "banks busy for %lld ticks\n", numWritesThisTime, 406 busBusyUntil - temp1, maxBankFreeAt() - temp2); 407 408 // Update stats 409 avgWrQLen = writeQueue.size(); 410 411 // turn the bus back around for reads again 412 busBusyUntil += tWTR; 413 stopReads = false; 414 415 if (retryWrReq) { 416 retryWrReq = false; 417 port.sendRetry(); 418 } 419 420 // if there is nothing left in any queue, signal a drain 421 if (writeQueue.empty() && readQueue.empty() && 422 respQueue.empty () && drainManager) { 423 drainManager->signalDrainDone(); 424 drainManager = NULL; 425 } 426 427 // Once you're done emptying the write queue, check if there's 428 // anything in the read queue, and call schedule if required. The 429 // retry above could already have caused it to be scheduled, so 430 // first check 431 if (!nextReqEvent.scheduled()) 432 schedule(nextReqEvent, busBusyUntil); 433} 434 435void 436SimpleDRAM::triggerWrites() 437{ 438 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick()); 439 // Flag variable to stop any more read scheduling 440 stopReads = true; 441 442 writeStartTime = std::max(busBusyUntil, curTick()) + tWTR; 443 444 DPRINTF(DRAM, "Writes scheduled at %lld\n", writeStartTime); 445 446 assert(writeStartTime >= curTick()); 447 assert(!writeEvent.scheduled()); 448 schedule(writeEvent, writeStartTime); 449} 450 451void 452SimpleDRAM::addToWriteQueue(PacketPtr pkt) 453{ 454 // only add to the write queue here. whenever the request is 455 // eventually done, set the readyTime, and call schedule() 456 assert(pkt->isWrite()); 457 458 DRAMPacket* dram_pkt = decodeAddr(pkt); 459 460 assert(writeQueue.size() < writeBufferSize); 461 wrQLenPdf[writeQueue.size()]++; 462 463 DPRINTF(DRAM, "Adding to write queue\n"); 464 465 writeQueue.push_back(dram_pkt); 466 467 // Update stats 468 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 469 assert(bank_id < ranksPerChannel * banksPerRank); 470 perBankWrReqs[bank_id]++; 471 472 avgWrQLen = writeQueue.size(); 473 474 // we do not wait for the writes to be send to the actual memory, 475 // but instead take responsibility for the consistency here and 476 // snoop the write queue for any upcoming reads 477 478 bytesConsumedWr += pkt->getSize(); 479 bytesWritten += bytesPerCacheLine; 480 accessAndRespond(pkt, frontendLatency); 481 482 // If your write buffer is starting to fill up, drain it! 483 if (writeQueue.size() > writeThreshold && !stopReads){ 484 triggerWrites(); 485 } 486} 487 488void 489SimpleDRAM::printParams() const 490{ 491 // Sanity check print of important parameters 492 DPRINTF(DRAM, 493 "Memory controller %s physical organization\n" \ 494 "Bytes per cacheline %d\n" \ 495 "Lines per row buffer %d\n" \ 496 "Rows per bank %d\n" \ 497 "Banks per rank %d\n" \ 498 "Ranks per channel %d\n" \ 499 "Total mem capacity %u\n", 500 name(), bytesPerCacheLine, linesPerRowBuffer, rowsPerBank, 501 banksPerRank, ranksPerChannel, bytesPerCacheLine * 502 linesPerRowBuffer * rowsPerBank * banksPerRank * ranksPerChannel); 503 504 string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 505 string address_mapping = addrMapping == Enums::RaBaChCo ? "RaBaChCo" : 506 (addrMapping == Enums::RaBaCoCh ? "RaBaCoCh" : "CoRaBaCh"); 507 string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE"; 508 509 DPRINTF(DRAM, 510 "Memory controller %s characteristics\n" \ 511 "Read buffer size %d\n" \ 512 "Write buffer size %d\n" \ 513 "Write buffer thresh %d\n" \ 514 "Scheduler %s\n" \ 515 "Address mapping %s\n" \ 516 "Page policy %s\n", 517 name(), readBufferSize, writeBufferSize, writeThreshold, 518 scheduler, address_mapping, page_policy); 519 520 DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 521 "tRCD %d ticks\n" \ 522 "tCL %d ticks\n" \ 523 "tRP %d ticks\n" \ 524 "tBURST %d ticks\n" \ 525 "tRFC %d ticks\n" \ 526 "tREFI %d ticks\n" \ 527 "tWTR %d ticks\n" \ 528 "tXAW (%d) %d ticks\n", 529 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR, 530 activationLimit, tXAW); 531} 532 533void 534SimpleDRAM::printQs() const { 535 536 list<DRAMPacket*>::const_iterator i; 537 538 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 539 for (i = readQueue.begin() ; i != readQueue.end() ; ++i) { 540 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 541 } 542 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 543 for (i = respQueue.begin() ; i != respQueue.end() ; ++i) { 544 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 545 } 546 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 547 for (i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 548 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 549 } 550} 551 552bool 553SimpleDRAM::recvTimingReq(PacketPtr pkt) 554{ 555 /// @todo temporary hack to deal with memory corruption issues until 556 /// 4-phase transactions are complete 557 for (int x = 0; x < pendingDelete.size(); x++) 558 delete pendingDelete[x]; 559 pendingDelete.clear(); 560 561 // This is where we enter from the outside world 562 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 563 pkt->cmdString(),pkt->getAddr(), pkt->getSize()); 564 565 // simply drop inhibited packets for now 566 if (pkt->memInhibitAsserted()) { 567 DPRINTF(DRAM,"Inhibited packet -- Dropping it now\n"); 568 pendingDelete.push_back(pkt); 569 return true; 570 } 571 572 if (pkt->getSize() == bytesPerCacheLine) 573 cpuReqs++; 574 575 // Every million accesses, print the state of the queues 576 if (numReqs % 1000000 == 0) 577 printQs(); 578 579 // Calc avg gap between requests 580 if (prevArrival != 0) { 581 totGap += curTick() - prevArrival; 582 } 583 prevArrival = curTick(); 584 585 unsigned size = pkt->getSize(); 586 if (size > bytesPerCacheLine) 587 panic("Request size %d is greater than burst size %d", 588 size, bytesPerCacheLine); 589 590 // check local buffers and do not accept if full 591 if (pkt->isRead()) { 592 assert(size != 0); 593 if (readQueueFull()) { 594 DPRINTF(DRAM, "Read queue full, not accepting\n"); 595 // remember that we have to retry this port 596 retryRdReq = true; 597 numRdRetry++; 598 return false; 599 } else { 600 readPktSize[ceilLog2(size)]++; 601 addToReadQueue(pkt); 602 readReqs++; 603 numReqs++; 604 } 605 } else if (pkt->isWrite()) { 606 assert(size != 0); 607 if (writeQueueFull()) { 608 DPRINTF(DRAM, "Write queue full, not accepting\n"); 609 // remember that we have to retry this port 610 retryWrReq = true; 611 numWrRetry++; 612 return false; 613 } else { 614 writePktSize[ceilLog2(size)]++; 615 addToWriteQueue(pkt); 616 writeReqs++; 617 numReqs++; 618 } 619 } else { 620 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 621 neitherReadNorWrite++; 622 accessAndRespond(pkt, 1); 623 } 624 625 retryRdReq = false; 626 retryWrReq = false; 627 return true; 628} 629 630void 631SimpleDRAM::processRespondEvent() 632{ 633 DPRINTF(DRAM, 634 "processRespondEvent(): Some req has reached its readyTime\n"); 635 636 PacketPtr pkt = respQueue.front()->pkt; 637 638 // Actually responds to the requestor 639 bytesConsumedRd += pkt->getSize(); 640 bytesRead += bytesPerCacheLine; 641 accessAndRespond(pkt, frontendLatency + backendLatency); 642 643 delete respQueue.front(); 644 respQueue.pop_front(); 645 646 // Update stats 647 avgRdQLen = readQueue.size() + respQueue.size(); 648 649 if (!respQueue.empty()) { 650 assert(respQueue.front()->readyTime >= curTick()); 651 assert(!respondEvent.scheduled()); 652 schedule(respondEvent, respQueue.front()->readyTime); 653 } else { 654 // if there is nothing left in any queue, signal a drain 655 if (writeQueue.empty() && readQueue.empty() && 656 drainManager) { 657 drainManager->signalDrainDone(); 658 drainManager = NULL; 659 } 660 } 661 662 // We have made a location in the queue available at this point, 663 // so if there is a read that was forced to wait, retry now 664 if (retryRdReq) { 665 retryRdReq = false; 666 port.sendRetry(); 667 } 668} 669 670void 671SimpleDRAM::chooseNextWrite() 672{ 673 // This method does the arbitration between write requests. The 674 // chosen packet is simply moved to the head of the write 675 // queue. The other methods know that this is the place to 676 // look. For example, with FCFS, this method does nothing 677 assert(!writeQueue.empty()); 678 679 if (writeQueue.size() == 1) { 680 DPRINTF(DRAMWR, "Single write request, nothing to do\n"); 681 return; 682 } 683 684 if (memSchedPolicy == Enums::fcfs) { 685 // Do nothing, since the correct request is already head 686 } else if (memSchedPolicy == Enums::frfcfs) { 687 list<DRAMPacket*>::iterator i = writeQueue.begin(); 688 bool foundRowHit = false; 689 while (!foundRowHit && i != writeQueue.end()) { 690 DRAMPacket* dram_pkt = *i; 691 const Bank& bank = dram_pkt->bank_ref; 692 if (bank.openRow == dram_pkt->row) { //FR part 693 DPRINTF(DRAMWR, "Write row buffer hit\n"); 694 writeQueue.erase(i); 695 writeQueue.push_front(dram_pkt); 696 foundRowHit = true; 697 } else { //FCFS part 698 ; 699 } 700 ++i; 701 } 702 } else 703 panic("No scheduling policy chosen\n"); 704 705 DPRINTF(DRAMWR, "Selected next write request\n"); 706} 707 708bool 709SimpleDRAM::chooseNextRead() 710{ 711 // This method does the arbitration between read requests. The 712 // chosen packet is simply moved to the head of the queue. The 713 // other methods know that this is the place to look. For example, 714 // with FCFS, this method does nothing 715 if (readQueue.empty()) { 716 DPRINTF(DRAM, "No read request to select\n"); 717 return false; 718 } 719 720 // If there is only one request then there is nothing left to do 721 if (readQueue.size() == 1) 722 return true; 723 724 if (memSchedPolicy == Enums::fcfs) { 725 // Do nothing, since the request to serve is already the first 726 // one in the read queue 727 } else if (memSchedPolicy == Enums::frfcfs) { 728 for (list<DRAMPacket*>::iterator i = readQueue.begin(); 729 i != readQueue.end() ; ++i) { 730 DRAMPacket* dram_pkt = *i; 731 const Bank& bank = dram_pkt->bank_ref; 732 // Check if it is a row hit 733 if (bank.openRow == dram_pkt->row) { //FR part 734 DPRINTF(DRAM, "Row buffer hit\n"); 735 readQueue.erase(i); 736 readQueue.push_front(dram_pkt); 737 break; 738 } else { //FCFS part 739 ; 740 } 741 } 742 } else 743 panic("No scheduling policy chosen!\n"); 744 745 DPRINTF(DRAM, "Selected next read request\n"); 746 return true; 747} 748 749void 750SimpleDRAM::accessAndRespond(PacketPtr pkt, Tick static_latency) 751{ 752 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 753 754 bool needsResponse = pkt->needsResponse(); 755 // do the actual memory access which also turns the packet into a 756 // response 757 access(pkt); 758 759 // turn packet around to go back to requester if response expected 760 if (needsResponse) { 761 // access already turned the packet into a response 762 assert(pkt->isResponse()); 763 764 // @todo someone should pay for this 765 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 766 767 // queue the packet in the response queue to be sent out after 768 // the static latency has passed 769 port.schedTimingResp(pkt, curTick() + static_latency); 770 } else { 771 // @todo the packet is going to be deleted, and the DRAMPacket 772 // is still having a pointer to it 773 pendingDelete.push_back(pkt); 774 } 775 776 DPRINTF(DRAM, "Done\n"); 777 778 return; 779} 780 781pair<Tick, Tick> 782SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 783{ 784 // If a request reaches a bank at tick 'inTime', how much time 785 // *after* that does it take to finish the request, depending 786 // on bank status and page open policy. Note that this method 787 // considers only the time taken for the actual read or write 788 // to complete, NOT any additional time thereafter for tRAS or 789 // tRP. 790 Tick accLat = 0; 791 Tick bankLat = 0; 792 rowHitFlag = false; 793 794 const Bank& bank = dram_pkt->bank_ref; 795 if (pageMgmt == Enums::open) { // open-page policy 796 if (bank.openRow == dram_pkt->row) { 797 // When we have a row-buffer hit, 798 // we don't care about tRAS having expired or not, 799 // but do care about bank being free for access 800 rowHitFlag = true; 801 802 if (bank.freeAt < inTime) { 803 // CAS latency only 804 accLat += tCL; 805 bankLat += tCL; 806 } else { 807 accLat += 0; 808 bankLat += 0; 809 } 810 811 } else { 812 // Row-buffer miss, need to close existing row 813 // once tRAS has expired, then open the new one, 814 // then add cas latency. 815 Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 816 817 if (freeTime > inTime) 818 accLat += freeTime - inTime; 819 820 accLat += tRP + tRCD + tCL; 821 bankLat += tRP + tRCD + tCL; 822 } 823 } else if (pageMgmt == Enums::close) { 824 // With a close page policy, no notion of 825 // bank.tRASDoneAt 826 if (bank.freeAt > inTime) 827 accLat += bank.freeAt - inTime; 828 829 // page already closed, simply open the row, and 830 // add cas latency 831 accLat += tRCD + tCL; 832 bankLat += tRCD + tCL; 833 } else 834 panic("No page management policy chosen\n"); 835 836 DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n", 837 bankLat, accLat); 838 839 return make_pair(bankLat, accLat); 840} 841 842void 843SimpleDRAM::processNextReqEvent() 844{ 845 scheduleNextReq(); 846} 847 848void 849SimpleDRAM::recordActivate(Tick act_tick) 850{ 851 assert(actTicks.size() == activationLimit); 852 853 DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 854 855 // if the activation limit is disabled then we are done 856 if (actTicks.empty()) 857 return; 858 859 // sanity check 860 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 861 panic("Got %d activates in window %d (%d - %d) which is smaller " 862 "than %d\n", activationLimit, act_tick - actTicks.back(), 863 act_tick, actTicks.back(), tXAW); 864 } 865 866 // shift the times used for the book keeping, the last element 867 // (highest index) is the oldest one and hence the lowest value 868 actTicks.pop_back(); 869 870 // record an new activation (in the future) 871 actTicks.push_front(act_tick); 872 873 // cannot activate more than X times in time window tXAW, push the 874 // next one (the X + 1'st activate) to be tXAW away from the 875 // oldest in our window of X 876 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 877 DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 878 "than %d\n", activationLimit, actTicks.back() + tXAW); 879 for(int i = 0; i < ranksPerChannel; i++) 880 for(int j = 0; j < banksPerRank; j++) 881 // next activate must not happen before end of window 882 banks[i][j].freeAt = std::max(banks[i][j].freeAt, 883 actTicks.back() + tXAW); 884 } 885} 886 887void 888SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) 889{ 890 891 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 892 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 893 894 // estimate the bank and access latency 895 pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 896 Tick bankLat = lat.first; 897 Tick accessLat = lat.second; 898 899 // This request was woken up at this time based on a prior call 900 // to estimateLatency(). However, between then and now, both the 901 // accessLatency and/or busBusyUntil may have changed. We need 902 // to correct for that. 903 904 Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 905 busBusyUntil - (curTick() + accessLat) : 0; 906 907 Bank& bank = dram_pkt->bank_ref; 908 909 // Update bank state 910 if (pageMgmt == Enums::open) { 911 bank.openRow = dram_pkt->row; 912 bank.freeAt = curTick() + addDelay + accessLat; 913 bank.bytesAccessed += bytesPerCacheLine; 914 915 // If you activated a new row do to this access, the next access 916 // will have to respect tRAS for this bank. Assume tRAS ~= 3 * tRP. 917 // Also need to account for t_XAW 918 if (!rowHitFlag) { 919 bank.tRASDoneAt = bank.freeAt + tRP; 920 recordActivate(bank.freeAt - tCL - tRCD); //since this is open page, 921 //no tRP by default 922 // sample the number of bytes accessed and reset it as 923 // we are now closing this row 924 bytesPerActivate.sample(bank.bytesAccessed); 925 bank.bytesAccessed = 0; 926 } 927 } else if (pageMgmt == Enums::close) { // accounting for tRAS also 928 // assuming that tRAS ~= 3 * tRP, and tRC ~= 4 * tRP, as is common 929 // (refer Jacob/Ng/Wang and Micron datasheets) 930 bank.freeAt = curTick() + addDelay + accessLat + tRP + tRP; 931 recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD); //essentially (freeAt - tRC) 932 DPRINTF(DRAM,"doDRAMAccess::bank.freeAt is %lld\n",bank.freeAt); 933 bytesPerActivate.sample(bytesPerCacheLine); 934 } else 935 panic("No page management policy chosen\n"); 936 937 // Update request parameters 938 dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 939 940 941 DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 942 "readytime is %lld busbusyuntil is %lld. " \ 943 "Scheduling at readyTime\n", dram_pkt->addr, 944 curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 945 946 // Make sure requests are not overlapping on the databus 947 assert (dram_pkt->readyTime - busBusyUntil >= tBURST); 948 949 // Update bus state 950 busBusyUntil = dram_pkt->readyTime; 951 952 DPRINTF(DRAM,"Access time is %lld\n", 953 dram_pkt->readyTime - dram_pkt->entryTime); 954 955 // Update stats 956 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 957 totBankLat += bankLat; 958 totBusLat += tBURST; 959 totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - tBURST; 960 961 if (rowHitFlag) 962 readRowHits++; 963 964 // At this point we're done dealing with the request 965 // It will be moved to a separate response queue with a 966 // correct readyTime, and eventually be sent back at that 967 //time 968 moveToRespQ(); 969 970 // The absolute soonest you have to start thinking about the 971 // next request is the longest access time that can occur before 972 // busBusyUntil. Assuming you need to meet tRAS, then precharge, 973 // open a new row, and access, it is ~4*tRCD. 974 975 976 Tick newTime = (busBusyUntil > 4 * tRCD) ? 977 std::max(busBusyUntil - 4 * tRCD, curTick()) : 978 curTick(); 979 980 if (!nextReqEvent.scheduled() && !stopReads){ 981 schedule(nextReqEvent, newTime); 982 } else { 983 if (newTime < nextReqEvent.when()) 984 reschedule(nextReqEvent, newTime); 985 } 986 987 988} 989 990void 991SimpleDRAM::moveToRespQ() 992{ 993 // Remove from read queue 994 DRAMPacket* dram_pkt = readQueue.front(); 995 readQueue.pop_front(); 996 997 // Insert into response queue sorted by readyTime 998 // It will be sent back to the requestor at its 999 // readyTime 1000 if (respQueue.empty()) { 1001 respQueue.push_front(dram_pkt); 1002 assert(!respondEvent.scheduled()); 1003 assert(dram_pkt->readyTime >= curTick()); 1004 schedule(respondEvent, dram_pkt->readyTime); 1005 } else { 1006 bool done = false; 1007 list<DRAMPacket*>::iterator i = respQueue.begin(); 1008 while (!done && i != respQueue.end()) { 1009 if ((*i)->readyTime > dram_pkt->readyTime) { 1010 respQueue.insert(i, dram_pkt); 1011 done = true; 1012 } 1013 ++i; 1014 } 1015 1016 if (!done) 1017 respQueue.push_back(dram_pkt); 1018 1019 assert(respondEvent.scheduled()); 1020 1021 if (respQueue.front()->readyTime < respondEvent.when()) { 1022 assert(respQueue.front()->readyTime >= curTick()); 1023 reschedule(respondEvent, respQueue.front()->readyTime); 1024 } 1025 } 1026} 1027 1028void 1029SimpleDRAM::scheduleNextReq() 1030{ 1031 DPRINTF(DRAM, "Reached scheduleNextReq()\n"); 1032 1033 // Figure out which read request goes next, and move it to the 1034 // front of the read queue 1035 if (!chooseNextRead()) { 1036 // In the case there is no read request to go next, see if we 1037 // are asked to drain, and if so trigger writes, this also 1038 // ensures that if we hit the write limit we will do this 1039 // multiple times until we are completely drained 1040 if (drainManager && !writeQueue.empty() && !writeEvent.scheduled()) 1041 triggerWrites(); 1042 } else { 1043 doDRAMAccess(readQueue.front()); 1044 } 1045} 1046 1047Tick 1048SimpleDRAM::maxBankFreeAt() const 1049{ 1050 Tick banksFree = 0; 1051 1052 for(int i = 0; i < ranksPerChannel; i++) 1053 for(int j = 0; j < banksPerRank; j++) 1054 banksFree = std::max(banks[i][j].freeAt, banksFree); 1055 1056 return banksFree; 1057} 1058 1059void 1060SimpleDRAM::processRefreshEvent() 1061{ 1062 DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick()); 1063 1064 Tick banksFree = std::max(curTick(), maxBankFreeAt()) + tRFC; 1065 1066 for(int i = 0; i < ranksPerChannel; i++) 1067 for(int j = 0; j < banksPerRank; j++) 1068 banks[i][j].freeAt = banksFree; 1069 1070 schedule(refreshEvent, curTick() + tREFI); 1071} 1072 1073void 1074SimpleDRAM::regStats() 1075{ 1076 using namespace Stats; 1077 1078 AbstractMemory::regStats(); 1079 1080 readReqs 1081 .name(name() + ".readReqs") 1082 .desc("Total number of read requests seen"); 1083 1084 writeReqs 1085 .name(name() + ".writeReqs") 1086 .desc("Total number of write requests seen"); 1087 1088 servicedByWrQ 1089 .name(name() + ".servicedByWrQ") 1090 .desc("Number of read reqs serviced by write Q"); 1091 1092 cpuReqs 1093 .name(name() + ".cpureqs") 1094 .desc("Reqs generatd by CPU via cache - shady"); 1095 1096 neitherReadNorWrite 1097 .name(name() + ".neitherReadNorWrite") 1098 .desc("Reqs where no action is needed"); 1099 1100 perBankRdReqs 1101 .init(banksPerRank * ranksPerChannel) 1102 .name(name() + ".perBankRdReqs") 1103 .desc("Track reads on a per bank basis"); 1104 1105 perBankWrReqs 1106 .init(banksPerRank * ranksPerChannel) 1107 .name(name() + ".perBankWrReqs") 1108 .desc("Track writes on a per bank basis"); 1109 1110 avgRdQLen 1111 .name(name() + ".avgRdQLen") 1112 .desc("Average read queue length over time") 1113 .precision(2); 1114 1115 avgWrQLen 1116 .name(name() + ".avgWrQLen") 1117 .desc("Average write queue length over time") 1118 .precision(2); 1119 1120 totQLat 1121 .name(name() + ".totQLat") 1122 .desc("Total cycles spent in queuing delays"); 1123 1124 totBankLat 1125 .name(name() + ".totBankLat") 1126 .desc("Total cycles spent in bank access"); 1127 1128 totBusLat 1129 .name(name() + ".totBusLat") 1130 .desc("Total cycles spent in databus access"); 1131 1132 totMemAccLat 1133 .name(name() + ".totMemAccLat") 1134 .desc("Sum of mem lat for all requests"); 1135 1136 avgQLat 1137 .name(name() + ".avgQLat") 1138 .desc("Average queueing delay per request") 1139 .precision(2); 1140 1141 avgQLat = totQLat / (readReqs - servicedByWrQ); 1142 1143 avgBankLat 1144 .name(name() + ".avgBankLat") 1145 .desc("Average bank access latency per request") 1146 .precision(2); 1147 1148 avgBankLat = totBankLat / (readReqs - servicedByWrQ); 1149 1150 avgBusLat 1151 .name(name() + ".avgBusLat") 1152 .desc("Average bus latency per request") 1153 .precision(2); 1154 1155 avgBusLat = totBusLat / (readReqs - servicedByWrQ); 1156 1157 avgMemAccLat 1158 .name(name() + ".avgMemAccLat") 1159 .desc("Average memory access latency") 1160 .precision(2); 1161 1162 avgMemAccLat = totMemAccLat / (readReqs - servicedByWrQ); 1163 1164 numRdRetry 1165 .name(name() + ".numRdRetry") 1166 .desc("Number of times rd buffer was full causing retry"); 1167 1168 numWrRetry 1169 .name(name() + ".numWrRetry") 1170 .desc("Number of times wr buffer was full causing retry"); 1171 1172 readRowHits 1173 .name(name() + ".readRowHits") 1174 .desc("Number of row buffer hits during reads"); 1175 1176 writeRowHits 1177 .name(name() + ".writeRowHits") 1178 .desc("Number of row buffer hits during writes"); 1179 1180 readRowHitRate 1181 .name(name() + ".readRowHitRate") 1182 .desc("Row buffer hit rate for reads") 1183 .precision(2); 1184 1185 readRowHitRate = (readRowHits / (readReqs - servicedByWrQ)) * 100; 1186 1187 writeRowHitRate 1188 .name(name() + ".writeRowHitRate") 1189 .desc("Row buffer hit rate for writes") 1190 .precision(2); 1191 1192 writeRowHitRate = (writeRowHits / writeReqs) * 100; 1193 1194 readPktSize 1195 .init(ceilLog2(bytesPerCacheLine) + 1) 1196 .name(name() + ".readPktSize") 1197 .desc("Categorize read packet sizes"); 1198 1199 writePktSize 1200 .init(ceilLog2(bytesPerCacheLine) + 1) 1201 .name(name() + ".writePktSize") 1202 .desc("Categorize write packet sizes"); 1203 1204 rdQLenPdf 1205 .init(readBufferSize) 1206 .name(name() + ".rdQLenPdf") 1207 .desc("What read queue length does an incoming req see"); 1208 1209 wrQLenPdf 1210 .init(writeBufferSize) 1211 .name(name() + ".wrQLenPdf") 1212 .desc("What write queue length does an incoming req see"); 1213 1214 bytesPerActivate 1215 .init(bytesPerCacheLine * linesPerRowBuffer) 1216 .name(name() + ".bytesPerActivate") 1217 .desc("Bytes accessed per row activation") 1218 .flags(nozero); 1219 1220 bytesRead 1221 .name(name() + ".bytesRead") 1222 .desc("Total number of bytes read from memory"); 1223 1224 bytesWritten 1225 .name(name() + ".bytesWritten") 1226 .desc("Total number of bytes written to memory"); 1227 1228 bytesConsumedRd 1229 .name(name() + ".bytesConsumedRd") 1230 .desc("bytesRead derated as per pkt->getSize()"); 1231 1232 bytesConsumedWr 1233 .name(name() + ".bytesConsumedWr") 1234 .desc("bytesWritten derated as per pkt->getSize()"); 1235 1236 avgRdBW 1237 .name(name() + ".avgRdBW") 1238 .desc("Average achieved read bandwidth in MB/s") 1239 .precision(2); 1240 1241 avgRdBW = (bytesRead / 1000000) / simSeconds; 1242 1243 avgWrBW 1244 .name(name() + ".avgWrBW") 1245 .desc("Average achieved write bandwidth in MB/s") 1246 .precision(2); 1247 1248 avgWrBW = (bytesWritten / 1000000) / simSeconds; 1249 1250 avgConsumedRdBW 1251 .name(name() + ".avgConsumedRdBW") 1252 .desc("Average consumed read bandwidth in MB/s") 1253 .precision(2); 1254 1255 avgConsumedRdBW = (bytesConsumedRd / 1000000) / simSeconds; 1256 1257 avgConsumedWrBW 1258 .name(name() + ".avgConsumedWrBW") 1259 .desc("Average consumed write bandwidth in MB/s") 1260 .precision(2); 1261 1262 avgConsumedWrBW = (bytesConsumedWr / 1000000) / simSeconds; 1263 1264 peakBW 1265 .name(name() + ".peakBW") 1266 .desc("Theoretical peak bandwidth in MB/s") 1267 .precision(2); 1268 1269 peakBW = (SimClock::Frequency / tBURST) * bytesPerCacheLine / 1000000; 1270 1271 busUtil 1272 .name(name() + ".busUtil") 1273 .desc("Data bus utilization in percentage") 1274 .precision(2); 1275 1276 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 1277 1278 totGap 1279 .name(name() + ".totGap") 1280 .desc("Total gap between requests"); 1281 1282 avgGap 1283 .name(name() + ".avgGap") 1284 .desc("Average gap between requests") 1285 .precision(2); 1286 1287 avgGap = totGap / (readReqs + writeReqs); 1288} 1289 1290void 1291SimpleDRAM::recvFunctional(PacketPtr pkt) 1292{ 1293 // rely on the abstract memory 1294 functionalAccess(pkt); 1295} 1296 1297BaseSlavePort& 1298SimpleDRAM::getSlavePort(const string &if_name, PortID idx) 1299{ 1300 if (if_name != "port") { 1301 return MemObject::getSlavePort(if_name, idx); 1302 } else { 1303 return port; 1304 } 1305} 1306 1307unsigned int 1308SimpleDRAM::drain(DrainManager *dm) 1309{ 1310 unsigned int count = port.drain(dm); 1311 1312 // if there is anything in any of our internal queues, keep track 1313 // of that as well 1314 if (!(writeQueue.empty() && readQueue.empty() && 1315 respQueue.empty())) { 1316 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 1317 " resp: %d\n", writeQueue.size(), readQueue.size(), 1318 respQueue.size()); 1319 ++count; 1320 drainManager = dm; 1321 // the only part that is not drained automatically over time 1322 // is the write queue, thus trigger writes if there are any 1323 // waiting and no reads waiting, otherwise wait until the 1324 // reads are done 1325 if (readQueue.empty() && !writeQueue.empty() && 1326 !writeEvent.scheduled()) 1327 triggerWrites(); 1328 } 1329 1330 if (count) 1331 setDrainState(Drainable::Draining); 1332 else 1333 setDrainState(Drainable::Drained); 1334 return count; 1335} 1336 1337SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory) 1338 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 1339 memory(_memory) 1340{ } 1341 1342AddrRangeList 1343SimpleDRAM::MemoryPort::getAddrRanges() const 1344{ 1345 AddrRangeList ranges; 1346 ranges.push_back(memory.getAddrRange()); 1347 return ranges; 1348} 1349 1350void 1351SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt) 1352{ 1353 pkt->pushLabel(memory.name()); 1354 1355 if (!queue.checkFunctional(pkt)) { 1356 // Default implementation of SimpleTimingPort::recvFunctional() 1357 // calls recvAtomic() and throws away the latency; we can save a 1358 // little here by just not calculating the latency. 1359 memory.recvFunctional(pkt); 1360 } 1361 1362 pkt->popLabel(); 1363} 1364 1365Tick 1366SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt) 1367{ 1368 return memory.recvAtomic(pkt); 1369} 1370 1371bool 1372SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt) 1373{ 1374 // pass it to the memory controller 1375 return memory.recvTimingReq(pkt); 1376} 1377 1378SimpleDRAM* 1379SimpleDRAMParams::create() 1380{ 1381 return new SimpleDRAM(this); 1382} 1383