dram_ctrl.cc revision 9566
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 * Ani Udipi 39 */ 40 41#include "base/trace.hh" 42#include "debug/Drain.hh" 43#include "debug/DRAM.hh" 44#include "debug/DRAMWR.hh" 45#include "mem/simple_dram.hh" 46#include "sim/stat_control.hh" 47 48using namespace std; 49 50SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) : 51 AbstractMemory(p), 52 port(name() + ".port", *this), 53 retryRdReq(false), retryWrReq(false), 54 rowHitFlag(false), stopReads(false), actTicks(p->activation_limit, 0), 55 writeEvent(this), respondEvent(this), 56 refreshEvent(this), nextReqEvent(this), drainManager(NULL), 57 bytesPerCacheLine(0), 58 linesPerRowBuffer(p->lines_per_rowbuffer), 59 ranksPerChannel(p->ranks_per_channel), 60 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 61 readBufferSize(p->read_buffer_size), 62 writeBufferSize(p->write_buffer_size), 63 writeThresholdPerc(p->write_thresh_perc), 64 tWTR(p->tWTR), tBURST(p->tBURST), 65 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), 66 tRFC(p->tRFC), tREFI(p->tREFI), 67 tXAW(p->tXAW), activationLimit(p->activation_limit), 68 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 69 pageMgmt(p->page_policy), 70 busBusyUntil(0), prevdramaccess(0), writeStartTime(0), 71 prevArrival(0), numReqs(0) 72{ 73 // create the bank states based on the dimensions of the ranks and 74 // banks 75 banks.resize(ranksPerChannel); 76 for (size_t c = 0; c < ranksPerChannel; ++c) { 77 banks[c].resize(banksPerRank); 78 } 79 80 // round the write threshold percent to a whole number of entries 81 // in the buffer 82 writeThreshold = writeBufferSize * writeThresholdPerc / 100.0; 83} 84 85void 86SimpleDRAM::init() 87{ 88 if (!port.isConnected()) { 89 fatal("SimpleDRAM %s is unconnected!\n", name()); 90 } else { 91 port.sendRangeChange(); 92 } 93 94 // get the cache line size from the connected port 95 bytesPerCacheLine = port.peerBlockSize(); 96 97 // we could deal with plenty options here, but for now do a quick 98 // sanity check 99 if (bytesPerCacheLine != 64 && bytesPerCacheLine != 32) 100 panic("Unexpected cache line size %d", bytesPerCacheLine); 101 102 // determine the rows per bank by looking at the total capacity 103 uint64_t capacity = AbstractMemory::size(); 104 uint64_t i = 1; 105 while (i < 64 && capacity > ((1 << i))) { 106 ++i; 107 } 108 109 // rounded up to nearest power of two 110 DPRINTF(DRAM, "i is %lld\n", i); 111 capacity = 1 << i; 112 113 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 114 AbstractMemory::size()); 115 rowsPerBank = capacity / (bytesPerCacheLine * linesPerRowBuffer * 116 banksPerRank * ranksPerChannel); 117 118 if (range.interleaved()) { 119 if (channels != range.stripes()) 120 panic("%s has %d interleaved address stripes but %d channel(s)\n", 121 name(), range.stripes(), channels); 122 123 if (addrMapping == Enums::openmap) { 124 if (bytesPerCacheLine * linesPerRowBuffer != 125 range.granularity()) { 126 panic("Interleaving of %s doesn't match open address map\n", 127 name()); 128 } 129 } else if (addrMapping == Enums::closemap) { 130 if (bytesPerCacheLine != range.granularity()) 131 panic("Interleaving of %s doesn't match closed address map\n", 132 name()); 133 } 134 } 135} 136 137void 138SimpleDRAM::startup() 139{ 140 // print the configuration of the controller 141 printParams(); 142 143 // kick off the refresh 144 schedule(&refreshEvent, curTick() + tREFI); 145} 146 147 148Tick 149SimpleDRAM::recvAtomic(PacketPtr pkt) 150{ 151 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 152 153 // do the actual memory access and turn the packet into a response 154 access(pkt); 155 156 Tick latency = 0; 157 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 158 // this value is not supposed to be accurate, just enough to 159 // keep things going, mimic a closed page 160 latency = tRP + tRCD + tCL; 161 } 162 return latency; 163} 164 165bool 166SimpleDRAM::readQueueFull() const 167{ 168 DPRINTF(DRAM, "Read queue limit %d current size %d\n", 169 readBufferSize, dramReadQueue.size() + dramRespQueue.size()); 170 171 return (dramReadQueue.size() + dramRespQueue.size()) == readBufferSize; 172} 173 174bool 175SimpleDRAM::writeQueueFull() const 176{ 177 DPRINTF(DRAM, "Write queue limit %d current size %d\n", 178 writeBufferSize, dramWriteQueue.size()); 179 return dramWriteQueue.size() == writeBufferSize; 180} 181 182 183SimpleDRAM::DRAMPacket* 184SimpleDRAM::decodeAddr(PacketPtr pkt) 185{ 186 // decode the address based on the address mapping scheme 187 // 188 // with R, C, B and K denoting rank, column, bank and rank, 189 // respectively, and going from MSB to LSB, the two schemes are 190 // RKBC (openmap) and RCKB (closedmap) 191 uint8_t rank; 192 uint16_t bank; 193 uint16_t row; 194 195 Addr addr = pkt->getAddr(); 196 Addr temp = addr; 197 198 // truncate the address to the access granularity 199 addr = addr / bytesPerCacheLine; 200 201 // we have removed the lowest order address bits that denote the 202 // position within the cache line, proceed and select the 203 // appropriate bits for bank, rank and row (no column address is 204 // needed) 205 if (addrMapping == Enums::openmap) { 206 // the lowest order bits denote the column to ensure that 207 // sequential cache lines occupy the same row 208 addr = addr / linesPerRowBuffer; 209 210 // take out the channel part of the address, note that this has 211 // to match with how accesses are interleaved between the 212 // controllers in the address mapping 213 addr = addr / channels; 214 215 // after the column bits, we get the bank bits to interleave 216 // over the banks 217 bank = addr % banksPerRank; 218 addr = addr / banksPerRank; 219 220 // after the bank, we get the rank bits which thus interleaves 221 // over the ranks 222 rank = addr % ranksPerChannel; 223 addr = addr / ranksPerChannel; 224 225 // lastly, get the row bits 226 row = addr % rowsPerBank; 227 addr = addr / rowsPerBank; 228 } else if (addrMapping == Enums::closemap) { 229 // optimise for closed page mode and utilise maximum 230 // parallelism of the DRAM (at the cost of power) 231 232 // take out the channel part of the address, not that this has 233 // to match with how accesses are interleaved between the 234 // controllers in the address mapping 235 addr = addr / channels; 236 237 // start with the bank bits, as this provides the maximum 238 // opportunity for parallelism between requests 239 bank = addr % banksPerRank; 240 addr = addr / banksPerRank; 241 242 // next get the rank bits 243 rank = addr % ranksPerChannel; 244 addr = addr / ranksPerChannel; 245 246 // next the column bits which we do not need to keep track of 247 // and simply skip past 248 addr = addr / linesPerRowBuffer; 249 250 // lastly, get the row bits 251 row = addr % rowsPerBank; 252 addr = addr / rowsPerBank; 253 } else 254 panic("Unknown address mapping policy chosen!"); 255 256 assert(rank < ranksPerChannel); 257 assert(bank < banksPerRank); 258 assert(row < rowsPerBank); 259 260 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 261 temp, rank, bank, row); 262 263 // create the corresponding DRAM packet with the entry time and 264 // ready time set to the current tick, they will be updated later 265 DRAMPacket* dram_pkt = new DRAMPacket(pkt, rank, bank, row, temp, 266 banks[rank][bank]); 267 268 return dram_pkt; 269} 270 271void 272SimpleDRAM::addToReadQueue(PacketPtr pkt) 273{ 274 // only add to the read queue here. whenever the request is 275 // eventually done, set the readyTime, and call schedule() 276 assert(!pkt->isWrite()); 277 278 // First check write buffer to see if the data is already at 279 // the controller 280 std::list<DRAMPacket*>::const_iterator i; 281 Addr addr = pkt->getAddr(); 282 283 // @todo: add size check 284 for (i = dramWriteQueue.begin(); i != dramWriteQueue.end(); ++i) { 285 if ((*i)->addr == addr){ 286 servicedByWrQ++; 287 DPRINTF(DRAM,"Serviced by write Q\n"); 288 bytesRead += bytesPerCacheLine; 289 bytesConsumedRd += pkt->getSize(); 290 accessAndRespond(pkt); 291 return; 292 } 293 } 294 295 DRAMPacket* dram_pkt = decodeAddr(pkt); 296 297 assert(dramReadQueue.size() + dramRespQueue.size() < readBufferSize); 298 rdQLenPdf[dramReadQueue.size() + dramRespQueue.size()]++; 299 300 DPRINTF(DRAM, "Adding to read queue\n"); 301 302 dramReadQueue.push_back(dram_pkt); 303 304 // Update stats 305 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 306 assert(bank_id < ranksPerChannel * banksPerRank); 307 perBankRdReqs[bank_id]++; 308 309 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 310 311 // Special case where no arbitration is required between requests 312 if (!nextReqEvent.scheduled() && !stopReads) { 313 DPRINTF(DRAM, "Request %lld - need to schedule immediately"); 314 schedule(&nextReqEvent, curTick() + 1); 315 } 316} 317 318void 319SimpleDRAM::processWriteEvent() 320{ 321 assert(!dramWriteQueue.empty()); 322 uint32_t numWritesThisTime = 0; 323 324 DPRINTF(DRAMWR, "Beginning DRAM Writes\n"); 325 Tick temp1 M5_VAR_USED = std::max(curTick(), busBusyUntil); 326 Tick temp2 M5_VAR_USED = std::max(curTick(), maxBankFreeAt()); 327 328 // @todo: are there any dangers with the untimed while loop? 329 while (!dramWriteQueue.empty()) { 330 if (numWritesThisTime > writeThreshold) 331 break; 332 333 chooseNextWrite(); 334 DRAMPacket* dram_pkt = dramWriteQueue.front(); 335 // What's the earlier the request can be put on the bus 336 Tick schedTime = std::max(curTick(), busBusyUntil); 337 338 DPRINTF(DRAMWR, "Asking for latency estimate at %lld\n", 339 schedTime + tBURST); 340 341 pair<Tick, Tick> lat = estimateLatency(dram_pkt, schedTime + tBURST); 342 Tick accessLat = lat.second; 343 344 // look at the rowHitFlag set by estimateLatency 345 346 // @todo: Race condition here where another packet gives rise 347 // to another call to estimateLatency in the meanwhile? 348 if (rowHitFlag) 349 writeRowHits++; 350 351 Bank& bank = dram_pkt->bank_ref; 352 353 if (pageMgmt == Enums::open) { 354 bank.openRow = dram_pkt->row; 355 bank.freeAt = schedTime + tBURST + std::max(accessLat, tCL); 356 busBusyUntil = bank.freeAt - tCL; 357 358 if (!rowHitFlag) { 359 bank.tRASDoneAt = bank.freeAt + tRP; 360 recordActivate(bank.freeAt - tCL - tRCD); 361 busBusyUntil = bank.freeAt - tCL - tRCD; 362 } 363 } else if (pageMgmt == Enums::close) { 364 bank.freeAt = schedTime + tBURST + accessLat + tRP + tRP; 365 // Work backwards from bank.freeAt to determine activate time 366 recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD); 367 busBusyUntil = bank.freeAt - tRP - tRP - tCL - tRCD; 368 DPRINTF(DRAMWR, "processWriteEvent::bank.freeAt for " 369 "banks_id %d is %lld\n", 370 dram_pkt->rank * banksPerRank + dram_pkt->bank, 371 bank.freeAt); 372 } else 373 panic("Unknown page management policy chosen\n"); 374 375 DPRINTF(DRAMWR,"Done writing to address %lld\n",dram_pkt->addr); 376 377 DPRINTF(DRAMWR,"schedtime is %lld, tBURST is %lld, " 378 "busbusyuntil is %lld\n", 379 schedTime, tBURST, busBusyUntil); 380 381 dramWriteQueue.pop_front(); 382 delete dram_pkt; 383 384 numWritesThisTime++; 385 } 386 387 DPRINTF(DRAMWR, "Completed %d writes, bus busy for %lld ticks,"\ 388 "banks busy for %lld ticks\n", numWritesThisTime, 389 busBusyUntil - temp1, maxBankFreeAt() - temp2); 390 391 // Update stats 392 avgWrQLen = dramWriteQueue.size(); 393 394 // turn the bus back around for reads again 395 busBusyUntil += tWTR; 396 stopReads = false; 397 398 if (retryWrReq) { 399 retryWrReq = false; 400 port.sendRetry(); 401 } 402 403 // if there is nothing left in any queue, signal a drain 404 if (dramWriteQueue.empty() && dramReadQueue.empty() && 405 dramRespQueue.empty () && drainManager) { 406 drainManager->signalDrainDone(); 407 drainManager = NULL; 408 } 409 410 // Once you're done emptying the write queue, check if there's 411 // anything in the read queue, and call schedule if required 412 schedule(&nextReqEvent, busBusyUntil); 413} 414 415void 416SimpleDRAM::triggerWrites() 417{ 418 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick()); 419 // Flag variable to stop any more read scheduling 420 stopReads = true; 421 422 writeStartTime = std::max(busBusyUntil, curTick()) + tWTR; 423 424 DPRINTF(DRAM, "Writes scheduled at %lld\n", writeStartTime); 425 426 assert(writeStartTime >= curTick()); 427 assert(!writeEvent.scheduled()); 428 schedule(&writeEvent, writeStartTime); 429} 430 431void 432SimpleDRAM::addToWriteQueue(PacketPtr pkt) 433{ 434 // only add to the write queue here. whenever the request is 435 // eventually done, set the readyTime, and call schedule() 436 assert(pkt->isWrite()); 437 438 DRAMPacket* dram_pkt = decodeAddr(pkt); 439 440 assert(dramWriteQueue.size() < writeBufferSize); 441 wrQLenPdf[dramWriteQueue.size()]++; 442 443 DPRINTF(DRAM, "Adding to write queue\n"); 444 445 dramWriteQueue.push_back(dram_pkt); 446 447 // Update stats 448 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 449 assert(bank_id < ranksPerChannel * banksPerRank); 450 perBankWrReqs[bank_id]++; 451 452 avgWrQLen = dramWriteQueue.size(); 453 454 // we do not wait for the writes to be send to the actual memory, 455 // but instead take responsibility for the consistency here and 456 // snoop the write queue for any upcoming reads 457 458 bytesConsumedWr += pkt->getSize(); 459 bytesWritten += bytesPerCacheLine; 460 accessAndRespond(pkt); 461 462 // If your write buffer is starting to fill up, drain it! 463 if (dramWriteQueue.size() > writeThreshold && !stopReads){ 464 triggerWrites(); 465 } 466} 467 468void 469SimpleDRAM::printParams() const 470{ 471 // Sanity check print of important parameters 472 DPRINTF(DRAM, 473 "Memory controller %s physical organization\n" \ 474 "Bytes per cacheline %d\n" \ 475 "Lines per row buffer %d\n" \ 476 "Rows per bank %d\n" \ 477 "Banks per rank %d\n" \ 478 "Ranks per channel %d\n" \ 479 "Total mem capacity %u\n", 480 name(), bytesPerCacheLine ,linesPerRowBuffer, rowsPerBank, 481 banksPerRank, ranksPerChannel, bytesPerCacheLine * 482 linesPerRowBuffer * rowsPerBank * banksPerRank * ranksPerChannel); 483 484 string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 485 string address_mapping = addrMapping == Enums::openmap ? "OPENMAP" : 486 "CLOSEMAP"; 487 string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE"; 488 489 DPRINTF(DRAM, 490 "Memory controller %s characteristics\n" \ 491 "Read buffer size %d\n" \ 492 "Write buffer size %d\n" \ 493 "Write buffer thresh %d\n" \ 494 "Scheduler %s\n" \ 495 "Address mapping %s\n" \ 496 "Page policy %s\n", 497 name(), readBufferSize, writeBufferSize, writeThreshold, 498 scheduler, address_mapping, page_policy); 499 500 DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 501 "tRCD %d ticks\n" \ 502 "tCL %d ticks\n" \ 503 "tRP %d ticks\n" \ 504 "tBURST %d ticks\n" \ 505 "tRFC %d ticks\n" \ 506 "tREFI %d ticks\n" \ 507 "tWTR %d ticks\n", 508 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR); 509} 510 511void 512SimpleDRAM::printQs() const { 513 514 list<DRAMPacket*>::const_iterator i; 515 516 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 517 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 518 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 519 } 520 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 521 for (i = dramRespQueue.begin() ; i != dramRespQueue.end() ; ++i) { 522 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 523 } 524 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 525 for (i = dramWriteQueue.begin() ; i != dramWriteQueue.end() ; ++i) { 526 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 527 } 528} 529 530bool 531SimpleDRAM::recvTimingReq(PacketPtr pkt) 532{ 533 /// @todo temporary hack to deal with memory corruption issues until 534 /// 4-phase transactions are complete 535 for (int x = 0; x < pendingDelete.size(); x++) 536 delete pendingDelete[x]; 537 pendingDelete.clear(); 538 539 540 // This is where we enter from the outside world 541 DPRINTF(DRAM, "Inside recvTimingReq: request %s addr %lld size %d\n", 542 pkt->cmdString(),pkt->getAddr(), pkt->getSize()); 543 544 int index; 545 546 if (pkt->getSize() == bytesPerCacheLine) 547 cpuReqs++; 548 549 if (numReqs % 1000000 == 0) 550 printQs(); 551 552 // Calc avg gap between requests 553 if (prevArrival != 0) { 554 totGap += curTick() - prevArrival; 555 } 556 prevArrival = curTick(); 557 558 // simply drop inhibited packets for now 559 if (pkt->memInhibitAsserted()) { 560 DPRINTF(DRAM,"Inhibited packet -- Dropping it now\n"); 561 pendingDelete.push_back(pkt); 562 return true; 563 } 564 565 unsigned size = pkt->getSize(); 566 if (size > bytesPerCacheLine) 567 panic("Request size %d is greater than cache line size %d", 568 size, bytesPerCacheLine); 569 570 if (size == 0) 571 index = log2(bytesPerCacheLine) + 1; 572 else 573 index = log2(size); 574 575 if (size != 0 && (1 << index) != size) 576 index = log2(bytesPerCacheLine) + 2; 577 578 // @todo: Do we really want to do all this before the packet is 579 // actually accepted? 580 581 /* Index 0 - Size 1 byte 582 Index 1 - Size 2 bytes 583 Index 2 - Size 4 bytes 584 . 585 . 586 Index 6 - Size 64 bytes 587 Index 7 - Size 0 bytes 588 Index 8 - Non-power-of-2 size */ 589 590 if (pkt->isRead()) 591 readPktSize[index]++; 592 else if (pkt->isWrite()) 593 writePktSize[index]++; 594 else 595 neitherPktSize[index]++; 596 597 // check local buffers and do not accept if full 598 if (pkt->isRead()) { 599 if (readQueueFull()) { 600 DPRINTF(DRAM,"Read queue full, not accepting\n"); 601 // remember that we have to retry this port 602 retryRdReq = true; 603 numRdRetry++; 604 return false; 605 } else { 606 addToReadQueue(pkt); 607 readReqs++; 608 numReqs++; 609 } 610 } else if (pkt->isWrite()) { 611 if (writeQueueFull()) { 612 DPRINTF(DRAM,"Write queue full, not accepting\n"); 613 // remember that we have to retry this port 614 retryWrReq = true; 615 numWrRetry++; 616 return false; 617 } else { 618 addToWriteQueue(pkt); 619 writeReqs++; 620 numReqs++; 621 } 622 } else { 623 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 624 neitherReadNorWrite++; 625 accessAndRespond(pkt); 626 } 627 628 629 retryRdReq = false; 630 retryWrReq = false; 631 return true; 632} 633 634void 635SimpleDRAM::processRespondEvent() 636{ 637 DPRINTF(DRAM, 638 "processRespondEvent(): Some req has reached its readyTime\n"); 639 640 PacketPtr pkt = dramRespQueue.front()->pkt; 641 642 // Actually responds to the requestor 643 bytesConsumedRd += pkt->getSize(); 644 bytesRead += bytesPerCacheLine; 645 accessAndRespond(pkt); 646 647 DRAMPacket* dram_pkt = dramRespQueue.front(); 648 dramRespQueue.pop_front(); 649 delete dram_pkt; 650 651 // Update stats 652 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 653 654 if (!dramRespQueue.empty()){ 655 assert(dramRespQueue.front()->readyTime >= curTick()); 656 assert(!respondEvent.scheduled()); 657 schedule(&respondEvent, dramRespQueue.front()->readyTime); 658 } else { 659 // if there is nothing left in any queue, signal a drain 660 if (dramWriteQueue.empty() && dramReadQueue.empty() && 661 drainManager) { 662 drainManager->signalDrainDone(); 663 drainManager = NULL; 664 } 665 } 666} 667 668void 669SimpleDRAM::chooseNextWrite() 670{ 671 // This method does the arbitration between requests. The chosen 672 // packet is simply moved to the head of the queue. The other 673 // methods know that this is the place to look. For example, with 674 // FCFS, this method does nothing 675 assert(!dramWriteQueue.empty()); 676 677 if (dramWriteQueue.size() == 1) { 678 DPRINTF(DRAMWR, "chooseNextWrite(): Single element, nothing to do\n"); 679 return; 680 } 681 682 if (memSchedPolicy == Enums::fcfs) { 683 684 // Do nothing, since the correct request is already head 685 686 } else if (memSchedPolicy == Enums::frfcfs) { 687 688 list<DRAMPacket*>::iterator i = dramWriteQueue.begin(); 689 bool foundRowHit = false; 690 while (!foundRowHit && i != dramWriteQueue.end()) { 691 DRAMPacket* dram_pkt = *i; 692 const Bank& bank = dram_pkt->bank_ref; 693 if (bank.openRow == dram_pkt->row) { //FR part 694 DPRINTF(DRAMWR,"Row buffer hit\n"); 695 dramWriteQueue.erase(i); 696 dramWriteQueue.push_front(dram_pkt); 697 foundRowHit = true; 698 } else { //FCFS part 699 ; 700 } 701 ++i; 702 } 703 704 } else 705 panic("No scheduling policy chosen\n"); 706 707 DPRINTF(DRAMWR, "chooseNextWrite(): Something chosen\n"); 708} 709 710bool 711SimpleDRAM::chooseNextReq() 712{ 713 // This method does the arbitration between requests. 714 // The chosen packet is simply moved to the head of the 715 // queue. The other methods know that this is the place 716 // to look. For example, with FCFS, this method does nothing 717 list<DRAMPacket*>::iterator i; 718 DRAMPacket* dram_pkt; 719 720 if (dramReadQueue.empty()){ 721 DPRINTF(DRAM, "chooseNextReq(): Returning False\n"); 722 return false; 723 } 724 725 if (dramReadQueue.size() == 1) 726 return true; 727 728 if (memSchedPolicy == Enums::fcfs) { 729 730 // Do nothing, since the correct request is already head 731 732 } else if (memSchedPolicy == Enums::frfcfs) { 733 734 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 735 dram_pkt = *i; 736 const Bank& bank = dram_pkt->bank_ref; 737 if (bank.openRow == dram_pkt->row) { //FR part 738 DPRINTF(DRAM, "Row buffer hit\n"); 739 dramReadQueue.erase(i); 740 dramReadQueue.push_front(dram_pkt); 741 break; 742 } else { //FCFS part 743 ; 744 } 745 746 } 747 748 } else 749 panic("No scheduling policy chosen!\n"); 750 751 752 DPRINTF(DRAM,"chooseNextReq(): Chosen something, returning True\n"); 753 return true; 754} 755 756void 757SimpleDRAM::accessAndRespond(PacketPtr pkt) 758{ 759 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 760 761 bool needsResponse = pkt->needsResponse(); 762 // do the actual memory access which also turns the packet into a 763 // response 764 access(pkt); 765 766 // turn packet around to go back to requester if response expected 767 if (needsResponse) { 768 // access already turned the packet into a response 769 assert(pkt->isResponse()); 770 771 // @todo someone should pay for this 772 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 773 774 // queue the packet in the response queue to be sent out the 775 // next tick 776 port.schedTimingResp(pkt, curTick() + 1); 777 } else { 778 } 779 780 DPRINTF(DRAM, "Done\n"); 781 782 return; 783} 784 785pair<Tick, Tick> 786SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 787{ 788 // If a request reaches a bank at tick 'inTime', how much time 789 // *after* that does it take to finish the request, depending 790 // on bank status and page open policy. Note that this method 791 // considers only the time taken for the actual read or write 792 // to complete, NOT any additional time thereafter for tRAS or 793 // tRP. 794 Tick accLat = 0; 795 Tick bankLat = 0; 796 rowHitFlag = false; 797 798 const Bank& bank = dram_pkt->bank_ref; 799 if (pageMgmt == Enums::open) { // open-page policy 800 if (bank.openRow == dram_pkt->row) { 801 // When we have a row-buffer hit, 802 // we don't care about tRAS having expired or not, 803 // but do care about bank being free for access 804 rowHitFlag = true; 805 806 if (bank.freeAt < inTime) { 807 // CAS latency only 808 accLat += tCL; 809 bankLat += tCL; 810 } else { 811 accLat += 0; 812 bankLat += 0; 813 } 814 815 } else { 816 // Row-buffer miss, need to close existing row 817 // once tRAS has expired, then open the new one, 818 // then add cas latency. 819 Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 820 821 if (freeTime > inTime) 822 accLat += freeTime - inTime; 823 824 accLat += tRP + tRCD + tCL; 825 bankLat += tRP + tRCD + tCL; 826 } 827 } else if (pageMgmt == Enums::close) { 828 829 // With a close page policy, no notion of 830 // bank.tRASDoneAt 831 if (bank.freeAt > inTime) 832 accLat += bank.freeAt - inTime; 833 834 // page already closed, simply open the row, and 835 // add cas latency 836 accLat += tRCD + tCL; 837 bankLat += tRCD + tCL; 838 } else 839 panic("No page management policy chosen\n"); 840 841 DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n", 842 bankLat, accLat); 843 844 return make_pair(bankLat, accLat); 845} 846 847void 848SimpleDRAM::processNextReqEvent() 849{ 850 scheduleNextReq(); 851} 852 853void 854SimpleDRAM::recordActivate(Tick act_tick) 855{ 856 assert(actTicks.size() == activationLimit); 857 858 DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 859 860 // sanity check 861 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 862 panic("Got %d activates in window %d (%d - %d) which is smaller " 863 "than %d\n", activationLimit, act_tick - actTicks.back(), 864 act_tick, actTicks.back(), tXAW); 865 } 866 867 // shift the times used for the book keeping, the last element 868 // (highest index) is the oldest one and hence the lowest value 869 actTicks.pop_back(); 870 871 // record an new activation (in the future) 872 actTicks.push_front(act_tick); 873 874 // cannot activate more than X times in time window tXAW, push the 875 // next one (the X + 1'st activate) to be tXAW away from the 876 // oldest in our window of X 877 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 878 DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 879 "than %d\n", activationLimit, actTicks.back() + tXAW); 880 for(int i = 0; i < ranksPerChannel; i++) 881 for(int j = 0; j < banksPerRank; j++) 882 // next activate must not happen before end of window 883 banks[i][j].freeAt = std::max(banks[i][j].freeAt, 884 actTicks.back() + tXAW); 885 } 886} 887 888void 889SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) 890{ 891 892 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 893 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 894 895 assert(curTick() >= prevdramaccess); 896 prevdramaccess = curTick(); 897 898 // estimate the bank and access latency 899 pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 900 Tick bankLat = lat.first; 901 Tick accessLat = lat.second; 902 903 // This request was woken up at this time based on a prior call 904 // to estimateLatency(). However, between then and now, both the 905 // accessLatency and/or busBusyUntil may have changed. We need 906 // to correct for that. 907 908 Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 909 busBusyUntil - (curTick() + accessLat) : 0; 910 911 Bank& bank = dram_pkt->bank_ref; 912 913 // Update bank state 914 if (pageMgmt == Enums::open) { 915 bank.openRow = dram_pkt->row; 916 bank.freeAt = curTick() + addDelay + accessLat; 917 // If you activated a new row do to this access, the next access 918 // will have to respect tRAS for this bank. Assume tRAS ~= 3 * tRP. 919 // Also need to account for t_XAW 920 if (!rowHitFlag) { 921 bank.tRASDoneAt = bank.freeAt + tRP; 922 recordActivate(bank.freeAt - tCL - tRCD); //since this is open page, 923 //no tRP by default 924 } 925 } else if (pageMgmt == Enums::close) { // accounting for tRAS also 926 // assuming that tRAS ~= 3 * tRP, and tRC ~= 4 * tRP, as is common 927 // (refer Jacob/Ng/Wang and Micron datasheets) 928 bank.freeAt = curTick() + addDelay + accessLat + tRP + tRP; 929 recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD); //essentially (freeAt - tRC) 930 DPRINTF(DRAM,"doDRAMAccess::bank.freeAt is %lld\n",bank.freeAt); 931 } else 932 panic("No page management policy chosen\n"); 933 934 // Update request parameters 935 dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 936 937 938 DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 939 "readytime is %lld busbusyuntil is %lld. " \ 940 "Scheduling at readyTime\n", dram_pkt->addr, 941 curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 942 943 // Make sure requests are not overlapping on the databus 944 assert (dram_pkt->readyTime - busBusyUntil >= tBURST); 945 946 // Update bus state 947 busBusyUntil = dram_pkt->readyTime; 948 949 DPRINTF(DRAM,"Access time is %lld\n", 950 dram_pkt->readyTime - dram_pkt->entryTime); 951 952 // Update stats 953 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 954 totBankLat += bankLat; 955 totBusLat += tBURST; 956 totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - tBURST; 957 958 if (rowHitFlag) 959 readRowHits++; 960 961 // At this point we're done dealing with the request 962 // It will be moved to a separate response queue with a 963 // correct readyTime, and eventually be sent back at that 964 //time 965 moveToRespQ(); 966 967 // The absolute soonest you have to start thinking about the 968 // next request is the longest access time that can occur before 969 // busBusyUntil. Assuming you need to meet tRAS, then precharge, 970 // open a new row, and access, it is ~4*tRCD. 971 972 973 Tick newTime = (busBusyUntil > 4 * tRCD) ? 974 std::max(busBusyUntil - 4 * tRCD, curTick()) : 975 curTick(); 976 977 if (!nextReqEvent.scheduled() && !stopReads){ 978 schedule(&nextReqEvent, newTime); 979 } else { 980 if (newTime < nextReqEvent.when()) 981 reschedule(&nextReqEvent, newTime); 982 } 983 984 985} 986 987void 988SimpleDRAM::moveToRespQ() 989{ 990 // Remove from read queue 991 DRAMPacket* dram_pkt = dramReadQueue.front(); 992 dramReadQueue.pop_front(); 993 994 // Insert into response queue sorted by readyTime 995 // It will be sent back to the requestor at its 996 // readyTime 997 if (dramRespQueue.empty()) { 998 dramRespQueue.push_front(dram_pkt); 999 assert(!respondEvent.scheduled()); 1000 assert(dram_pkt->readyTime >= curTick()); 1001 schedule(&respondEvent, dram_pkt->readyTime); 1002 } else { 1003 bool done = false; 1004 std::list<DRAMPacket*>::iterator i = dramRespQueue.begin(); 1005 while (!done && i != dramRespQueue.end()) { 1006 if ((*i)->readyTime > dram_pkt->readyTime) { 1007 dramRespQueue.insert(i, dram_pkt); 1008 done = true; 1009 } 1010 ++i; 1011 } 1012 1013 if (!done) 1014 dramRespQueue.push_back(dram_pkt); 1015 1016 assert(respondEvent.scheduled()); 1017 1018 if (dramRespQueue.front()->readyTime < respondEvent.when()) { 1019 assert(dramRespQueue.front()->readyTime >= curTick()); 1020 reschedule(&respondEvent, dramRespQueue.front()->readyTime); 1021 } 1022 } 1023 1024 if (retryRdReq) { 1025 retryRdReq = false; 1026 port.sendRetry(); 1027 } 1028} 1029 1030void 1031SimpleDRAM::scheduleNextReq() 1032{ 1033 DPRINTF(DRAM, "Reached scheduleNextReq()\n"); 1034 1035 // Figure out which request goes next, and move it to front() 1036 if (!chooseNextReq()) { 1037 // In the case there is no read request to go next, see if we 1038 // are asked to drain, and if so trigger writes, this also 1039 // ensures that if we hit the write limit we will do this 1040 // multiple times until we are completely drained 1041 if (drainManager && !dramWriteQueue.empty() && !writeEvent.scheduled()) 1042 triggerWrites(); 1043 } else { 1044 doDRAMAccess(dramReadQueue.front()); 1045 } 1046} 1047 1048Tick 1049SimpleDRAM::maxBankFreeAt() const 1050{ 1051 Tick banksFree = 0; 1052 1053 for(int i = 0; i < ranksPerChannel; i++) 1054 for(int j = 0; j < banksPerRank; j++) 1055 banksFree = std::max(banks[i][j].freeAt, banksFree); 1056 1057 return banksFree; 1058} 1059 1060void 1061SimpleDRAM::processRefreshEvent() 1062{ 1063 DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick()); 1064 1065 Tick banksFree = std::max(curTick(), maxBankFreeAt()) + tRFC; 1066 1067 for(int i = 0; i < ranksPerChannel; i++) 1068 for(int j = 0; j < banksPerRank; j++) 1069 banks[i][j].freeAt = banksFree; 1070 1071 schedule(&refreshEvent, curTick() + tREFI); 1072} 1073 1074void 1075SimpleDRAM::regStats() 1076{ 1077 using namespace Stats; 1078 1079 AbstractMemory::regStats(); 1080 1081 readReqs 1082 .name(name() + ".readReqs") 1083 .desc("Total number of read requests seen"); 1084 1085 writeReqs 1086 .name(name() + ".writeReqs") 1087 .desc("Total number of write requests seen"); 1088 1089 servicedByWrQ 1090 .name(name() + ".servicedByWrQ") 1091 .desc("Number of read reqs serviced by write Q"); 1092 1093 cpuReqs 1094 .name(name() + ".cpureqs") 1095 .desc("Reqs generatd by CPU via cache - shady"); 1096 1097 neitherReadNorWrite 1098 .name(name() + ".neitherReadNorWrite") 1099 .desc("Reqs where no action is needed"); 1100 1101 perBankRdReqs 1102 .init(banksPerRank * ranksPerChannel) 1103 .name(name() + ".perBankRdReqs") 1104 .desc("Track reads on a per bank basis"); 1105 1106 perBankWrReqs 1107 .init(banksPerRank * ranksPerChannel) 1108 .name(name() + ".perBankWrReqs") 1109 .desc("Track writes on a per bank basis"); 1110 1111 avgRdQLen 1112 .name(name() + ".avgRdQLen") 1113 .desc("Average read queue length over time") 1114 .precision(2); 1115 1116 avgWrQLen 1117 .name(name() + ".avgWrQLen") 1118 .desc("Average write queue length over time") 1119 .precision(2); 1120 1121 totQLat 1122 .name(name() + ".totQLat") 1123 .desc("Total cycles spent in queuing delays"); 1124 1125 totBankLat 1126 .name(name() + ".totBankLat") 1127 .desc("Total cycles spent in bank access"); 1128 1129 totBusLat 1130 .name(name() + ".totBusLat") 1131 .desc("Total cycles spent in databus access"); 1132 1133 totMemAccLat 1134 .name(name() + ".totMemAccLat") 1135 .desc("Sum of mem lat for all requests"); 1136 1137 avgQLat 1138 .name(name() + ".avgQLat") 1139 .desc("Average queueing delay per request") 1140 .precision(2); 1141 1142 avgQLat = totQLat / (readReqs - servicedByWrQ); 1143 1144 avgBankLat 1145 .name(name() + ".avgBankLat") 1146 .desc("Average bank access latency per request") 1147 .precision(2); 1148 1149 avgBankLat = totBankLat / (readReqs - servicedByWrQ); 1150 1151 avgBusLat 1152 .name(name() + ".avgBusLat") 1153 .desc("Average bus latency per request") 1154 .precision(2); 1155 1156 avgBusLat = totBusLat / (readReqs - servicedByWrQ); 1157 1158 avgMemAccLat 1159 .name(name() + ".avgMemAccLat") 1160 .desc("Average memory access latency") 1161 .precision(2); 1162 1163 avgMemAccLat = totMemAccLat / (readReqs - servicedByWrQ); 1164 1165 numRdRetry 1166 .name(name() + ".numRdRetry") 1167 .desc("Number of times rd buffer was full causing retry"); 1168 1169 numWrRetry 1170 .name(name() + ".numWrRetry") 1171 .desc("Number of times wr buffer was full causing retry"); 1172 1173 readRowHits 1174 .name(name() + ".readRowHits") 1175 .desc("Number of row buffer hits during reads"); 1176 1177 writeRowHits 1178 .name(name() + ".writeRowHits") 1179 .desc("Number of row buffer hits during writes"); 1180 1181 readRowHitRate 1182 .name(name() + ".readRowHitRate") 1183 .desc("Row buffer hit rate for reads") 1184 .precision(2); 1185 1186 readRowHitRate = (readRowHits / (readReqs - servicedByWrQ)) * 100; 1187 1188 writeRowHitRate 1189 .name(name() + ".writeRowHitRate") 1190 .desc("Row buffer hit rate for writes") 1191 .precision(2); 1192 1193 writeRowHitRate = (writeRowHits / writeReqs) * 100; 1194 1195 readPktSize 1196 .init(log2(bytesPerCacheLine)+3) 1197 .name(name() + ".readPktSize") 1198 .desc("Categorize read packet sizes"); 1199 1200 writePktSize 1201 .init(log2(bytesPerCacheLine)+3) 1202 .name(name() + ".writePktSize") 1203 .desc("categorize write packet sizes"); 1204 1205 neitherPktSize 1206 .init(log2(bytesPerCacheLine)+3) 1207 .name(name() + ".neitherpktsize") 1208 .desc("categorize neither packet sizes"); 1209 1210 rdQLenPdf 1211 .init(readBufferSize + 1) 1212 .name(name() + ".rdQLenPdf") 1213 .desc("What read queue length does an incoming req see"); 1214 1215 wrQLenPdf 1216 .init(writeBufferSize + 1) 1217 .name(name() + ".wrQLenPdf") 1218 .desc("What write queue length does an incoming req see"); 1219 1220 1221 bytesRead 1222 .name(name() + ".bytesRead") 1223 .desc("Total number of bytes read from memory"); 1224 1225 bytesWritten 1226 .name(name() + ".bytesWritten") 1227 .desc("Total number of bytes written to memory"); 1228 1229 bytesConsumedRd 1230 .name(name() + ".bytesConsumedRd") 1231 .desc("bytesRead derated as per pkt->getSize()"); 1232 1233 bytesConsumedWr 1234 .name(name() + ".bytesConsumedWr") 1235 .desc("bytesWritten derated as per pkt->getSize()"); 1236 1237 avgRdBW 1238 .name(name() + ".avgRdBW") 1239 .desc("Average achieved read bandwidth in MB/s") 1240 .precision(2); 1241 1242 avgRdBW = (bytesRead / 1000000) / simSeconds; 1243 1244 avgWrBW 1245 .name(name() + ".avgWrBW") 1246 .desc("Average achieved write bandwidth in MB/s") 1247 .precision(2); 1248 1249 avgWrBW = (bytesWritten / 1000000) / simSeconds; 1250 1251 avgConsumedRdBW 1252 .name(name() + ".avgConsumedRdBW") 1253 .desc("Average consumed read bandwidth in MB/s") 1254 .precision(2); 1255 1256 avgConsumedRdBW = (bytesConsumedRd / 1000000) / simSeconds; 1257 1258 avgConsumedWrBW 1259 .name(name() + ".avgConsumedWrBW") 1260 .desc("Average consumed write bandwidth in MB/s") 1261 .precision(2); 1262 1263 avgConsumedWrBW = (bytesConsumedWr / 1000000) / simSeconds; 1264 1265 peakBW 1266 .name(name() + ".peakBW") 1267 .desc("Theoretical peak bandwidth in MB/s") 1268 .precision(2); 1269 1270 peakBW = (SimClock::Frequency / tBURST) * bytesPerCacheLine / 1000000; 1271 1272 busUtil 1273 .name(name() + ".busUtil") 1274 .desc("Data bus utilization in percentage") 1275 .precision(2); 1276 1277 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 1278 1279 totGap 1280 .name(name() + ".totGap") 1281 .desc("Total gap between requests"); 1282 1283 avgGap 1284 .name(name() + ".avgGap") 1285 .desc("Average gap between requests") 1286 .precision(2); 1287 1288 avgGap = totGap / (readReqs + writeReqs); 1289} 1290 1291void 1292SimpleDRAM::recvFunctional(PacketPtr pkt) 1293{ 1294 // rely on the abstract memory 1295 functionalAccess(pkt); 1296} 1297 1298BaseSlavePort& 1299SimpleDRAM::getSlavePort(const string &if_name, PortID idx) 1300{ 1301 if (if_name != "port") { 1302 return MemObject::getSlavePort(if_name, idx); 1303 } else { 1304 return port; 1305 } 1306} 1307 1308unsigned int 1309SimpleDRAM::drain(DrainManager *dm) 1310{ 1311 unsigned int count = port.drain(dm); 1312 1313 // if there is anything in any of our internal queues, keep track 1314 // of that as well 1315 if (!(dramWriteQueue.empty() && dramReadQueue.empty() && 1316 dramRespQueue.empty())) { 1317 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 1318 " resp: %d\n", dramWriteQueue.size(), dramReadQueue.size(), 1319 dramRespQueue.size()); 1320 ++count; 1321 drainManager = dm; 1322 // the only part that is not drained automatically over time 1323 // is the write queue, thus trigger writes if there are any 1324 // waiting and no reads waiting, otherwise wait until the 1325 // reads are done 1326 if (dramReadQueue.empty() && !dramWriteQueue.empty() && 1327 !writeEvent.scheduled()) 1328 triggerWrites(); 1329 } 1330 1331 if (count) 1332 setDrainState(Drainable::Draining); 1333 else 1334 setDrainState(Drainable::Drained); 1335 return count; 1336} 1337 1338SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory) 1339 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 1340 memory(_memory) 1341{ } 1342 1343AddrRangeList 1344SimpleDRAM::MemoryPort::getAddrRanges() const 1345{ 1346 AddrRangeList ranges; 1347 ranges.push_back(memory.getAddrRange()); 1348 return ranges; 1349} 1350 1351void 1352SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt) 1353{ 1354 pkt->pushLabel(memory.name()); 1355 1356 if (!queue.checkFunctional(pkt)) { 1357 // Default implementation of SimpleTimingPort::recvFunctional() 1358 // calls recvAtomic() and throws away the latency; we can save a 1359 // little here by just not calculating the latency. 1360 memory.recvFunctional(pkt); 1361 } 1362 1363 pkt->popLabel(); 1364} 1365 1366Tick 1367SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt) 1368{ 1369 return memory.recvAtomic(pkt); 1370} 1371 1372bool 1373SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt) 1374{ 1375 // pass it to the memory controller 1376 return memory.recvTimingReq(pkt); 1377} 1378 1379SimpleDRAM* 1380SimpleDRAMParams::create() 1381{ 1382 return new SimpleDRAM(this); 1383} 1384