dram_ctrl.cc revision 9349
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 * Ani Udipi 39 */ 40 41#include "debug/DRAM.hh" 42#include "debug/DRAMWR.hh" 43#include "mem/simple_dram.hh" 44#include "sim/stat_control.hh" 45 46using namespace std; 47 48SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) : 49 AbstractMemory(p), 50 port(name() + ".port", *this), 51 retryRdReq(false), retryWrReq(false), 52 rowHitFlag(false), stopReads(false), 53 writeEvent(this), respondEvent(this), 54 refreshEvent(this), nextReqEvent(this), drainManager(NULL), 55 bytesPerCacheLine(0), 56 linesPerRowBuffer(p->lines_per_rowbuffer), 57 ranksPerChannel(p->ranks_per_channel), 58 banksPerRank(p->banks_per_rank), rowsPerBank(0), 59 readBufferSize(p->read_buffer_size), 60 writeBufferSize(p->write_buffer_size), 61 writeThresholdPerc(p->write_thresh_perc), 62 tWTR(p->tWTR), tBURST(p->tBURST), 63 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), 64 tRFC(p->tRFC), tREFI(p->tREFI), 65 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 66 pageMgmt(p->page_policy), 67 busBusyUntil(0), prevdramaccess(0), writeStartTime(0), 68 prevArrival(0), numReqs(0) 69{ 70 // create the bank states based on the dimensions of the ranks and 71 // banks 72 banks.resize(ranksPerChannel); 73 for (size_t c = 0; c < ranksPerChannel; ++c) { 74 banks[c].resize(banksPerRank); 75 } 76 77 // round the write threshold percent to a whole number of entries 78 // in the buffer 79 writeThreshold = writeBufferSize * writeThresholdPerc / 100.0; 80} 81 82void 83SimpleDRAM::init() 84{ 85 if (!port.isConnected()) { 86 fatal("SimpleDRAM %s is unconnected!\n", name()); 87 } else { 88 port.sendRangeChange(); 89 } 90 91 // get the cache line size from the connected port 92 bytesPerCacheLine = port.peerBlockSize(); 93 94 // we could deal with plenty options here, but for now do a quick 95 // sanity check 96 if (bytesPerCacheLine != 64 && bytesPerCacheLine != 32) 97 panic("Unexpected cache line size %d", bytesPerCacheLine); 98 99 // determine the rows per bank by looking at the total capacity 100 uint64_t capacity = AbstractMemory::size(); 101 uint64_t i = 1; 102 while (i < 64 && capacity > ((1 << i))) { 103 ++i; 104 } 105 106 // rounded up to nearest power of two 107 DPRINTF(DRAM, "i is %lld\n", i); 108 capacity = 1 << i; 109 110 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 111 AbstractMemory::size()); 112 rowsPerBank = capacity / (bytesPerCacheLine * linesPerRowBuffer * 113 banksPerRank * ranksPerChannel); 114 115} 116 117void 118SimpleDRAM::startup() 119{ 120 // print the configuration of the controller 121 printParams(); 122 123 // kick off the refresh 124 schedule(&refreshEvent, curTick() + tREFI); 125} 126 127 128Tick 129SimpleDRAM::recvAtomic(PacketPtr pkt) 130{ 131 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 132 133 // do the actual memory access and turn the packet into a response 134 access(pkt); 135 136 Tick latency = 0; 137 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 138 // this value is not supposed to be accurate, just enough to 139 // keep things going, mimic a closed page 140 latency = tRP + tRCD + tCL; 141 } 142 return latency; 143} 144 145bool 146SimpleDRAM::readQueueFull() const 147{ 148 DPRINTF(DRAM, "Read queue limit %d current size %d\n", 149 readBufferSize, dramReadQueue.size() + dramRespQueue.size()); 150 151 return (dramReadQueue.size() + dramRespQueue.size()) == readBufferSize; 152} 153 154bool 155SimpleDRAM::writeQueueFull() const 156{ 157 DPRINTF(DRAM, "Write queue limit %d current size %d\n", 158 writeBufferSize, dramWriteQueue.size()); 159 return dramWriteQueue.size() == writeBufferSize; 160} 161 162 163SimpleDRAM::DRAMPacket* 164SimpleDRAM::decodeAddr(PacketPtr pkt) 165{ 166 uint8_t rank; 167 uint16_t bank; 168 uint16_t row; 169 170 Addr addr = pkt->getAddr(); 171 Addr temp = addr; 172 173 // truncate the address to the access granularity 174 addr = addr / bytesPerCacheLine; 175 176 if (addrMapping == Enums::openmap) { 177 addr = addr / linesPerRowBuffer; 178 179 bank = addr % banksPerRank; 180 addr = addr / banksPerRank; 181 182 rank = addr % ranksPerChannel; 183 addr = addr / ranksPerChannel; 184 185 row = addr % rowsPerBank; 186 addr = addr / rowsPerBank; 187 } else if (addrMapping == Enums::closemap) { 188 bank = addr % banksPerRank; 189 addr = addr / banksPerRank; 190 191 rank = addr % ranksPerChannel; 192 addr = addr / ranksPerChannel; 193 194 addr = addr / linesPerRowBuffer; 195 196 row = addr % rowsPerBank; 197 addr = addr / rowsPerBank; 198 } else 199 panic("Unknown address mapping policy chosen!"); 200 201 assert(rank < ranksPerChannel); 202 assert(bank < banksPerRank); 203 assert(row < rowsPerBank); 204 205 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 206 temp, rank, bank, row); 207 208 // create the corresponding DRAM packet with the entry time and 209 // ready time set to the current tick, they will be updated later 210 DRAMPacket* dram_pkt = new DRAMPacket(pkt, rank, bank, row, temp, 211 banks[rank][bank]); 212 213 return dram_pkt; 214} 215 216void 217SimpleDRAM::addToReadQueue(PacketPtr pkt) 218{ 219 // only add to the read queue here. whenever the request is 220 // eventually done, set the readyTime, and call schedule() 221 assert(!pkt->isWrite()); 222 223 // First check write buffer to see if the data is already at 224 // the controller 225 std::list<DRAMPacket*>::const_iterator i; 226 Addr addr = pkt->getAddr(); 227 228 // @todo: add size check 229 for (i = dramWriteQueue.begin(); i != dramWriteQueue.end(); ++i) { 230 if ((*i)->addr == addr){ 231 servicedByWrQ++; 232 DPRINTF(DRAM,"Serviced by write Q\n"); 233 bytesRead += bytesPerCacheLine; 234 bytesConsumedRd += pkt->getSize(); 235 accessAndRespond(pkt); 236 return; 237 } 238 } 239 240 DRAMPacket* dram_pkt = decodeAddr(pkt); 241 242 assert(dramReadQueue.size() + dramRespQueue.size() < readBufferSize); 243 rdQLenPdf[dramReadQueue.size() + dramRespQueue.size()]++; 244 245 DPRINTF(DRAM, "Adding to read queue\n"); 246 247 dramReadQueue.push_back(dram_pkt); 248 249 // Update stats 250 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 251 assert(bank_id < ranksPerChannel * banksPerRank); 252 perBankRdReqs[bank_id]++; 253 254 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 255 256 // Special case where no arbitration is required between requests 257 if (!nextReqEvent.scheduled() && !stopReads) { 258 DPRINTF(DRAM, "Request %lld - need to schedule immediately"); 259 schedule(&nextReqEvent, curTick() + 1); 260 } 261} 262 263void 264SimpleDRAM::processWriteEvent() 265{ 266 assert(!dramWriteQueue.empty()); 267 uint32_t numWritesThisTime = 0; 268 269 DPRINTF(DRAMWR, "Beginning DRAM Writes\n"); 270 Tick temp1 M5_VAR_USED = std::max(curTick(), busBusyUntil); 271 Tick temp2 M5_VAR_USED = std::max(curTick(), maxBankFreeAt()); 272 273 // @todo: are there any dangers with the untimed while loop? 274 while (!dramWriteQueue.empty()) { 275 if (numWritesThisTime > writeThreshold) 276 break; 277 278 chooseNextWrite(); 279 DRAMPacket* dram_pkt = dramWriteQueue.front(); 280 // What's the earlier the request can be put on the bus 281 Tick schedTime = std::max(curTick(), busBusyUntil); 282 283 DPRINTF(DRAMWR, "Asking for latency estimate at %lld\n", 284 schedTime + tBURST); 285 286 pair<Tick, Tick> lat = estimateLatency(dram_pkt, schedTime + tBURST); 287 Tick accessLat = lat.second; 288 289 // look at the rowHitFlag set by estimateLatency 290 291 // @todo: Race condition here where another packet gives rise 292 // to another call to estimateLatency in the meanwhile? 293 if (rowHitFlag) 294 writeRowHits++; 295 296 Bank& bank = dram_pkt->bank_ref; 297 298 if (pageMgmt == Enums::open) { 299 bank.openRow = dram_pkt->row; 300 bank.freeAt = schedTime + tBURST + accessLat; 301 302 if (!rowHitFlag) 303 bank.tRASDoneAt = bank.freeAt + tRP; 304 305 } else if (pageMgmt == Enums::close) { 306 bank.freeAt = schedTime + tBURST + accessLat + tRP + tRP; 307 DPRINTF(DRAMWR, "processWriteEvent::bank.freeAt for " 308 "banks_id %d is %lld\n", 309 dram_pkt->rank * banksPerRank + dram_pkt->bank, 310 bank.freeAt); 311 } else 312 panic("Unknown page management policy chosen\n"); 313 314 // @todo: As of now, write goes on the databus asap, maybe 315 // be held up at bank. May want to change it to delay the 316 // schedTime itself. 317 busBusyUntil = schedTime + tBURST; 318 DPRINTF(DRAMWR,"Done writing to address %lld\n",dram_pkt->addr); 319 320 321 DPRINTF(DRAMWR,"schedtime is %lld, tBURST is %lld, " 322 "busbusyuntil is %lld\n", 323 schedTime, tBURST, busBusyUntil); 324 325 dramWriteQueue.pop_front(); 326 delete dram_pkt; 327 328 numWritesThisTime++; 329 } 330 331 DPRINTF(DRAMWR, "Completed %d writes, bus busy for %lld ticks,"\ 332 "banks busy for %lld ticks\n", numWritesThisTime, 333 busBusyUntil - temp1, maxBankFreeAt() - temp2); 334 335 // Update stats 336 avgWrQLen = dramWriteQueue.size(); 337 338 // turn the bus back around for reads again 339 busBusyUntil += tWTR; 340 stopReads = false; 341 342 if (retryWrReq) { 343 retryWrReq = false; 344 port.sendRetry(); 345 } 346 347 // if there is nothing left in any queue, signal a drain 348 if (dramWriteQueue.empty() && dramReadQueue.empty() && 349 dramRespQueue.empty () && drainManager) { 350 drainManager->signalDrainDone(); 351 drainManager = NULL; 352 } 353 354 // Once you're done emptying the write queue, check if there's 355 // anything in the read queue, and call schedule if required 356 schedule(&nextReqEvent, busBusyUntil); 357} 358 359void 360SimpleDRAM::triggerWrites() 361{ 362 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick()); 363 // Flag variable to stop any more read scheduling 364 stopReads = true; 365 366 writeStartTime = std::max(busBusyUntil, curTick()) + tWTR; 367 368 DPRINTF(DRAM, "Writes scheduled at %lld\n", writeStartTime); 369 370 assert(writeStartTime >= curTick()); 371 assert(!writeEvent.scheduled()); 372 schedule(&writeEvent, writeStartTime); 373} 374 375void 376SimpleDRAM::addToWriteQueue(PacketPtr pkt) 377{ 378 // only add to the write queue here. whenever the request is 379 // eventually done, set the readyTime, and call schedule() 380 assert(pkt->isWrite()); 381 382 DRAMPacket* dram_pkt = decodeAddr(pkt); 383 384 assert(dramWriteQueue.size() < writeBufferSize); 385 wrQLenPdf[dramWriteQueue.size()]++; 386 387 DPRINTF(DRAM, "Adding to write queue\n"); 388 389 dramWriteQueue.push_back(dram_pkt); 390 391 // Update stats 392 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 393 assert(bank_id < ranksPerChannel * banksPerRank); 394 perBankWrReqs[bank_id]++; 395 396 avgWrQLen = dramWriteQueue.size(); 397 398 // we do not wait for the writes to be send to the actual memory, 399 // but instead take responsibility for the consistency here and 400 // snoop the write queue for any upcoming reads 401 402 bytesConsumedWr += pkt->getSize(); 403 bytesWritten += bytesPerCacheLine; 404 accessAndRespond(pkt); 405 406 // If your write buffer is starting to fill up, drain it! 407 if (dramWriteQueue.size() > writeThreshold && !stopReads){ 408 triggerWrites(); 409 } 410} 411 412void 413SimpleDRAM::printParams() const 414{ 415 // Sanity check print of important parameters 416 DPRINTF(DRAM, 417 "Memory controller %s physical organization\n" \ 418 "Bytes per cacheline %d\n" \ 419 "Lines per row buffer %d\n" \ 420 "Rows per bank %d\n" \ 421 "Banks per rank %d\n" \ 422 "Ranks per channel %d\n" \ 423 "Total mem capacity %u\n", 424 name(), bytesPerCacheLine ,linesPerRowBuffer, rowsPerBank, 425 banksPerRank, ranksPerChannel, bytesPerCacheLine * 426 linesPerRowBuffer * rowsPerBank * banksPerRank * ranksPerChannel); 427 428 string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 429 string address_mapping = addrMapping == Enums::openmap ? "OPENMAP" : 430 "CLOSEMAP"; 431 string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE"; 432 433 DPRINTF(DRAM, 434 "Memory controller %s characteristics\n" \ 435 "Read buffer size %d\n" \ 436 "Write buffer size %d\n" \ 437 "Write buffer thresh %d\n" \ 438 "Scheduler %s\n" \ 439 "Address mapping %s\n" \ 440 "Page policy %s\n", 441 name(), readBufferSize, writeBufferSize, writeThreshold, 442 scheduler, address_mapping, page_policy); 443 444 DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 445 "tRCD %d ticks\n" \ 446 "tCL %d ticks\n" \ 447 "tRP %d ticks\n" \ 448 "tBURST %d ticks\n" \ 449 "tRFC %d ticks\n" \ 450 "tREFI %d ticks\n" \ 451 "tWTR %d ticks\n", 452 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR); 453} 454 455void 456SimpleDRAM::printQs() const { 457 458 list<DRAMPacket*>::const_iterator i; 459 460 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 461 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 462 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 463 } 464 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 465 for (i = dramRespQueue.begin() ; i != dramRespQueue.end() ; ++i) { 466 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 467 } 468 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 469 for (i = dramWriteQueue.begin() ; i != dramWriteQueue.end() ; ++i) { 470 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 471 } 472} 473 474bool 475SimpleDRAM::recvTimingReq(PacketPtr pkt) 476{ 477 /// @todo temporary hack to deal with memory corruption issues until 478 /// 4-phase transactions are complete 479 for (int x = 0; x < pendingDelete.size(); x++) 480 delete pendingDelete[x]; 481 pendingDelete.clear(); 482 483 484 // This is where we enter from the outside world 485 DPRINTF(DRAM, "Inside recvTimingReq: request %s addr %lld size %d\n", 486 pkt->cmdString(),pkt->getAddr(), pkt->getSize()); 487 488 int index; 489 490 if (pkt->getSize() == bytesPerCacheLine) 491 cpuReqs++; 492 493 if (numReqs % 1000000 == 0) 494 printQs(); 495 496 // Calc avg gap between requests 497 if (prevArrival != 0) { 498 totGap += curTick() - prevArrival; 499 } 500 prevArrival = curTick(); 501 502 // simply drop inhibited packets for now 503 if (pkt->memInhibitAsserted()) { 504 DPRINTF(DRAM,"Inhibited packet -- Dropping it now\n"); 505 pendingDelete.push_back(pkt); 506 return true; 507 } 508 509 unsigned size = pkt->getSize(); 510 if (size > bytesPerCacheLine) 511 panic("Request size %d is greater than cache line size %d", 512 size, bytesPerCacheLine); 513 514 if (size == 0) 515 index = log2(bytesPerCacheLine) + 1; 516 else 517 index = log2(size); 518 519 if (size != 0 && (1 << index) != size) 520 index = log2(bytesPerCacheLine) + 2; 521 522 // @todo: Do we really want to do all this before the packet is 523 // actually accepted? 524 525 /* Index 0 - Size 1 byte 526 Index 1 - Size 2 bytes 527 Index 2 - Size 4 bytes 528 . 529 . 530 Index 6 - Size 64 bytes 531 Index 7 - Size 0 bytes 532 Index 8 - Non-power-of-2 size */ 533 534 if (pkt->isRead()) 535 readPktSize[index]++; 536 else if (pkt->isWrite()) 537 writePktSize[index]++; 538 else 539 neitherPktSize[index]++; 540 541 // check local buffers and do not accept if full 542 if (pkt->isRead()) { 543 if (readQueueFull()) { 544 DPRINTF(DRAM,"Read queue full, not accepting\n"); 545 // remember that we have to retry this port 546 retryRdReq = true; 547 numRdRetry++; 548 return false; 549 } else { 550 addToReadQueue(pkt); 551 readReqs++; 552 numReqs++; 553 } 554 } else if (pkt->isWrite()) { 555 if (writeQueueFull()) { 556 DPRINTF(DRAM,"Write queue full, not accepting\n"); 557 // remember that we have to retry this port 558 retryWrReq = true; 559 numWrRetry++; 560 return false; 561 } else { 562 addToWriteQueue(pkt); 563 writeReqs++; 564 numReqs++; 565 } 566 } else { 567 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 568 neitherReadNorWrite++; 569 accessAndRespond(pkt); 570 } 571 572 573 retryRdReq = false; 574 retryWrReq = false; 575 return true; 576} 577 578void 579SimpleDRAM::processRespondEvent() 580{ 581 DPRINTF(DRAM, 582 "processRespondEvent(): Some req has reached its readyTime\n"); 583 584 PacketPtr pkt = dramRespQueue.front()->pkt; 585 586 // Actually responds to the requestor 587 bytesConsumedRd += pkt->getSize(); 588 bytesRead += bytesPerCacheLine; 589 accessAndRespond(pkt); 590 591 DRAMPacket* dram_pkt = dramRespQueue.front(); 592 dramRespQueue.pop_front(); 593 delete dram_pkt; 594 595 // Update stats 596 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 597 598 if (!dramRespQueue.empty()){ 599 assert(dramRespQueue.front()->readyTime >= curTick()); 600 assert(!respondEvent.scheduled()); 601 schedule(&respondEvent, dramRespQueue.front()->readyTime); 602 } else { 603 // if there is nothing left in any queue, signal a drain 604 if (dramWriteQueue.empty() && dramReadQueue.empty() && 605 drainManager) { 606 drainManager->signalDrainDone(); 607 drainManager = NULL; 608 } 609 } 610} 611 612void 613SimpleDRAM::chooseNextWrite() 614{ 615 // This method does the arbitration between requests. The chosen 616 // packet is simply moved to the head of the queue. The other 617 // methods know that this is the place to look. For example, with 618 // FCFS, this method does nothing 619 assert(!dramWriteQueue.empty()); 620 621 if (dramWriteQueue.size() == 1) { 622 DPRINTF(DRAMWR, "chooseNextWrite(): Single element, nothing to do\n"); 623 return; 624 } 625 626 if (memSchedPolicy == Enums::fcfs) { 627 628 // Do nothing, since the correct request is already head 629 630 } else if (memSchedPolicy == Enums::frfcfs) { 631 632 list<DRAMPacket*>::iterator i = dramWriteQueue.begin(); 633 bool foundRowHit = false; 634 while (!foundRowHit && i != dramWriteQueue.end()) { 635 DRAMPacket* dram_pkt = *i; 636 const Bank& bank = dram_pkt->bank_ref; 637 if (bank.openRow == dram_pkt->row) { //FR part 638 DPRINTF(DRAMWR,"Row buffer hit\n"); 639 dramWriteQueue.erase(i); 640 dramWriteQueue.push_front(dram_pkt); 641 foundRowHit = true; 642 } else { //FCFS part 643 ; 644 } 645 ++i; 646 } 647 648 } else 649 panic("No scheduling policy chosen\n"); 650 651 DPRINTF(DRAMWR, "chooseNextWrite(): Something chosen\n"); 652} 653 654bool 655SimpleDRAM::chooseNextReq() 656{ 657 // This method does the arbitration between requests. 658 // The chosen packet is simply moved to the head of the 659 // queue. The other methods know that this is the place 660 // to look. For example, with FCFS, this method does nothing 661 list<DRAMPacket*>::iterator i; 662 DRAMPacket* dram_pkt; 663 664 if (dramReadQueue.empty()){ 665 DPRINTF(DRAM, "chooseNextReq(): Returning False\n"); 666 return false; 667 } 668 669 if (dramReadQueue.size() == 1) 670 return true; 671 672 if (memSchedPolicy == Enums::fcfs) { 673 674 // Do nothing, since the correct request is already head 675 676 } else if (memSchedPolicy == Enums::frfcfs) { 677 678 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 679 dram_pkt = *i; 680 const Bank& bank = dram_pkt->bank_ref; 681 if (bank.openRow == dram_pkt->row) { //FR part 682 DPRINTF(DRAM, "Row buffer hit\n"); 683 dramReadQueue.erase(i); 684 dramReadQueue.push_front(dram_pkt); 685 break; 686 } else { //FCFS part 687 ; 688 } 689 690 } 691 692 } else 693 panic("No scheduling policy chosen!\n"); 694 695 696 DPRINTF(DRAM,"chooseNextReq(): Chosen something, returning True\n"); 697 return true; 698} 699 700void 701SimpleDRAM::accessAndRespond(PacketPtr pkt) 702{ 703 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 704 705 bool needsResponse = pkt->needsResponse(); 706 // do the actual memory access which also turns the packet into a 707 // response 708 access(pkt); 709 710 // turn packet around to go back to requester if response expected 711 if (needsResponse) { 712 // access already turned the packet into a response 713 assert(pkt->isResponse()); 714 715 // queue the packet in the response queue to be sent out the 716 // next tick 717 port.schedTimingResp(pkt, curTick() + 1); 718 } else { 719 } 720 721 DPRINTF(DRAM, "Done\n"); 722 723 return; 724} 725 726pair<Tick, Tick> 727SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 728{ 729 // If a request reaches a bank at tick 'inTime', how much time 730 // *after* that does it take to finish the request, depending 731 // on bank status and page open policy. Note that this method 732 // considers only the time taken for the actual read or write 733 // to complete, NOT any additional time thereafter for tRAS or 734 // tRP. 735 Tick accLat = 0; 736 Tick bankLat = 0; 737 rowHitFlag = false; 738 739 const Bank& bank = dram_pkt->bank_ref; 740 if (pageMgmt == Enums::open) { // open-page policy 741 if (bank.openRow == dram_pkt->row) { 742 // When we have a row-buffer hit, 743 // we don't care about tRAS having expired or not, 744 // but do care about bank being free for access 745 rowHitFlag = true; 746 747 if (bank.freeAt < inTime) { 748 // CAS latency only 749 accLat += tCL; 750 bankLat += tCL; 751 } else { 752 accLat += 0; 753 bankLat += 0; 754 } 755 756 } else { 757 // Row-buffer miss, need to close existing row 758 // once tRAS has expired, then open the new one, 759 // then add cas latency. 760 Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 761 762 if (freeTime > inTime) 763 accLat += freeTime - inTime; 764 765 accLat += tRP + tRCD + tCL; 766 bankLat += tRP + tRCD + tCL; 767 } 768 } else if (pageMgmt == Enums::close) { 769 770 // With a close page policy, no notion of 771 // bank.tRASDoneAt 772 if (bank.freeAt > inTime) 773 accLat += bank.freeAt - inTime; 774 775 // page already closed, simply open the row, and 776 // add cas latency 777 accLat += tRCD + tCL; 778 bankLat += tRCD + tCL; 779 } else 780 panic("No page management policy chosen\n"); 781 782 DPRINTF(DRAM, "Returning %lld from estimateLatency()\n",accLat); 783 784 return make_pair(bankLat, accLat); 785} 786 787void 788SimpleDRAM::processNextReqEvent() 789{ 790 scheduleNextReq(); 791} 792 793void 794SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) 795{ 796 797 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 798 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 799 800 assert(curTick() >= prevdramaccess); 801 prevdramaccess = curTick(); 802 803 // estimate the bank and access latency 804 pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 805 Tick bankLat = lat.first; 806 Tick accessLat = lat.second; 807 808 // This request was woken up at this time based on a prior call 809 // to estimateLatency(). However, between then and now, both the 810 // accessLatency and/or busBusyUntil may have changed. We need 811 // to correct for that. 812 813 Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 814 busBusyUntil - (curTick() + accessLat) : 0; 815 816 Bank& bank = dram_pkt->bank_ref; 817 818 // Update bank state 819 if (pageMgmt == Enums::open) { 820 bank.openRow = dram_pkt->row; 821 bank.freeAt = curTick() + addDelay + accessLat; 822 // If you activated a new row do to this access, the next access 823 // will have to respect tRAS for this bank. Assume tRAS ~= 3 * tRP 824 if (!rowHitFlag) 825 bank.tRASDoneAt = bank.freeAt + tRP; 826 827 } else if (pageMgmt == Enums::close) { // accounting for tRAS also 828 // assuming that tRAS ~= 3 * tRP, and tRAS ~= 4 * tRP, as is common 829 // (refer Jacob/Ng/Wang and Micron datasheets) 830 bank.freeAt = curTick() + addDelay + accessLat + tRP + tRP; 831 DPRINTF(DRAM,"doDRAMAccess::bank.freeAt is %lld\n",bank.freeAt); 832 } else 833 panic("No page management policy chosen\n"); 834 835 // Update request parameters 836 dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 837 838 839 DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 840 "readytime is %lld busbusyuntil is %lld. " \ 841 "Scheduling at readyTime\n", dram_pkt->addr, 842 curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 843 844 // Make sure requests are not overlapping on the databus 845 assert (dram_pkt->readyTime - busBusyUntil >= tBURST); 846 847 // Update bus state 848 busBusyUntil = dram_pkt->readyTime; 849 850 DPRINTF(DRAM,"Access time is %lld\n", 851 dram_pkt->readyTime - dram_pkt->entryTime); 852 853 // Update stats 854 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 855 totBankLat += bankLat; 856 totBusLat += tBURST; 857 totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - tBURST; 858 859 if (rowHitFlag) 860 readRowHits++; 861 862 // At this point we're done dealing with the request 863 // It will be moved to a separate response queue with a 864 // correct readyTime, and eventually be sent back at that 865 //time 866 moveToRespQ(); 867 868 // The absolute soonest you have to start thinking about the 869 // next request is the longest access time that can occur before 870 // busBusyUntil. Assuming you need to meet tRAS, then precharge, 871 // open a new row, and access, it is ~4*tRCD. 872 873 874 Tick newTime = (busBusyUntil > 4 * tRCD) ? 875 std::max(busBusyUntil - 4 * tRCD, curTick()) : 876 curTick(); 877 878 if (!nextReqEvent.scheduled() && !stopReads){ 879 schedule(&nextReqEvent, newTime); 880 } else { 881 if (newTime < nextReqEvent.when()) 882 reschedule(&nextReqEvent, newTime); 883 } 884 885 886} 887 888void 889SimpleDRAM::moveToRespQ() 890{ 891 // Remove from read queue 892 DRAMPacket* dram_pkt = dramReadQueue.front(); 893 dramReadQueue.pop_front(); 894 895 // Insert into response queue sorted by readyTime 896 // It will be sent back to the requestor at its 897 // readyTime 898 if (dramRespQueue.empty()) { 899 dramRespQueue.push_front(dram_pkt); 900 assert(!respondEvent.scheduled()); 901 assert(dram_pkt->readyTime >= curTick()); 902 schedule(&respondEvent, dram_pkt->readyTime); 903 } else { 904 bool done = false; 905 std::list<DRAMPacket*>::iterator i = dramRespQueue.begin(); 906 while (!done && i != dramRespQueue.end()) { 907 if ((*i)->readyTime > dram_pkt->readyTime) { 908 dramRespQueue.insert(i, dram_pkt); 909 done = true; 910 } 911 ++i; 912 } 913 914 if (!done) 915 dramRespQueue.push_back(dram_pkt); 916 917 assert(respondEvent.scheduled()); 918 919 if (dramRespQueue.front()->readyTime < respondEvent.when()) { 920 assert(dramRespQueue.front()->readyTime >= curTick()); 921 reschedule(&respondEvent, dramRespQueue.front()->readyTime); 922 } 923 } 924 925 if (retryRdReq) { 926 retryRdReq = false; 927 port.sendRetry(); 928 } 929} 930 931void 932SimpleDRAM::scheduleNextReq() 933{ 934 DPRINTF(DRAM, "Reached scheduleNextReq()\n"); 935 936 // Figure out which request goes next, and move it to front() 937 if (!chooseNextReq()) 938 return; 939 940 doDRAMAccess(dramReadQueue.front()); 941} 942 943 944 945 946Tick 947SimpleDRAM::maxBankFreeAt() const 948{ 949 Tick banksFree = 0; 950 951 for(int i = 0; i < ranksPerChannel; i++) 952 for(int j = 0; j < banksPerRank; j++) 953 banksFree = std::max(banks[i][j].freeAt, banksFree); 954 955 return banksFree; 956} 957 958void 959SimpleDRAM::processRefreshEvent() 960{ 961 DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick()); 962 963 Tick banksFree = std::max(curTick(), maxBankFreeAt()) + tRFC; 964 965 for(int i = 0; i < ranksPerChannel; i++) 966 for(int j = 0; j < banksPerRank; j++) 967 banks[i][j].freeAt = banksFree; 968 969 schedule(&refreshEvent, curTick() + tREFI); 970} 971 972void 973SimpleDRAM::regStats() 974{ 975 using namespace Stats; 976 977 AbstractMemory::regStats(); 978 979 readReqs 980 .name(name() + ".readReqs") 981 .desc("Total number of read requests seen"); 982 983 writeReqs 984 .name(name() + ".writeReqs") 985 .desc("Total number of write requests seen"); 986 987 servicedByWrQ 988 .name(name() + ".servicedByWrQ") 989 .desc("Number of read reqs serviced by write Q"); 990 991 cpuReqs 992 .name(name() + ".cpureqs") 993 .desc("Reqs generatd by CPU via cache - shady"); 994 995 neitherReadNorWrite 996 .name(name() + ".neitherReadNorWrite") 997 .desc("Reqs where no action is needed"); 998 999 perBankRdReqs 1000 .init(banksPerRank * ranksPerChannel) 1001 .name(name() + ".perBankRdReqs") 1002 .desc("Track reads on a per bank basis"); 1003 1004 perBankWrReqs 1005 .init(banksPerRank * ranksPerChannel) 1006 .name(name() + ".perBankWrReqs") 1007 .desc("Track writes on a per bank basis"); 1008 1009 avgRdQLen 1010 .name(name() + ".avgRdQLen") 1011 .desc("Average read queue length over time") 1012 .precision(2); 1013 1014 avgWrQLen 1015 .name(name() + ".avgWrQLen") 1016 .desc("Average write queue length over time") 1017 .precision(2); 1018 1019 totQLat 1020 .name(name() + ".totQLat") 1021 .desc("Total cycles spent in queuing delays"); 1022 1023 totBankLat 1024 .name(name() + ".totBankLat") 1025 .desc("Total cycles spent in bank access"); 1026 1027 totBusLat 1028 .name(name() + ".totBusLat") 1029 .desc("Total cycles spent in databus access"); 1030 1031 totMemAccLat 1032 .name(name() + ".totMemAccLat") 1033 .desc("Sum of mem lat for all requests"); 1034 1035 avgQLat 1036 .name(name() + ".avgQLat") 1037 .desc("Average queueing delay per request") 1038 .precision(2); 1039 1040 avgQLat = totQLat / (readReqs - servicedByWrQ); 1041 1042 avgBankLat 1043 .name(name() + ".avgBankLat") 1044 .desc("Average bank access latency per request") 1045 .precision(2); 1046 1047 avgBankLat = totBankLat / (readReqs - servicedByWrQ); 1048 1049 avgBusLat 1050 .name(name() + ".avgBusLat") 1051 .desc("Average bus latency per request") 1052 .precision(2); 1053 1054 avgBusLat = totBusLat / (readReqs - servicedByWrQ); 1055 1056 avgMemAccLat 1057 .name(name() + ".avgMemAccLat") 1058 .desc("Average memory access latency") 1059 .precision(2); 1060 1061 avgMemAccLat = totMemAccLat / (readReqs - servicedByWrQ); 1062 1063 numRdRetry 1064 .name(name() + ".numRdRetry") 1065 .desc("Number of times rd buffer was full causing retry"); 1066 1067 numWrRetry 1068 .name(name() + ".numWrRetry") 1069 .desc("Number of times wr buffer was full causing retry"); 1070 1071 readRowHits 1072 .name(name() + ".readRowHits") 1073 .desc("Number of row buffer hits during reads"); 1074 1075 writeRowHits 1076 .name(name() + ".writeRowHits") 1077 .desc("Number of row buffer hits during writes"); 1078 1079 readRowHitRate 1080 .name(name() + ".readRowHitRate") 1081 .desc("Row buffer hit rate for reads") 1082 .precision(2); 1083 1084 readRowHitRate = (readRowHits / (readReqs - servicedByWrQ)) * 100; 1085 1086 writeRowHitRate 1087 .name(name() + ".writeRowHitRate") 1088 .desc("Row buffer hit rate for writes") 1089 .precision(2); 1090 1091 writeRowHitRate = (writeRowHits / writeReqs) * 100; 1092 1093 readPktSize 1094 .init(log2(bytesPerCacheLine)+3) 1095 .name(name() + ".readPktSize") 1096 .desc("Categorize read packet sizes"); 1097 1098 writePktSize 1099 .init(log2(bytesPerCacheLine)+3) 1100 .name(name() + ".writePktSize") 1101 .desc("categorize write packet sizes"); 1102 1103 neitherPktSize 1104 .init(log2(bytesPerCacheLine)+3) 1105 .name(name() + ".neitherpktsize") 1106 .desc("categorize neither packet sizes"); 1107 1108 rdQLenPdf 1109 .init(readBufferSize + 1) 1110 .name(name() + ".rdQLenPdf") 1111 .desc("What read queue length does an incoming req see"); 1112 1113 wrQLenPdf 1114 .init(writeBufferSize + 1) 1115 .name(name() + ".wrQLenPdf") 1116 .desc("What write queue length does an incoming req see"); 1117 1118 1119 bytesRead 1120 .name(name() + ".bytesRead") 1121 .desc("Total number of bytes read from memory"); 1122 1123 bytesWritten 1124 .name(name() + ".bytesWritten") 1125 .desc("Total number of bytes written to memory"); 1126 1127 bytesConsumedRd 1128 .name(name() + ".bytesConsumedRd") 1129 .desc("bytesRead derated as per pkt->getSize()"); 1130 1131 bytesConsumedWr 1132 .name(name() + ".bytesConsumedWr") 1133 .desc("bytesWritten derated as per pkt->getSize()"); 1134 1135 avgRdBW 1136 .name(name() + ".avgRdBW") 1137 .desc("Average achieved read bandwidth in MB/s") 1138 .precision(2); 1139 1140 avgRdBW = (bytesRead / 1000000) / simSeconds; 1141 1142 avgWrBW 1143 .name(name() + ".avgWrBW") 1144 .desc("Average achieved write bandwidth in MB/s") 1145 .precision(2); 1146 1147 avgWrBW = (bytesWritten / 1000000) / simSeconds; 1148 1149 avgConsumedRdBW 1150 .name(name() + ".avgConsumedRdBW") 1151 .desc("Average consumed read bandwidth in MB/s") 1152 .precision(2); 1153 1154 avgConsumedRdBW = (bytesConsumedRd / 1000000) / simSeconds; 1155 1156 avgConsumedWrBW 1157 .name(name() + ".avgConsumedWrBW") 1158 .desc("Average consumed write bandwidth in MB/s") 1159 .precision(2); 1160 1161 avgConsumedWrBW = (bytesConsumedWr / 1000000) / simSeconds; 1162 1163 peakBW 1164 .name(name() + ".peakBW") 1165 .desc("Theoretical peak bandwidth in MB/s") 1166 .precision(2); 1167 1168 peakBW = (SimClock::Frequency / tBURST) * bytesPerCacheLine / 1000000; 1169 1170 busUtil 1171 .name(name() + ".busUtil") 1172 .desc("Data bus utilization in percentage") 1173 .precision(2); 1174 1175 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 1176 1177 totGap 1178 .name(name() + ".totGap") 1179 .desc("Total gap between requests"); 1180 1181 avgGap 1182 .name(name() + ".avgGap") 1183 .desc("Average gap between requests") 1184 .precision(2); 1185 1186 avgGap = totGap / (readReqs + writeReqs); 1187} 1188 1189void 1190SimpleDRAM::recvFunctional(PacketPtr pkt) 1191{ 1192 // rely on the abstract memory 1193 functionalAccess(pkt); 1194} 1195 1196BaseSlavePort& 1197SimpleDRAM::getSlavePort(const string &if_name, PortID idx) 1198{ 1199 if (if_name != "port") { 1200 return MemObject::getSlavePort(if_name, idx); 1201 } else { 1202 return port; 1203 } 1204} 1205 1206unsigned int 1207SimpleDRAM::drain(DrainManager *dm) 1208{ 1209 unsigned int count = port.drain(dm); 1210 1211 // if there is anything in any of our internal queues, keep track 1212 // of that as well 1213 if (!(dramWriteQueue.empty() && dramReadQueue.empty() && 1214 dramRespQueue.empty())) { 1215 ++count; 1216 drainManager = dm; 1217 } 1218 1219 if (count) 1220 setDrainState(Drainable::Draining); 1221 else 1222 setDrainState(Drainable::Drained); 1223 return count; 1224} 1225 1226SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory) 1227 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 1228 memory(_memory) 1229{ } 1230 1231AddrRangeList 1232SimpleDRAM::MemoryPort::getAddrRanges() const 1233{ 1234 AddrRangeList ranges; 1235 ranges.push_back(memory.getAddrRange()); 1236 return ranges; 1237} 1238 1239void 1240SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt) 1241{ 1242 pkt->pushLabel(memory.name()); 1243 1244 if (!queue.checkFunctional(pkt)) { 1245 // Default implementation of SimpleTimingPort::recvFunctional() 1246 // calls recvAtomic() and throws away the latency; we can save a 1247 // little here by just not calculating the latency. 1248 memory.recvFunctional(pkt); 1249 } 1250 1251 pkt->popLabel(); 1252} 1253 1254Tick 1255SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt) 1256{ 1257 return memory.recvAtomic(pkt); 1258} 1259 1260bool 1261SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt) 1262{ 1263 // pass it to the memory controller 1264 return memory.recvTimingReq(pkt); 1265} 1266 1267SimpleDRAM* 1268SimpleDRAMParams::create() 1269{ 1270 return new SimpleDRAM(this); 1271} 1272