dram_ctrl.cc revision 10809
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 449243SN/A */ 459243SN/A 4610146Sandreas.hansson@arm.com#include "base/bitfield.hh" 479356SN/A#include "base/trace.hh" 4810146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4910247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5010208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 519352SN/A#include "debug/Drain.hh" 5210146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 539814SN/A#include "sim/system.hh" 549243SN/A 559243SN/Ausing namespace std; 5610432SOmar.Naji@arm.comusing namespace Data; 579243SN/A 5810146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 599243SN/A AbstractMemory(p), 6010619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 619243SN/A retryRdReq(false), retryWrReq(false), 6210211Sandreas.hansson@arm.com busState(READ), 6310618SOmar.Naji@arm.com nextReqEvent(this), respondEvent(this), 6410208Sandreas.hansson@arm.com drainManager(NULL), 6510489SOmar.Naji@arm.com deviceSize(p->device_size), 669831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 679831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 689831SN/A devicesPerRank(p->devices_per_rank), 699831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 709831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7110140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7210646Sandreas.hansson@arm.com columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1), 739243SN/A ranksPerChannel(p->ranks_per_channel), 7410394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7510394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 769566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 779243SN/A readBufferSize(p->read_buffer_size), 789243SN/A writeBufferSize(p->write_buffer_size), 7910140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8010140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8110147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8210147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8310393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8410394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8510394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8610394Swendy.elsasser@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 879243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 889243SN/A pageMgmt(p->page_policy), 8910141SN/A maxAccessesPerRow(p->max_accesses_per_row), 909726SN/A frontendLatency(p->static_frontend_latency), 919726SN/A backendLatency(p->static_backend_latency), 9210618SOmar.Naji@arm.com busBusyUntil(0), prevArrival(0), 9310618SOmar.Naji@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0) 949243SN/A{ 9510620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 9610620Sandreas.hansson@arm.com // address decoding 9710620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 9810620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 9910620Sandreas.hansson@arm.com 10010618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 10110618SOmar.Naji@arm.com Rank* rank = new Rank(*this, p); 10210618SOmar.Naji@arm.com ranks.push_back(rank); 10310432SOmar.Naji@arm.com 10410618SOmar.Naji@arm.com rank->actTicks.resize(activationLimit, 0); 10510618SOmar.Naji@arm.com rank->banks.resize(banksPerRank); 10610618SOmar.Naji@arm.com rank->rank = i; 10710432SOmar.Naji@arm.com 10810246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 10910618SOmar.Naji@arm.com rank->banks[b].bank = b; 11010561SOmar.Naji@arm.com // GDDR addressing of banks to BG is linear. 11110561SOmar.Naji@arm.com // Here we assume that all DRAM generations address bank groups as 11210561SOmar.Naji@arm.com // follows: 11310394Swendy.elsasser@arm.com if (bankGroupArch) { 11410394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 11510394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 11610394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 11710394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 11810394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 11910394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 12010394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 12110618SOmar.Naji@arm.com rank->banks[b].bankgr = b % bankGroupsPerRank; 12210394Swendy.elsasser@arm.com } else { 12310394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 12410618SOmar.Naji@arm.com rank->banks[b].bankgr = b; 12510394Swendy.elsasser@arm.com } 12610246Sandreas.hansson@arm.com } 12710246Sandreas.hansson@arm.com } 12810246Sandreas.hansson@arm.com 12910140SN/A // perform a basic check of the write thresholds 13010140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 13110140SN/A fatal("Write buffer low threshold %d must be smaller than the " 13210140SN/A "high threshold %d\n", p->write_low_thresh_perc, 13310140SN/A p->write_high_thresh_perc); 1349243SN/A 1359243SN/A // determine the rows per bank by looking at the total capacity 1369567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1379243SN/A 13810489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 13910489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 14010489SOmar.Naji@arm.com ranksPerChannel; 14110489SOmar.Naji@arm.com 14210489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 14310489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 14410489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 14510489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 14610489SOmar.Naji@arm.com capacity / (1024 * 1024)); 14710489SOmar.Naji@arm.com 1489243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1499243SN/A AbstractMemory::size()); 1509831SN/A 1519831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1529831SN/A rowBufferSize, columnsPerRowBuffer); 1539831SN/A 1549831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1559243SN/A 15610207Sandreas.hansson@arm.com // some basic sanity checks 15710207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 15810207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 15910207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 16010207Sandreas.hansson@arm.com } 16110394Swendy.elsasser@arm.com 16210394Swendy.elsasser@arm.com // basic bank group architecture checks -> 16310394Swendy.elsasser@arm.com if (bankGroupArch) { 16410394Swendy.elsasser@arm.com // must have at least one bank per bank group 16510394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 16610394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 16710394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 16810394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 16910394Swendy.elsasser@arm.com } 17010394Swendy.elsasser@arm.com // must have same number of banks in each bank group 17110394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 17210394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 17310394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 17410394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 17510394Swendy.elsasser@arm.com } 17610394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 17710394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 17810394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 17910394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 18010394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 18110394Swendy.elsasser@arm.com } 18210394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 18310561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 18410561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 18510394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 18610394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 18710394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 18810394Swendy.elsasser@arm.com } 18910394Swendy.elsasser@arm.com } 19010394Swendy.elsasser@arm.com 1919243SN/A} 1929243SN/A 1939243SN/Avoid 19410146Sandreas.hansson@arm.comDRAMCtrl::init() 19510140SN/A{ 19610466Sandreas.hansson@arm.com AbstractMemory::init(); 19710466Sandreas.hansson@arm.com 19810466Sandreas.hansson@arm.com if (!port.isConnected()) { 19910146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 20010140SN/A } else { 20110140SN/A port.sendRangeChange(); 20210140SN/A } 20310646Sandreas.hansson@arm.com 20410646Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving, save it for here to 20510646Sandreas.hansson@arm.com // ensure that the system pointer is initialised 20610646Sandreas.hansson@arm.com if (range.interleaved()) { 20710646Sandreas.hansson@arm.com if (channels != range.stripes()) 20810646Sandreas.hansson@arm.com fatal("%s has %d interleaved address stripes but %d channel(s)\n", 20910646Sandreas.hansson@arm.com name(), range.stripes(), channels); 21010646Sandreas.hansson@arm.com 21110646Sandreas.hansson@arm.com if (addrMapping == Enums::RoRaBaChCo) { 21210646Sandreas.hansson@arm.com if (rowBufferSize != range.granularity()) { 21310646Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 21410646Sandreas.hansson@arm.com "address map\n", name()); 21510646Sandreas.hansson@arm.com } 21610646Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 21710646Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 21810646Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 21910646Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 22010646Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 22110646Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 22210646Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 22310646Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 22410646Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 22510646Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 22610646Sandreas.hansson@arm.com 22710646Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 22810646Sandreas.hansson@arm.com // is equal or larger to a cache line 22910646Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 23010646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 23110646Sandreas.hansson@arm.com "as the cache line size\n", name()); 23210646Sandreas.hansson@arm.com } 23310646Sandreas.hansson@arm.com 23410646Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 23510646Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 23610646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 23710646Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 23810646Sandreas.hansson@arm.com } 23910646Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 24010646Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 24110646Sandreas.hansson@arm.com } 24210646Sandreas.hansson@arm.com } 24310140SN/A} 24410140SN/A 24510140SN/Avoid 24610146Sandreas.hansson@arm.comDRAMCtrl::startup() 2479243SN/A{ 24810619Sandreas.hansson@arm.com // remember the memory system mode of operation 24910619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 25010618SOmar.Naji@arm.com 25110619Sandreas.hansson@arm.com if (isTimingMode) { 25210619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 25310619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 25410619Sandreas.hansson@arm.com 25510619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 25610619Sandreas.hansson@arm.com // current tick 25710619Sandreas.hansson@arm.com for (auto r : ranks) { 25810619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 25910619Sandreas.hansson@arm.com } 26010619Sandreas.hansson@arm.com 26110619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 26210619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 26310619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 26410619Sandreas.hansson@arm.com // start of simulation 26510619Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 26610618SOmar.Naji@arm.com } 2679243SN/A} 2689243SN/A 2699243SN/ATick 27010146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2719243SN/A{ 2729243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2739243SN/A 2749243SN/A // do the actual memory access and turn the packet into a response 2759243SN/A access(pkt); 2769243SN/A 2779243SN/A Tick latency = 0; 2789243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2799243SN/A // this value is not supposed to be accurate, just enough to 2809243SN/A // keep things going, mimic a closed page 2819243SN/A latency = tRP + tRCD + tCL; 2829243SN/A } 2839243SN/A return latency; 2849243SN/A} 2859243SN/A 2869243SN/Abool 28710146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2889243SN/A{ 2899831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2909831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2919831SN/A neededEntries); 2929243SN/A 2939831SN/A return 2949831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2959243SN/A} 2969243SN/A 2979243SN/Abool 29810146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2999243SN/A{ 3009831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 3019831SN/A writeBufferSize, writeQueue.size(), neededEntries); 3029831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 3039243SN/A} 3049243SN/A 30510146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 30610146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 30710143SN/A bool isRead) 3089243SN/A{ 3099669SN/A // decode the address based on the address mapping scheme, with 31010136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 31110136SN/A // channel, respectively 3129243SN/A uint8_t rank; 3139967SN/A uint8_t bank; 31410245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 31510245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 31610245Sandreas.hansson@arm.com uint64_t row; 3179243SN/A 31810286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 31910286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3209831SN/A Addr addr = dramPktAddr / burstSize; 3219243SN/A 3229491SN/A // we have removed the lowest order address bits that denote the 3239831SN/A // position within the column 32410136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3259491SN/A // the lowest order bits denote the column to ensure that 3269491SN/A // sequential cache lines occupy the same row 3279831SN/A addr = addr / columnsPerRowBuffer; 3289243SN/A 3299669SN/A // take out the channel part of the address 3309566SN/A addr = addr / channels; 3319566SN/A 3329669SN/A // after the channel bits, get the bank bits to interleave 3339669SN/A // over the banks 3349669SN/A bank = addr % banksPerRank; 3359669SN/A addr = addr / banksPerRank; 3369669SN/A 3379669SN/A // after the bank, we get the rank bits which thus interleaves 3389669SN/A // over the ranks 3399669SN/A rank = addr % ranksPerChannel; 3409669SN/A addr = addr / ranksPerChannel; 3419669SN/A 3429669SN/A // lastly, get the row bits 3439669SN/A row = addr % rowsPerBank; 3449669SN/A addr = addr / rowsPerBank; 34510136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 34610286Sandreas.hansson@arm.com // take out the lower-order column bits 34710286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 34810286Sandreas.hansson@arm.com 3499669SN/A // take out the channel part of the address 3509669SN/A addr = addr / channels; 3519669SN/A 35210286Sandreas.hansson@arm.com // next, the higher-order column bites 35310286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3549669SN/A 3559669SN/A // after the column bits, we get the bank bits to interleave 3569491SN/A // over the banks 3579243SN/A bank = addr % banksPerRank; 3589243SN/A addr = addr / banksPerRank; 3599243SN/A 3609491SN/A // after the bank, we get the rank bits which thus interleaves 3619491SN/A // over the ranks 3629243SN/A rank = addr % ranksPerChannel; 3639243SN/A addr = addr / ranksPerChannel; 3649243SN/A 3659491SN/A // lastly, get the row bits 3669243SN/A row = addr % rowsPerBank; 3679243SN/A addr = addr / rowsPerBank; 36810136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3699491SN/A // optimise for closed page mode and utilise maximum 3709491SN/A // parallelism of the DRAM (at the cost of power) 3719491SN/A 37210286Sandreas.hansson@arm.com // take out the lower-order column bits 37310286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 37410286Sandreas.hansson@arm.com 3759566SN/A // take out the channel part of the address, not that this has 3769566SN/A // to match with how accesses are interleaved between the 3779566SN/A // controllers in the address mapping 3789566SN/A addr = addr / channels; 3799566SN/A 3809491SN/A // start with the bank bits, as this provides the maximum 3819491SN/A // opportunity for parallelism between requests 3829243SN/A bank = addr % banksPerRank; 3839243SN/A addr = addr / banksPerRank; 3849243SN/A 3859491SN/A // next get the rank bits 3869243SN/A rank = addr % ranksPerChannel; 3879243SN/A addr = addr / ranksPerChannel; 3889243SN/A 38910286Sandreas.hansson@arm.com // next, the higher-order column bites 39010286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3919243SN/A 3929491SN/A // lastly, get the row bits 3939243SN/A row = addr % rowsPerBank; 3949243SN/A addr = addr / rowsPerBank; 3959243SN/A } else 3969243SN/A panic("Unknown address mapping policy chosen!"); 3979243SN/A 3989243SN/A assert(rank < ranksPerChannel); 3999243SN/A assert(bank < banksPerRank); 4009243SN/A assert(row < rowsPerBank); 40110245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 4029243SN/A 4039243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 4049831SN/A dramPktAddr, rank, bank, row); 4059243SN/A 4069243SN/A // create the corresponding DRAM packet with the entry time and 4079567SN/A // ready time set to the current tick, the latter will be updated 4089567SN/A // later 4099967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4109967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 41110618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 4129243SN/A} 4139243SN/A 4149243SN/Avoid 41510146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4169243SN/A{ 4179243SN/A // only add to the read queue here. whenever the request is 4189243SN/A // eventually done, set the readyTime, and call schedule() 4199243SN/A assert(!pkt->isWrite()); 4209243SN/A 4219831SN/A assert(pktCount != 0); 4229831SN/A 4239831SN/A // if the request size is larger than burst size, the pkt is split into 4249831SN/A // multiple DRAM packets 4259831SN/A // Note if the pkt starting address is not aligened to burst size, the 4269831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4279831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4289831SN/A // check read packets against packets in write queue. 4299243SN/A Addr addr = pkt->getAddr(); 4309831SN/A unsigned pktsServicedByWrQ = 0; 4319831SN/A BurstHelper* burst_helper = NULL; 4329831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4339831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4349831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4359831SN/A readPktSize[ceilLog2(size)]++; 4369831SN/A readBursts++; 4379243SN/A 4389831SN/A // First check write buffer to see if the data is already at 4399831SN/A // the controller 4409831SN/A bool foundInWrQ = false; 4419833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 4429832SN/A // check if the read is subsumed in the write entry we are 4439832SN/A // looking at 4449832SN/A if ((*i)->addr <= addr && 4459832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 4469831SN/A foundInWrQ = true; 4479831SN/A servicedByWrQ++; 4489831SN/A pktsServicedByWrQ++; 4499831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 4509831SN/A "write queue\n", addr, size); 4519975SN/A bytesReadWrQ += burstSize; 4529831SN/A break; 4539831SN/A } 4549243SN/A } 4559831SN/A 4569831SN/A // If not found in the write q, make a DRAM packet and 4579831SN/A // push it onto the read queue 4589831SN/A if (!foundInWrQ) { 4599831SN/A 4609831SN/A // Make the burst helper for split packets 4619831SN/A if (pktCount > 1 && burst_helper == NULL) { 4629831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4639831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4649831SN/A burst_helper = new BurstHelper(pktCount); 4659831SN/A } 4669831SN/A 4679966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4689831SN/A dram_pkt->burstHelper = burst_helper; 4699831SN/A 4709831SN/A assert(!readQueueFull(1)); 4719831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4729831SN/A 4739831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4749831SN/A 4759831SN/A readQueue.push_back(dram_pkt); 4769831SN/A 4779831SN/A // Update stats 4789831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4799831SN/A } 4809831SN/A 4819831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4829831SN/A addr = (addr | (burstSize - 1)) + 1; 4839243SN/A } 4849243SN/A 4859831SN/A // If all packets are serviced by write queue, we send the repsonse back 4869831SN/A if (pktsServicedByWrQ == pktCount) { 4879831SN/A accessAndRespond(pkt, frontendLatency); 4889831SN/A return; 4899831SN/A } 4909243SN/A 4919831SN/A // Update how many split packets are serviced by write queue 4929831SN/A if (burst_helper != NULL) 4939831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4949243SN/A 49510206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 49610206Sandreas.hansson@arm.com // queue, do so now 49710206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4989567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4999567SN/A schedule(nextReqEvent, curTick()); 5009243SN/A } 5019243SN/A} 5029243SN/A 5039243SN/Avoid 50410146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 5059243SN/A{ 5069243SN/A // only add to the write queue here. whenever the request is 5079243SN/A // eventually done, set the readyTime, and call schedule() 5089243SN/A assert(pkt->isWrite()); 5099243SN/A 5109831SN/A // if the request size is larger than burst size, the pkt is split into 5119831SN/A // multiple DRAM packets 5129831SN/A Addr addr = pkt->getAddr(); 5139831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5149831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5159831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5169831SN/A writePktSize[ceilLog2(size)]++; 5179831SN/A writeBursts++; 5189243SN/A 5199832SN/A // see if we can merge with an existing item in the write 5209838SN/A // queue and keep track of whether we have merged or not so we 5219838SN/A // can stop at that point and also avoid enqueueing a new 5229838SN/A // request 5239832SN/A bool merged = false; 5249832SN/A auto w = writeQueue.begin(); 5259243SN/A 5269832SN/A while(!merged && w != writeQueue.end()) { 5279832SN/A // either of the two could be first, if they are the same 5289832SN/A // it does not matter which way we go 5299832SN/A if ((*w)->addr >= addr) { 5309838SN/A // the existing one starts after the new one, figure 5319838SN/A // out where the new one ends with respect to the 5329838SN/A // existing one 5339832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 5349832SN/A // check if the existing one is completely 5359832SN/A // subsumed in the new one 5369832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 5379832SN/A merged = true; 5389832SN/A // update both the address and the size 5399832SN/A (*w)->addr = addr; 5409832SN/A (*w)->size = size; 5419832SN/A } else if ((addr + size) >= (*w)->addr && 5429832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 5439832SN/A // the new one is just before or partially 5449832SN/A // overlapping with the existing one, and together 5459832SN/A // they fit within a burst 5469832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 5479832SN/A merged = true; 5489832SN/A // the existing queue item needs to be adjusted with 5499832SN/A // respect to both address and size 55010047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 5519832SN/A (*w)->addr = addr; 5529832SN/A } 5539832SN/A } else { 5549838SN/A // the new one starts after the current one, figure 5559838SN/A // out where the existing one ends with respect to the 5569838SN/A // new one 5579832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 5589832SN/A // check if the new one is completely subsumed in the 5599832SN/A // existing one 5609832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 5619832SN/A merged = true; 5629832SN/A // no adjustments necessary 5639832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 5649832SN/A (addr + size - (*w)->addr) <= burstSize) { 5659832SN/A // the existing one is just before or partially 5669832SN/A // overlapping with the new one, and together 5679832SN/A // they fit within a burst 5689832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5699832SN/A merged = true; 5709832SN/A // the address is right, and only the size has 5719832SN/A // to be adjusted 5729832SN/A (*w)->size = addr + size - (*w)->addr; 5739832SN/A } 5749832SN/A } 5759832SN/A ++w; 5769832SN/A } 5779243SN/A 5789832SN/A // if the item was not merged we need to create a new write 5799832SN/A // and enqueue it 5809832SN/A if (!merged) { 5819966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5829243SN/A 5839832SN/A assert(writeQueue.size() < writeBufferSize); 5849832SN/A wrQLenPdf[writeQueue.size()]++; 5859243SN/A 5869832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5879831SN/A 5889832SN/A writeQueue.push_back(dram_pkt); 5899831SN/A 5909832SN/A // Update stats 5919832SN/A avgWrQLen = writeQueue.size(); 5929977SN/A } else { 5939977SN/A // keep track of the fact that this burst effectively 5949977SN/A // disappeared as it was merged with an existing one 5959977SN/A mergedWrBursts++; 5969832SN/A } 5979832SN/A 5989831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5999831SN/A addr = (addr | (burstSize - 1)) + 1; 6009831SN/A } 6019243SN/A 6029243SN/A // we do not wait for the writes to be send to the actual memory, 6039243SN/A // but instead take responsibility for the consistency here and 6049243SN/A // snoop the write queue for any upcoming reads 6059831SN/A // @todo, if a pkt size is larger than burst size, we might need a 6069831SN/A // different front end latency 6079726SN/A accessAndRespond(pkt, frontendLatency); 6089243SN/A 60910206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 61010206Sandreas.hansson@arm.com // queue, do so now 61110206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 61210206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 61310206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 6149243SN/A } 6159243SN/A} 6169243SN/A 6179243SN/Avoid 61810146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 6199243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 6209833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 6219243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 6229243SN/A } 6239243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 6249833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 6259243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 6269243SN/A } 6279243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 6289833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 6299243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 6309243SN/A } 6319243SN/A} 6329243SN/A 6339243SN/Abool 63410146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6359243SN/A{ 6369349SN/A /// @todo temporary hack to deal with memory corruption issues until 6379349SN/A /// 4-phase transactions are complete 6389349SN/A for (int x = 0; x < pendingDelete.size(); x++) 6399349SN/A delete pendingDelete[x]; 6409349SN/A pendingDelete.clear(); 6419349SN/A 6429243SN/A // This is where we enter from the outside world 6439567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6449831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6459243SN/A 6469567SN/A // simply drop inhibited packets for now 6479567SN/A if (pkt->memInhibitAsserted()) { 64810143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6499567SN/A pendingDelete.push_back(pkt); 6509567SN/A return true; 6519567SN/A } 6529243SN/A 6539243SN/A // Calc avg gap between requests 6549243SN/A if (prevArrival != 0) { 6559243SN/A totGap += curTick() - prevArrival; 6569243SN/A } 6579243SN/A prevArrival = curTick(); 6589243SN/A 6599831SN/A 6609831SN/A // Find out how many dram packets a pkt translates to 6619831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6629831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6639831SN/A // multiple dram packets 6649243SN/A unsigned size = pkt->getSize(); 6659831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6669831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6679243SN/A 6689243SN/A // check local buffers and do not accept if full 6699243SN/A if (pkt->isRead()) { 6709567SN/A assert(size != 0); 6719831SN/A if (readQueueFull(dram_pkt_count)) { 6729567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6739243SN/A // remember that we have to retry this port 6749243SN/A retryRdReq = true; 6759243SN/A numRdRetry++; 6769243SN/A return false; 6779243SN/A } else { 6789831SN/A addToReadQueue(pkt, dram_pkt_count); 6799243SN/A readReqs++; 6809977SN/A bytesReadSys += size; 6819243SN/A } 6829243SN/A } else if (pkt->isWrite()) { 6839567SN/A assert(size != 0); 6849831SN/A if (writeQueueFull(dram_pkt_count)) { 6859567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6869243SN/A // remember that we have to retry this port 6879243SN/A retryWrReq = true; 6889243SN/A numWrRetry++; 6899243SN/A return false; 6909243SN/A } else { 6919831SN/A addToWriteQueue(pkt, dram_pkt_count); 6929243SN/A writeReqs++; 6939977SN/A bytesWrittenSys += size; 6949243SN/A } 6959243SN/A } else { 6969243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6979243SN/A neitherReadNorWrite++; 6989726SN/A accessAndRespond(pkt, 1); 6999243SN/A } 7009243SN/A 7019243SN/A return true; 7029243SN/A} 7039243SN/A 7049243SN/Avoid 70510146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 7069243SN/A{ 7079243SN/A DPRINTF(DRAM, 7089243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 7099243SN/A 7109831SN/A DRAMPacket* dram_pkt = respQueue.front(); 7119243SN/A 7129831SN/A if (dram_pkt->burstHelper) { 7139831SN/A // it is a split packet 7149831SN/A dram_pkt->burstHelper->burstsServiced++; 7159831SN/A if (dram_pkt->burstHelper->burstsServiced == 71610143SN/A dram_pkt->burstHelper->burstCount) { 7179831SN/A // we have now serviced all children packets of a system packet 7189831SN/A // so we can now respond to the requester 7199831SN/A // @todo we probably want to have a different front end and back 7209831SN/A // end latency for split packets 7219831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7229831SN/A delete dram_pkt->burstHelper; 7239831SN/A dram_pkt->burstHelper = NULL; 7249831SN/A } 7259831SN/A } else { 7269831SN/A // it is not a split packet 7279831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7289831SN/A } 7299243SN/A 7309831SN/A delete respQueue.front(); 7319831SN/A respQueue.pop_front(); 7329243SN/A 7339831SN/A if (!respQueue.empty()) { 7349831SN/A assert(respQueue.front()->readyTime >= curTick()); 7359831SN/A assert(!respondEvent.scheduled()); 7369831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7379831SN/A } else { 7389831SN/A // if there is nothing left in any queue, signal a drain 7399831SN/A if (writeQueue.empty() && readQueue.empty() && 7409831SN/A drainManager) { 74110509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 7429831SN/A drainManager->signalDrainDone(); 7439831SN/A drainManager = NULL; 7449831SN/A } 7459831SN/A } 7469567SN/A 7479831SN/A // We have made a location in the queue available at this point, 7489831SN/A // so if there is a read that was forced to wait, retry now 7499831SN/A if (retryRdReq) { 7509831SN/A retryRdReq = false; 75110713Sandreas.hansson@arm.com port.sendRetryReq(); 7529831SN/A } 7539243SN/A} 7549243SN/A 75510618SOmar.Naji@arm.combool 75610393Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7579243SN/A{ 75810206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 75910206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 76010206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 76110206Sandreas.hansson@arm.com // FCFS, this method does nothing 76210206Sandreas.hansson@arm.com assert(!queue.empty()); 7639243SN/A 76410618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 76510618SOmar.Naji@arm.com bool found_packet = false; 76610206Sandreas.hansson@arm.com if (queue.size() == 1) { 76710618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 76810618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 76910618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 77010618SOmar.Naji@arm.com found_packet = true; 77110618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 77210618SOmar.Naji@arm.com } else { 77310618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 77410618SOmar.Naji@arm.com } 77510618SOmar.Naji@arm.com return found_packet; 7769243SN/A } 7779243SN/A 7789243SN/A if (memSchedPolicy == Enums::fcfs) { 77910618SOmar.Naji@arm.com // check if there is a packet going to a free rank 78010618SOmar.Naji@arm.com for(auto i = queue.begin(); i != queue.end() ; ++i) { 78110618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 78210618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 78310618SOmar.Naji@arm.com queue.erase(i); 78410618SOmar.Naji@arm.com queue.push_front(dram_pkt); 78510618SOmar.Naji@arm.com found_packet = true; 78610618SOmar.Naji@arm.com break; 78710618SOmar.Naji@arm.com } 78810618SOmar.Naji@arm.com } 7899243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 79010618SOmar.Naji@arm.com found_packet = reorderQueue(queue, switched_cmd_type); 7919243SN/A } else 7929243SN/A panic("No scheduling policy chosen\n"); 79310618SOmar.Naji@arm.com return found_packet; 7949243SN/A} 7959243SN/A 79610618SOmar.Naji@arm.combool 79710393Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7989974SN/A{ 7999974SN/A // Only determine this when needed 8009974SN/A uint64_t earliest_banks = 0; 8019974SN/A 8029974SN/A // Search for row hits first, if no row hit is found then schedule the 8039974SN/A // packet to one of the earliest banks available 80410618SOmar.Naji@arm.com bool found_packet = false; 8059974SN/A bool found_earliest_pkt = false; 80610393Swendy.elsasser@arm.com bool found_prepped_diff_rank_pkt = false; 80710618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 8089974SN/A 8099974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8109974SN/A DRAMPacket* dram_pkt = *i; 8119974SN/A const Bank& bank = dram_pkt->bankRef; 81210618SOmar.Naji@arm.com // check if rank is busy. If this is the case jump to the next packet 8139974SN/A // Check if it is a row hit 81410618SOmar.Naji@arm.com if (dram_pkt->rankRef.isAvailable()) { 81510618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 81610618SOmar.Naji@arm.com if (dram_pkt->rank == activeRank || switched_cmd_type) { 81710618SOmar.Naji@arm.com // FCFS within the hits, giving priority to commands 81810618SOmar.Naji@arm.com // that access the same rank as the previous burst 81910618SOmar.Naji@arm.com // to minimize bus turnaround delays 82010618SOmar.Naji@arm.com // Only give rank prioity when command type is 82110618SOmar.Naji@arm.com // not changing 82210618SOmar.Naji@arm.com DPRINTF(DRAM, "Row buffer hit\n"); 82310618SOmar.Naji@arm.com selected_pkt_it = i; 82410618SOmar.Naji@arm.com break; 82510618SOmar.Naji@arm.com } else if (!found_prepped_diff_rank_pkt) { 82610618SOmar.Naji@arm.com // found row hit for command on different rank 82710618SOmar.Naji@arm.com // than prev burst 82810618SOmar.Naji@arm.com selected_pkt_it = i; 82910618SOmar.Naji@arm.com found_prepped_diff_rank_pkt = true; 83010618SOmar.Naji@arm.com } 83110618SOmar.Naji@arm.com } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 83210618SOmar.Naji@arm.com // packet going to a rank which is currently not waiting for a 83310618SOmar.Naji@arm.com // refresh, No row hit and 83410618SOmar.Naji@arm.com // haven't found an entry with a row hit to a new rank 83510618SOmar.Naji@arm.com if (earliest_banks == 0) 83610618SOmar.Naji@arm.com // Determine entries with earliest bank prep delay 83710618SOmar.Naji@arm.com // Function will give priority to commands that access the 83810618SOmar.Naji@arm.com // same rank as previous burst and can prep 83910618SOmar.Naji@arm.com // the bank seamlessly 84010618SOmar.Naji@arm.com earliest_banks = minBankPrep(queue, switched_cmd_type); 84110211Sandreas.hansson@arm.com 84210618SOmar.Naji@arm.com // FCFS - Bank is first available bank 84310618SOmar.Naji@arm.com if (bits(earliest_banks, dram_pkt->bankId, 84410618SOmar.Naji@arm.com dram_pkt->bankId)) { 84510618SOmar.Naji@arm.com // Remember the packet to be scheduled to one of 84610618SOmar.Naji@arm.com // the earliest banks available, FCFS amongst the 84710618SOmar.Naji@arm.com // earliest banks 84810618SOmar.Naji@arm.com selected_pkt_it = i; 84910618SOmar.Naji@arm.com //if the packet found is going to a rank that is currently 85010618SOmar.Naji@arm.com //not busy then update the found_packet to true 85110618SOmar.Naji@arm.com found_earliest_pkt = true; 85210618SOmar.Naji@arm.com } 8539974SN/A } 8549974SN/A } 8559974SN/A } 8569974SN/A 85710618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 85810618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 85910618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 86010618SOmar.Naji@arm.com queue.push_front(selected_pkt); 86110618SOmar.Naji@arm.com found_packet = true; 86210618SOmar.Naji@arm.com } 86310618SOmar.Naji@arm.com return found_packet; 8649974SN/A} 8659974SN/A 8669974SN/Avoid 86710146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8689243SN/A{ 8699243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8709243SN/A 8719243SN/A bool needsResponse = pkt->needsResponse(); 8729243SN/A // do the actual memory access which also turns the packet into a 8739243SN/A // response 8749243SN/A access(pkt); 8759243SN/A 8769243SN/A // turn packet around to go back to requester if response expected 8779243SN/A if (needsResponse) { 8789243SN/A // access already turned the packet into a response 8799243SN/A assert(pkt->isResponse()); 88010721SMarco.Balboni@ARM.com // response_time consumes the static latency and is charged also 88110721SMarco.Balboni@ARM.com // with headerDelay that takes into account the delay provided by 88210721SMarco.Balboni@ARM.com // the xbar and also the payloadDelay that takes into account the 88310721SMarco.Balboni@ARM.com // number of data beats. 88410721SMarco.Balboni@ARM.com Tick response_time = curTick() + static_latency + pkt->headerDelay + 88510721SMarco.Balboni@ARM.com pkt->payloadDelay; 88610721SMarco.Balboni@ARM.com // Here we reset the timing of the packet before sending it out. 88710694SMarco.Balboni@ARM.com pkt->headerDelay = pkt->payloadDelay = 0; 8889549SN/A 8899726SN/A // queue the packet in the response queue to be sent out after 8909726SN/A // the static latency has passed 89110721SMarco.Balboni@ARM.com port.schedTimingResp(pkt, response_time); 8929243SN/A } else { 8939587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8949587SN/A // is still having a pointer to it 8959587SN/A pendingDelete.push_back(pkt); 8969243SN/A } 8979243SN/A 8989243SN/A DPRINTF(DRAM, "Done\n"); 8999243SN/A 9009243SN/A return; 9019243SN/A} 9029243SN/A 9039243SN/Avoid 90410618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 90510618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 9069488SN/A{ 90710618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 9089488SN/A 9099488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 9109488SN/A 91110207Sandreas.hansson@arm.com // update the open row 91210618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 91310618SOmar.Naji@arm.com bank_ref.openRow = row; 91410207Sandreas.hansson@arm.com 91510207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 91610207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 91710207Sandreas.hansson@arm.com // precharge 91810618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 91910618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 92010207Sandreas.hansson@arm.com 92110618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 92210618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 92310207Sandreas.hansson@arm.com 92410247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 92510618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 92610618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 92710247Sandreas.hansson@arm.com 92810618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank, 92910618SOmar.Naji@arm.com divCeil(act_tick, tCK) - 93010618SOmar.Naji@arm.com timeStampOffset); 93110432SOmar.Naji@arm.com 93210432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 93310618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9349975SN/A 93510211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 93610618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 93710211Sandreas.hansson@arm.com 93810211Sandreas.hansson@arm.com // Respect the row-to-column command delay 93910618SOmar.Naji@arm.com bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 94010211Sandreas.hansson@arm.com 9419971SN/A // start by enforcing tRRD 9429971SN/A for(int i = 0; i < banksPerRank; i++) { 94310210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 94410210Sandreas.hansson@arm.com // before tRRD 94510618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 94610394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 94710394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 94810394Swendy.elsasser@arm.com // in this case 94910618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 95010618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 95110394Swendy.elsasser@arm.com } else { 95210394Swendy.elsasser@arm.com // use shorter tRRD value when either 95310394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 95410394Swendy.elsasser@arm.com // 2) bank is in a different bank group 95510618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 95610618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 95710394Swendy.elsasser@arm.com } 9589971SN/A } 95910208Sandreas.hansson@arm.com 9609971SN/A // next, we deal with tXAW, if the activation limit is disabled 96110492SOmar.Naji@arm.com // then we directly schedule an activate power event 96210618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 96310492SOmar.Naji@arm.com // sanity check 96410618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 96510618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 96610492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 96710492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 96810618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 96910618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 97010492SOmar.Naji@arm.com } 9719824SN/A 97210492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 97310492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 97410618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9759488SN/A 97610492SOmar.Naji@arm.com // record an new activation (in the future) 97710618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 9789488SN/A 97910492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 98010492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 98110492SOmar.Naji@arm.com // oldest in our window of X 98210618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 98310618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 98410492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 98510492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 98610618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 9879488SN/A for(int j = 0; j < banksPerRank; j++) 9889488SN/A // next activate must not happen before end of window 98910618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 99010618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 99110618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 99210492SOmar.Naji@arm.com } 9939488SN/A } 99410208Sandreas.hansson@arm.com 99510208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 99610208Sandreas.hansson@arm.com // transition to the active power state 99710618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 99810618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 99910618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 100010208Sandreas.hansson@arm.com // move it sooner in time 100110618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 100210208Sandreas.hansson@arm.com} 100310208Sandreas.hansson@arm.com 100410208Sandreas.hansson@arm.comvoid 100510618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 100610207Sandreas.hansson@arm.com{ 100710207Sandreas.hansson@arm.com // make sure the bank has an open row 100810207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 100910207Sandreas.hansson@arm.com 101010207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 101110207Sandreas.hansson@arm.com // the page 101210207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 101310207Sandreas.hansson@arm.com 101410207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 101510207Sandreas.hansson@arm.com 101610214Sandreas.hansson@arm.com // no precharge allowed before this one 101710214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 101810214Sandreas.hansson@arm.com 101910211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 102010211Sandreas.hansson@arm.com 102110211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 102210207Sandreas.hansson@arm.com 102310618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 102410618SOmar.Naji@arm.com --rank_ref.numBanksActive; 102510207Sandreas.hansson@arm.com 102610247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 102710618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 102810618SOmar.Naji@arm.com rank_ref.numBanksActive); 102910247Sandreas.hansson@arm.com 103010432SOmar.Naji@arm.com if (trace) { 103110207Sandreas.hansson@arm.com 103210618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank, 103310432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 103410432SOmar.Naji@arm.com timeStampOffset); 103510432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 103610618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 103710432SOmar.Naji@arm.com } 103810208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 103910208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 104010208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 104110208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 104210208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 104310208Sandreas.hansson@arm.com // the (last) precharge takes place 104410618SOmar.Naji@arm.com if (!rank_ref.prechargeEvent.scheduled()) 104510618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 104610618SOmar.Naji@arm.com else if (rank_ref.prechargeEvent.when() < pre_done_at) 104710618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 104810207Sandreas.hansson@arm.com} 104910207Sandreas.hansson@arm.com 105010207Sandreas.hansson@arm.comvoid 105110146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10529243SN/A{ 10539243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10549243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10559243SN/A 105610618SOmar.Naji@arm.com // get the rank 105710618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 105810618SOmar.Naji@arm.com 105910211Sandreas.hansson@arm.com // get the bank 10609967SN/A Bank& bank = dram_pkt->bankRef; 10619243SN/A 106210211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 106310211Sandreas.hansson@arm.com bool row_hit = true; 106410211Sandreas.hansson@arm.com 106510211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 106610211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 106710211Sandreas.hansson@arm.com 106810211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 106910211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 107010211Sandreas.hansson@arm.com // nothing to do 107110209Sandreas.hansson@arm.com } else { 107210211Sandreas.hansson@arm.com row_hit = false; 107310211Sandreas.hansson@arm.com 107410209Sandreas.hansson@arm.com // If there is a page open, precharge it. 107510209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 107610618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 10779488SN/A } 10789973SN/A 107910211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 108010211Sandreas.hansson@arm.com // page 108110211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10829973SN/A 108310210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 108410210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 108510618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 108610210Sandreas.hansson@arm.com 108710211Sandreas.hansson@arm.com // issue the command as early as possible 108810211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 108910209Sandreas.hansson@arm.com } 109010209Sandreas.hansson@arm.com 109110211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 109210211Sandreas.hansson@arm.com // the command 109310211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 109410211Sandreas.hansson@arm.com 109510211Sandreas.hansson@arm.com // update the packet ready time 109610211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 109710211Sandreas.hansson@arm.com 109810211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 109910211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 110010211Sandreas.hansson@arm.com 110110394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 110210394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 110310394Swendy.elsasser@arm.com Tick cmd_dly; 110410394Swendy.elsasser@arm.com for(int j = 0; j < ranksPerChannel; j++) { 110510394Swendy.elsasser@arm.com for(int i = 0; i < banksPerRank; i++) { 110610394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 110710394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 110810394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 110910394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 111010618SOmar.Naji@arm.com if (bankGroupArch && 111110618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 111210394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 111310394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 111410394Swendy.elsasser@arm.com // Use tCCD_L in this case 111510394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 111610394Swendy.elsasser@arm.com } else { 111710394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 111810394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 111910394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 112010394Swendy.elsasser@arm.com // 2) bank is in a different bank group 112110394Swendy.elsasser@arm.com cmd_dly = tBURST; 112210394Swendy.elsasser@arm.com } 112310394Swendy.elsasser@arm.com } else { 112410394Swendy.elsasser@arm.com // different rank is by default in a different bank group 112510394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 112610394Swendy.elsasser@arm.com // cas-to-cas delay in this case 112710394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 112810394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 112910394Swendy.elsasser@arm.com } 113010618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 113110618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt); 113210394Swendy.elsasser@arm.com } 113310394Swendy.elsasser@arm.com } 113410211Sandreas.hansson@arm.com 113510393Swendy.elsasser@arm.com // Save rank of current access 113610393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 113710393Swendy.elsasser@arm.com 113810212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 113910212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 114010212Sandreas.hansson@arm.com // read to precharge constraint 114110212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 114210212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 114310212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 114410210Sandreas.hansson@arm.com 114510209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 114610209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 114710209Sandreas.hansson@arm.com ++bank.rowAccesses; 114810209Sandreas.hansson@arm.com 114910209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 115010209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 115110209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 115210209Sandreas.hansson@arm.com 115310209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 115410209Sandreas.hansson@arm.com // auto-precharge 115510209Sandreas.hansson@arm.com if (!auto_precharge && 115610209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 115710209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 115810209Sandreas.hansson@arm.com // a twist on the open and close page policies: 115910209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 116010209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 116110209Sandreas.hansson@arm.com // are bank conflicts in the queue 116210209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 116310209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 116410209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 116510209Sandreas.hansson@arm.com // are no same page hits in the queue 116610209Sandreas.hansson@arm.com bool got_more_hits = false; 116710209Sandreas.hansson@arm.com bool got_bank_conflict = false; 116810209Sandreas.hansson@arm.com 116910209Sandreas.hansson@arm.com // either look at the read queue or write queue 117010209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 117110209Sandreas.hansson@arm.com writeQueue; 117210209Sandreas.hansson@arm.com auto p = queue.begin(); 117310209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 117410209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 117510209Sandreas.hansson@arm.com ++p; 117610209Sandreas.hansson@arm.com 117710809Srb639@drexel.edu // keep on looking until we find a hit or reach the end of the queue 117810809Srb639@drexel.edu // 1) if a hit is found, then both open and close adaptive policies keep 117910809Srb639@drexel.edu // the page open 118010809Srb639@drexel.edu // 2) if no hit is found, got_bank_conflict is set to true if a bank 118110809Srb639@drexel.edu // conflict request is waiting in the queue 118210809Srb639@drexel.edu while (!got_more_hits && p != queue.end()) { 118310209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 118410209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 118510209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 118610209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 118710209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11889973SN/A ++p; 118910141SN/A } 119010141SN/A 119110209Sandreas.hansson@arm.com // auto pre-charge when either 119210209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 119310209Sandreas.hansson@arm.com // have a bank conflict 119410209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 119510209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 119610209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 119710209Sandreas.hansson@arm.com } 119810142SN/A 119910247Sandreas.hansson@arm.com // DRAMPower trace command to be written 120010247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 120110247Sandreas.hansson@arm.com 120210432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 120310432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 120410432SOmar.Naji@arm.com MemCommand::WR; 120510432SOmar.Naji@arm.com 120610209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 120710209Sandreas.hansson@arm.com // closing the row 120810209Sandreas.hansson@arm.com if (auto_precharge) { 120910432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 121010432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 121110618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12129973SN/A 121310209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 121410209Sandreas.hansson@arm.com } 12159963SN/A 12169243SN/A // Update bus state 12179243SN/A busBusyUntil = dram_pkt->readyTime; 12189243SN/A 121910211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 122010211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 12219243SN/A 122210618SOmar.Naji@arm.com dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank, 122310432SOmar.Naji@arm.com divCeil(cmd_at, tCK) - 122410432SOmar.Naji@arm.com timeStampOffset); 122510432SOmar.Naji@arm.com 122610432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 122710432SOmar.Naji@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 122810247Sandreas.hansson@arm.com 122910206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 123010206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 123110206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 123210206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 123310206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12349972SN/A 123510206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12369977SN/A if (dram_pkt->isRead) { 123710147Sandreas.hansson@arm.com ++readsThisTime; 123810211Sandreas.hansson@arm.com if (row_hit) 12399977SN/A readRowHits++; 12409977SN/A bytesReadDRAM += burstSize; 12419977SN/A perBankRdBursts[dram_pkt->bankId]++; 124210206Sandreas.hansson@arm.com 124310206Sandreas.hansson@arm.com // Update latency stats 124410206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 124510206Sandreas.hansson@arm.com totBusLat += tBURST; 124610211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12479977SN/A } else { 124810147Sandreas.hansson@arm.com ++writesThisTime; 124910211Sandreas.hansson@arm.com if (row_hit) 12509977SN/A writeRowHits++; 12519977SN/A bytesWritten += burstSize; 12529977SN/A perBankWrBursts[dram_pkt->bankId]++; 12539243SN/A } 12549243SN/A} 12559243SN/A 12569243SN/Avoid 125710206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12589243SN/A{ 125910618SOmar.Naji@arm.com int busyRanks = 0; 126010618SOmar.Naji@arm.com for (auto r : ranks) { 126110618SOmar.Naji@arm.com if (!r->isAvailable()) { 126210618SOmar.Naji@arm.com // rank is busy refreshing 126310618SOmar.Naji@arm.com busyRanks++; 126410618SOmar.Naji@arm.com 126510618SOmar.Naji@arm.com // let the rank know that if it was waiting to drain, it 126610618SOmar.Naji@arm.com // is now done and ready to proceed 126710618SOmar.Naji@arm.com r->checkDrainDone(); 126810618SOmar.Naji@arm.com } 126910618SOmar.Naji@arm.com } 127010618SOmar.Naji@arm.com 127110618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 127210618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 127310618SOmar.Naji@arm.com // and stall this state machine without taking any further 127410618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 127510618SOmar.Naji@arm.com return; 127610618SOmar.Naji@arm.com } 127710618SOmar.Naji@arm.com 127810393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 127910393Swendy.elsasser@arm.com // or WRITE_TO_READ state 128010393Swendy.elsasser@arm.com bool switched_cmd_type = false; 128110206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 128210206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 128310206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12849243SN/A 128510206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 128610206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 128710206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 128810206Sandreas.hansson@arm.com readsThisTime = 0; 128910206Sandreas.hansson@arm.com 129010206Sandreas.hansson@arm.com // now proceed to do the actual writes 129110206Sandreas.hansson@arm.com busState = WRITE; 129210393Swendy.elsasser@arm.com switched_cmd_type = true; 129310206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 129410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 129510206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 129610206Sandreas.hansson@arm.com 129710206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 129810206Sandreas.hansson@arm.com writesThisTime = 0; 129910206Sandreas.hansson@arm.com 130010206Sandreas.hansson@arm.com busState = READ; 130110393Swendy.elsasser@arm.com switched_cmd_type = true; 130210206Sandreas.hansson@arm.com } 130310206Sandreas.hansson@arm.com 130410206Sandreas.hansson@arm.com // when we get here it is either a read or a write 130510206Sandreas.hansson@arm.com if (busState == READ) { 130610206Sandreas.hansson@arm.com 130710206Sandreas.hansson@arm.com // track if we should switch or not 130810206Sandreas.hansson@arm.com bool switch_to_writes = false; 130910206Sandreas.hansson@arm.com 131010206Sandreas.hansson@arm.com if (readQueue.empty()) { 131110206Sandreas.hansson@arm.com // In the case there is no read request to go next, 131210206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 131310206Sandreas.hansson@arm.com // if we are draining) 131410206Sandreas.hansson@arm.com if (!writeQueue.empty() && 131510206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 131610206Sandreas.hansson@arm.com 131710206Sandreas.hansson@arm.com switch_to_writes = true; 131810206Sandreas.hansson@arm.com } else { 131910206Sandreas.hansson@arm.com // check if we are drained 132010206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 132110509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 132210206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 132310206Sandreas.hansson@arm.com drainManager = NULL; 132410206Sandreas.hansson@arm.com } 132510206Sandreas.hansson@arm.com 132610206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 132710206Sandreas.hansson@arm.com // event for the next request 132810206Sandreas.hansson@arm.com return; 132910206Sandreas.hansson@arm.com } 133010206Sandreas.hansson@arm.com } else { 133110618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 133210618SOmar.Naji@arm.com bool found_read = false; 133310618SOmar.Naji@arm.com 133410206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 133510206Sandreas.hansson@arm.com // front of the read queue 133610618SOmar.Naji@arm.com found_read = chooseNext(readQueue, switched_cmd_type); 133710618SOmar.Naji@arm.com 133810618SOmar.Naji@arm.com // if no read to an available rank is found then return 133910618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 134010618SOmar.Naji@arm.com // which are above the required threshold. However, to 134110618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 134210618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 134310618SOmar.Naji@arm.com if (!found_read) 134410618SOmar.Naji@arm.com return; 134510206Sandreas.hansson@arm.com 134610215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 134710618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 134810393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 134910393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 135010393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 135110393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 135210393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 135310394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 135410394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 135510393Swendy.elsasser@arm.com } 135610393Swendy.elsasser@arm.com 135710215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 135810206Sandreas.hansson@arm.com 135910206Sandreas.hansson@arm.com // At this point we're done dealing with the request 136010215Sandreas.hansson@arm.com readQueue.pop_front(); 136110215Sandreas.hansson@arm.com 136210215Sandreas.hansson@arm.com // sanity check 136310215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 136410215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 136510215Sandreas.hansson@arm.com 136610215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 136710215Sandreas.hansson@arm.com // requestor at its readyTime 136810215Sandreas.hansson@arm.com if (respQueue.empty()) { 136910215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 137010215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 137110215Sandreas.hansson@arm.com } else { 137210215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 137310215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 137410215Sandreas.hansson@arm.com } 137510215Sandreas.hansson@arm.com 137610215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 137710206Sandreas.hansson@arm.com 137810206Sandreas.hansson@arm.com // we have so many writes that we have to transition 137910206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 138010206Sandreas.hansson@arm.com switch_to_writes = true; 138110206Sandreas.hansson@arm.com } 138210206Sandreas.hansson@arm.com } 138310206Sandreas.hansson@arm.com 138410206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 138510206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 138610206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 138710206Sandreas.hansson@arm.com if (switch_to_writes) { 138810206Sandreas.hansson@arm.com // transition to writing 138910206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 139010206Sandreas.hansson@arm.com } 13919352SN/A } else { 139210618SOmar.Naji@arm.com // bool to check if write to free rank is found 139310618SOmar.Naji@arm.com bool found_write = false; 139410618SOmar.Naji@arm.com 139510618SOmar.Naji@arm.com found_write = chooseNext(writeQueue, switched_cmd_type); 139610618SOmar.Naji@arm.com 139710618SOmar.Naji@arm.com // if no writes to an available rank are found then return. 139810618SOmar.Naji@arm.com // There could be reads to the available ranks. However, to avoid 139910618SOmar.Naji@arm.com // adding more complexity to the code, return at this point and wait 140010618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 140110618SOmar.Naji@arm.com if (!found_write) 140210618SOmar.Naji@arm.com return; 140310618SOmar.Naji@arm.com 140410206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 140510618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 140610206Sandreas.hansson@arm.com // sanity check 140710206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 140810393Swendy.elsasser@arm.com 140910394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 141010394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 141110394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 141210394Swendy.elsasser@arm.com // applied to colAllowedAt 141310394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 141410394Swendy.elsasser@arm.com busBusyUntil += tRTW; 141510393Swendy.elsasser@arm.com } 141610393Swendy.elsasser@arm.com 141710206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 141810206Sandreas.hansson@arm.com 141910206Sandreas.hansson@arm.com writeQueue.pop_front(); 142010206Sandreas.hansson@arm.com delete dram_pkt; 142110206Sandreas.hansson@arm.com 142210206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 142310206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 142410206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 142510206Sandreas.hansson@arm.com // writes, then switch to reads. 142610206Sandreas.hansson@arm.com if (writeQueue.empty() || 142710206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 142810206Sandreas.hansson@arm.com !drainManager) || 142910206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 143010206Sandreas.hansson@arm.com // turn the bus back around for reads again 143110206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 143210206Sandreas.hansson@arm.com 143310206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 143410206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 143510206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 143610206Sandreas.hansson@arm.com // nothing to do 143710206Sandreas.hansson@arm.com } 143810206Sandreas.hansson@arm.com } 143910618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 144010618SOmar.Naji@arm.com // action before reaching this point. 144110618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 144210618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 144310206Sandreas.hansson@arm.com 144410206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 144510206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 144610206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 144710206Sandreas.hansson@arm.com // the next request processing 144810206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 144910206Sandreas.hansson@arm.com retryWrReq = false; 145010713Sandreas.hansson@arm.com port.sendRetryReq(); 14519352SN/A } 14529243SN/A} 14539243SN/A 14549967SN/Auint64_t 145510393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 145610393Swendy.elsasser@arm.com bool switched_cmd_type) const 14579967SN/A{ 14589967SN/A uint64_t bank_mask = 0; 145910211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 14609967SN/A 146110393Swendy.elsasser@arm.com uint64_t bank_mask_same_rank = 0; 146210393Swendy.elsasser@arm.com Tick min_act_at_same_rank = MaxTick; 146310393Swendy.elsasser@arm.com 146410393Swendy.elsasser@arm.com // Give precedence to commands that access same rank as previous command 146510393Swendy.elsasser@arm.com bool same_rank_match = false; 146610393Swendy.elsasser@arm.com 146710393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 14689967SN/A // bank in question 14699967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 147010618SOmar.Naji@arm.com for (const auto& p : queue) { 147110618SOmar.Naji@arm.com if(p->rankRef.isAvailable()) 147210618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 14739967SN/A } 14749967SN/A 14759967SN/A for (int i = 0; i < ranksPerChannel; i++) { 14769967SN/A for (int j = 0; j < banksPerRank; j++) { 147710618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 147810211Sandreas.hansson@arm.com 14799967SN/A // if we have waiting requests for the bank, and it is 14809967SN/A // amongst the first available, update the mask 148110211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 148210618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 148310618SOmar.Naji@arm.com assert(ranks[i]->isAvailable()); 148410211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 148510211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 148610393Swendy.elsasser@arm.com // cost in this calculation 148710618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 148810618SOmar.Naji@arm.com ranks[i]->banks[j].actAllowedAt : 148910618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 149010211Sandreas.hansson@arm.com 149110393Swendy.elsasser@arm.com // prioritize commands that access the 149210393Swendy.elsasser@arm.com // same rank as previous burst 149310393Swendy.elsasser@arm.com // Calculate bank mask separately for the case and 149410393Swendy.elsasser@arm.com // evaluate after loop iterations complete 149510393Swendy.elsasser@arm.com if (i == activeRank && ranksPerChannel > 1) { 149610393Swendy.elsasser@arm.com if (act_at <= min_act_at_same_rank) { 149710393Swendy.elsasser@arm.com // reset same rank bank mask if new minimum is found 149810393Swendy.elsasser@arm.com // and previous minimum could not immediately send ACT 149910393Swendy.elsasser@arm.com if (act_at < min_act_at_same_rank && 150010393Swendy.elsasser@arm.com min_act_at_same_rank > curTick()) 150110393Swendy.elsasser@arm.com bank_mask_same_rank = 0; 150210393Swendy.elsasser@arm.com 150310393Swendy.elsasser@arm.com // Set flag indicating that a same rank 150410393Swendy.elsasser@arm.com // opportunity was found 150510393Swendy.elsasser@arm.com same_rank_match = true; 150610393Swendy.elsasser@arm.com 150710393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 150810393Swendy.elsasser@arm.com replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 150910393Swendy.elsasser@arm.com min_act_at_same_rank = act_at; 151010393Swendy.elsasser@arm.com } 151110393Swendy.elsasser@arm.com } else { 151210393Swendy.elsasser@arm.com if (act_at <= min_act_at) { 151310393Swendy.elsasser@arm.com // reset bank mask if new minimum is found 151410393Swendy.elsasser@arm.com // and either previous minimum could not immediately send ACT 151510393Swendy.elsasser@arm.com if (act_at < min_act_at && min_act_at > curTick()) 151610393Swendy.elsasser@arm.com bank_mask = 0; 151710393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 151810393Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 151910393Swendy.elsasser@arm.com min_act_at = act_at; 152010393Swendy.elsasser@arm.com } 152110211Sandreas.hansson@arm.com } 15229967SN/A } 15239967SN/A } 15249967SN/A } 152510211Sandreas.hansson@arm.com 152610393Swendy.elsasser@arm.com // Determine the earliest time when the next burst can issue based 152710393Swendy.elsasser@arm.com // on the current busBusyUntil delay. 152810393Swendy.elsasser@arm.com // Offset by tRCD to correlate with ACT timing variables 152910393Swendy.elsasser@arm.com Tick min_cmd_at = busBusyUntil - tCL - tRCD; 153010393Swendy.elsasser@arm.com 153110617SOmar.Naji@arm.com // if we have multiple ranks and all 153210617SOmar.Naji@arm.com // waiting packets are accessing a rank which was previously active 153310617SOmar.Naji@arm.com // then bank_mask_same_rank will be set to a value while bank_mask will 153410617SOmar.Naji@arm.com // remain 0. In this case, the function should return the value of 153510617SOmar.Naji@arm.com // bank_mask_same_rank. 153610617SOmar.Naji@arm.com // else if waiting packets access a rank which was previously active and 153710617SOmar.Naji@arm.com // other ranks, prioritize same rank accesses that can issue B2B 153810393Swendy.elsasser@arm.com // Only optimize for same ranks when the command type 153910393Swendy.elsasser@arm.com // does not change; do not want to unnecessarily incur tWTR 154010393Swendy.elsasser@arm.com // 154110393Swendy.elsasser@arm.com // Resulting FCFS prioritization Order is: 154210393Swendy.elsasser@arm.com // 1) Commands that access the same rank as previous burst 154310393Swendy.elsasser@arm.com // and can prep the bank seamlessly. 154410393Swendy.elsasser@arm.com // 2) Commands (any rank) with earliest bank prep 154510617SOmar.Naji@arm.com if ((bank_mask == 0) || (!switched_cmd_type && same_rank_match && 154610617SOmar.Naji@arm.com min_act_at_same_rank <= min_cmd_at)) { 154710393Swendy.elsasser@arm.com bank_mask = bank_mask_same_rank; 154810393Swendy.elsasser@arm.com } 154910393Swendy.elsasser@arm.com 15509967SN/A return bank_mask; 15519967SN/A} 15529967SN/A 155310618SOmar.Naji@arm.comDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p) 155410618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 155510618SOmar.Naji@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0), 155610618SOmar.Naji@arm.com refreshState(REF_IDLE), refreshDueAt(0), 155710618SOmar.Naji@arm.com power(_p, false), numBanksActive(0), 155810618SOmar.Naji@arm.com activateEvent(*this), prechargeEvent(*this), 155910618SOmar.Naji@arm.com refreshEvent(*this), powerEvent(*this) 156010618SOmar.Naji@arm.com{ } 156110618SOmar.Naji@arm.com 15629243SN/Avoid 156310618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 156410618SOmar.Naji@arm.com{ 156510618SOmar.Naji@arm.com assert(ref_tick > curTick()); 156610618SOmar.Naji@arm.com 156710618SOmar.Naji@arm.com pwrStateTick = curTick(); 156810618SOmar.Naji@arm.com 156910618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 157010618SOmar.Naji@arm.com // precharge 157110618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 157210618SOmar.Naji@arm.com} 157310618SOmar.Naji@arm.com 157410618SOmar.Naji@arm.comvoid 157510619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 157610619Sandreas.hansson@arm.com{ 157710619Sandreas.hansson@arm.com deschedule(refreshEvent); 157810619Sandreas.hansson@arm.com} 157910619Sandreas.hansson@arm.com 158010619Sandreas.hansson@arm.comvoid 158110618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 158210618SOmar.Naji@arm.com{ 158310618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 158410618SOmar.Naji@arm.com // precharge 158510618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 158610618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 158710618SOmar.Naji@arm.com 158810618SOmar.Naji@arm.com refreshState = REF_PRE; 158910618SOmar.Naji@arm.com 159010618SOmar.Naji@arm.com // hand control back to the refresh event loop 159110618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 159210618SOmar.Naji@arm.com } 159310618SOmar.Naji@arm.com} 159410618SOmar.Naji@arm.com 159510618SOmar.Naji@arm.comvoid 159610618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 159710618SOmar.Naji@arm.com{ 159810618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 159910618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 160010618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 160110618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 160210618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 160310618SOmar.Naji@arm.com} 160410618SOmar.Naji@arm.com 160510618SOmar.Naji@arm.comvoid 160610618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 160710618SOmar.Naji@arm.com{ 160810618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 160910618SOmar.Naji@arm.com // if all banks are precharged for the power models 161010618SOmar.Naji@arm.com if (numBanksActive == 0) { 161110618SOmar.Naji@arm.com // we should transition to the idle state when the last bank 161210618SOmar.Naji@arm.com // is precharged 161310618SOmar.Naji@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 161410618SOmar.Naji@arm.com } 161510618SOmar.Naji@arm.com} 161610618SOmar.Naji@arm.com 161710618SOmar.Naji@arm.comvoid 161810618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 16199243SN/A{ 162010207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 162110207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 162210207Sandreas.hansson@arm.com // remember when the refresh is due 162310207Sandreas.hansson@arm.com refreshDueAt = curTick(); 16249243SN/A 162510207Sandreas.hansson@arm.com // proceed to drain 162610207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 16279243SN/A 162810207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 162910207Sandreas.hansson@arm.com } 163010207Sandreas.hansson@arm.com 163110618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 163210618SOmar.Naji@arm.com // after which it will 163310207Sandreas.hansson@arm.com // hand control back to this event loop 163410207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 163510618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 163610618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 163710618SOmar.Naji@arm.com if ((rank == memory.activeRank) 163810618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 163910207Sandreas.hansson@arm.com // hand control over to the request loop until it is 164010207Sandreas.hansson@arm.com // evaluated next 164110207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 164210207Sandreas.hansson@arm.com 164310207Sandreas.hansson@arm.com return; 164410207Sandreas.hansson@arm.com } else { 164510207Sandreas.hansson@arm.com refreshState = REF_PRE; 164610207Sandreas.hansson@arm.com } 164710207Sandreas.hansson@arm.com } 164810207Sandreas.hansson@arm.com 164910207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 165010207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 165110208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 165210208Sandreas.hansson@arm.com // state 165310208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 165410214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 165510214Sandreas.hansson@arm.com // only a single bank open 165610208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 165710214Sandreas.hansson@arm.com 165810214Sandreas.hansson@arm.com // first determine when we can precharge 165910214Sandreas.hansson@arm.com Tick pre_at = curTick(); 166010618SOmar.Naji@arm.com 166110618SOmar.Naji@arm.com for (auto &b : banks) { 166210618SOmar.Naji@arm.com // respect both causality and any existing bank 166310618SOmar.Naji@arm.com // constraints, some banks could already have a 166410618SOmar.Naji@arm.com // (auto) precharge scheduled 166510618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 166610618SOmar.Naji@arm.com } 166710618SOmar.Naji@arm.com 166810618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 166910618SOmar.Naji@arm.com // already are, update their availability 167010618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 167110618SOmar.Naji@arm.com 167210618SOmar.Naji@arm.com for (auto &b : banks) { 167310618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 167410618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 167510618SOmar.Naji@arm.com } else { 167610618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 167710618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 167810214Sandreas.hansson@arm.com } 167910214Sandreas.hansson@arm.com } 168010214Sandreas.hansson@arm.com 168110618SOmar.Naji@arm.com // precharge all banks in rank 168210618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::PREA, 0, 168310618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 168410618SOmar.Naji@arm.com memory.timeStampOffset); 168510214Sandreas.hansson@arm.com 168610618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 168710618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 168810618SOmar.Naji@arm.com memory.timeStampOffset, rank); 168910208Sandreas.hansson@arm.com } else { 169010208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 169110208Sandreas.hansson@arm.com 169210208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 169310208Sandreas.hansson@arm.com // we are already idle 169410208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 16959975SN/A } 16969975SN/A 169710208Sandreas.hansson@arm.com refreshState = REF_RUN; 169810208Sandreas.hansson@arm.com assert(numBanksActive == 0); 16999243SN/A 170010208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 170110208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 170210208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 170310208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 170410207Sandreas.hansson@arm.com return; 170510207Sandreas.hansson@arm.com } 170610207Sandreas.hansson@arm.com 170710207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 170810207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 170910207Sandreas.hansson@arm.com // should never get here with any banks active 171010207Sandreas.hansson@arm.com assert(numBanksActive == 0); 171110208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 171210207Sandreas.hansson@arm.com 171310618SOmar.Naji@arm.com Tick ref_done_at = curTick() + memory.tRFC; 171410207Sandreas.hansson@arm.com 171510618SOmar.Naji@arm.com for (auto &b : banks) { 171610618SOmar.Naji@arm.com b.actAllowedAt = ref_done_at; 171710618SOmar.Naji@arm.com } 171810247Sandreas.hansson@arm.com 171910618SOmar.Naji@arm.com // at the moment this affects all ranks 172010618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::REF, 0, 172110618SOmar.Naji@arm.com divCeil(curTick(), memory.tCK) - 172210618SOmar.Naji@arm.com memory.timeStampOffset); 172310432SOmar.Naji@arm.com 172410618SOmar.Naji@arm.com // at the moment sort the list of commands and update the counters 172510618SOmar.Naji@arm.com // for DRAMPower libray when doing a refresh 172610618SOmar.Naji@arm.com sort(power.powerlib.cmdList.begin(), 172710618SOmar.Naji@arm.com power.powerlib.cmdList.end(), DRAMCtrl::sortTime); 172810432SOmar.Naji@arm.com 172910618SOmar.Naji@arm.com // update the counters for DRAMPower, passing false to 173010618SOmar.Naji@arm.com // indicate that this is not the last command in the 173110618SOmar.Naji@arm.com // list. DRAMPower requires this information for the 173210618SOmar.Naji@arm.com // correct calculation of the background energy at the end 173310618SOmar.Naji@arm.com // of the simulation. Ideally we would want to call this 173410618SOmar.Naji@arm.com // function with true once at the end of the 173510618SOmar.Naji@arm.com // simulation. However, the discarded energy is extremly 173610618SOmar.Naji@arm.com // small and does not effect the final results. 173710618SOmar.Naji@arm.com power.powerlib.updateCounters(false); 173810432SOmar.Naji@arm.com 173910618SOmar.Naji@arm.com // call the energy function 174010618SOmar.Naji@arm.com power.powerlib.calcEnergy(); 174110432SOmar.Naji@arm.com 174210618SOmar.Naji@arm.com // Update the stats 174310618SOmar.Naji@arm.com updatePowerStats(); 174410432SOmar.Naji@arm.com 174510618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 174610618SOmar.Naji@arm.com memory.timeStampOffset, rank); 174710207Sandreas.hansson@arm.com 174810207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 174910207Sandreas.hansson@arm.com // for it 175010618SOmar.Naji@arm.com if (refreshDueAt + memory.tREFI < ref_done_at) { 175110207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 175210207Sandreas.hansson@arm.com } 175310207Sandreas.hansson@arm.com 175410207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 175510207Sandreas.hansson@arm.com // when scheduling the next one 175610618SOmar.Naji@arm.com schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP); 175710207Sandreas.hansson@arm.com 175810208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 175910207Sandreas.hansson@arm.com 176010208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 176110208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 176210208Sandreas.hansson@arm.com // idle state 176310211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 176410207Sandreas.hansson@arm.com 176510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 176610618SOmar.Naji@arm.com ref_done_at, refreshDueAt + memory.tREFI); 176710208Sandreas.hansson@arm.com } 176810208Sandreas.hansson@arm.com} 176910208Sandreas.hansson@arm.com 177010208Sandreas.hansson@arm.comvoid 177110618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 177210208Sandreas.hansson@arm.com{ 177310208Sandreas.hansson@arm.com // respect causality 177410208Sandreas.hansson@arm.com assert(tick >= curTick()); 177510208Sandreas.hansson@arm.com 177610208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 177710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 177810208Sandreas.hansson@arm.com tick, pwr_state); 177910208Sandreas.hansson@arm.com 178010208Sandreas.hansson@arm.com // insert the new transition 178110208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 178210208Sandreas.hansson@arm.com 178310208Sandreas.hansson@arm.com schedule(powerEvent, tick); 178410208Sandreas.hansson@arm.com } else { 178510208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 178610208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 178710208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 178810208Sandreas.hansson@arm.com } 178910208Sandreas.hansson@arm.com} 179010208Sandreas.hansson@arm.com 179110208Sandreas.hansson@arm.comvoid 179210618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 179310208Sandreas.hansson@arm.com{ 179410208Sandreas.hansson@arm.com // remember where we were, and for how long 179510208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 179610208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 179710208Sandreas.hansson@arm.com 179810208Sandreas.hansson@arm.com // update the accounting 179910208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 180010208Sandreas.hansson@arm.com 180110208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 180210208Sandreas.hansson@arm.com pwrStateTick = curTick(); 180310208Sandreas.hansson@arm.com 180410208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 180510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 180610208Sandreas.hansson@arm.com 180710208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 180810208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 180910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 181010208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 181110208Sandreas.hansson@arm.com 181210208Sandreas.hansson@arm.com // kick things into action again 181310208Sandreas.hansson@arm.com refreshState = REF_IDLE; 181410618SOmar.Naji@arm.com // a request event could be already scheduled by the state 181510618SOmar.Naji@arm.com // machine of the other rank 181610618SOmar.Naji@arm.com if (!memory.nextReqEvent.scheduled()) 181710618SOmar.Naji@arm.com schedule(memory.nextReqEvent, curTick()); 181810208Sandreas.hansson@arm.com } else { 181910208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 182010208Sandreas.hansson@arm.com 182110208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 182210208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 182310208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 182410208Sandreas.hansson@arm.com // there should be nothing waiting at this point 182510208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 182610208Sandreas.hansson@arm.com 182710208Sandreas.hansson@arm.com // update the state in zero time and proceed below 182810208Sandreas.hansson@arm.com pwrState = PWR_REF; 182910208Sandreas.hansson@arm.com } 183010208Sandreas.hansson@arm.com } 183110208Sandreas.hansson@arm.com } 183210208Sandreas.hansson@arm.com 183310208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 183410208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 183510208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 183610208Sandreas.hansson@arm.com // following refresh 183710208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 183810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 183910208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 184010208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 184110208Sandreas.hansson@arm.com // state once the refresh is done 184210208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 184310208Sandreas.hansson@arm.com processRefreshEvent(); 184410207Sandreas.hansson@arm.com } 18459243SN/A} 18469243SN/A 18479243SN/Avoid 184810618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 184910432SOmar.Naji@arm.com{ 185010432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 185110432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 185210618SOmar.Naji@arm.com power.powerlib.getEnergy(); 185310618SOmar.Naji@arm.com Data::MemoryPowerModel::Power rank_power = 185410618SOmar.Naji@arm.com power.powerlib.getPower(); 185510432SOmar.Naji@arm.com 185610618SOmar.Naji@arm.com actEnergy = energy.act_energy * memory.devicesPerRank; 185710618SOmar.Naji@arm.com preEnergy = energy.pre_energy * memory.devicesPerRank; 185810618SOmar.Naji@arm.com readEnergy = energy.read_energy * memory.devicesPerRank; 185910618SOmar.Naji@arm.com writeEnergy = energy.write_energy * memory.devicesPerRank; 186010618SOmar.Naji@arm.com refreshEnergy = energy.ref_energy * memory.devicesPerRank; 186110618SOmar.Naji@arm.com actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 186210618SOmar.Naji@arm.com preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 186310618SOmar.Naji@arm.com totalEnergy = energy.total_energy * memory.devicesPerRank; 186410618SOmar.Naji@arm.com averagePower = rank_power.average_power * memory.devicesPerRank; 186510432SOmar.Naji@arm.com} 186610432SOmar.Naji@arm.com 186710432SOmar.Naji@arm.comvoid 186810618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 186910618SOmar.Naji@arm.com{ 187010618SOmar.Naji@arm.com using namespace Stats; 187110618SOmar.Naji@arm.com 187210618SOmar.Naji@arm.com pwrStateTime 187310618SOmar.Naji@arm.com .init(5) 187410618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 187510618SOmar.Naji@arm.com .desc("Time in different power states"); 187610618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 187710618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 187810618SOmar.Naji@arm.com pwrStateTime.subname(2, "PRE_PDN"); 187910618SOmar.Naji@arm.com pwrStateTime.subname(3, "ACT"); 188010618SOmar.Naji@arm.com pwrStateTime.subname(4, "ACT_PDN"); 188110618SOmar.Naji@arm.com 188210618SOmar.Naji@arm.com actEnergy 188310618SOmar.Naji@arm.com .name(name() + ".actEnergy") 188410618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 188510618SOmar.Naji@arm.com 188610618SOmar.Naji@arm.com preEnergy 188710618SOmar.Naji@arm.com .name(name() + ".preEnergy") 188810618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 188910618SOmar.Naji@arm.com 189010618SOmar.Naji@arm.com readEnergy 189110618SOmar.Naji@arm.com .name(name() + ".readEnergy") 189210618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 189310618SOmar.Naji@arm.com 189410618SOmar.Naji@arm.com writeEnergy 189510618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 189610618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 189710618SOmar.Naji@arm.com 189810618SOmar.Naji@arm.com refreshEnergy 189910618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 190010618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 190110618SOmar.Naji@arm.com 190210618SOmar.Naji@arm.com actBackEnergy 190310618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 190410618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 190510618SOmar.Naji@arm.com 190610618SOmar.Naji@arm.com preBackEnergy 190710618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 190810618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 190910618SOmar.Naji@arm.com 191010618SOmar.Naji@arm.com totalEnergy 191110618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 191210618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 191310618SOmar.Naji@arm.com 191410618SOmar.Naji@arm.com averagePower 191510618SOmar.Naji@arm.com .name(name() + ".averagePower") 191610618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 191710618SOmar.Naji@arm.com} 191810618SOmar.Naji@arm.comvoid 191910146Sandreas.hansson@arm.comDRAMCtrl::regStats() 19209243SN/A{ 19219243SN/A using namespace Stats; 19229243SN/A 19239243SN/A AbstractMemory::regStats(); 19249243SN/A 192510618SOmar.Naji@arm.com for (auto r : ranks) { 192610618SOmar.Naji@arm.com r->regStats(); 192710618SOmar.Naji@arm.com } 192810618SOmar.Naji@arm.com 19299243SN/A readReqs 19309243SN/A .name(name() + ".readReqs") 19319977SN/A .desc("Number of read requests accepted"); 19329243SN/A 19339243SN/A writeReqs 19349243SN/A .name(name() + ".writeReqs") 19359977SN/A .desc("Number of write requests accepted"); 19369831SN/A 19379831SN/A readBursts 19389831SN/A .name(name() + ".readBursts") 19399977SN/A .desc("Number of DRAM read bursts, " 19409977SN/A "including those serviced by the write queue"); 19419831SN/A 19429831SN/A writeBursts 19439831SN/A .name(name() + ".writeBursts") 19449977SN/A .desc("Number of DRAM write bursts, " 19459977SN/A "including those merged in the write queue"); 19469243SN/A 19479243SN/A servicedByWrQ 19489243SN/A .name(name() + ".servicedByWrQ") 19499977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 19509977SN/A 19519977SN/A mergedWrBursts 19529977SN/A .name(name() + ".mergedWrBursts") 19539977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 19549243SN/A 19559243SN/A neitherReadNorWrite 19569977SN/A .name(name() + ".neitherReadNorWriteReqs") 19579977SN/A .desc("Number of requests that are neither read nor write"); 19589243SN/A 19599977SN/A perBankRdBursts 19609243SN/A .init(banksPerRank * ranksPerChannel) 19619977SN/A .name(name() + ".perBankRdBursts") 19629977SN/A .desc("Per bank write bursts"); 19639243SN/A 19649977SN/A perBankWrBursts 19659243SN/A .init(banksPerRank * ranksPerChannel) 19669977SN/A .name(name() + ".perBankWrBursts") 19679977SN/A .desc("Per bank write bursts"); 19689243SN/A 19699243SN/A avgRdQLen 19709243SN/A .name(name() + ".avgRdQLen") 19719977SN/A .desc("Average read queue length when enqueuing") 19729243SN/A .precision(2); 19739243SN/A 19749243SN/A avgWrQLen 19759243SN/A .name(name() + ".avgWrQLen") 19769977SN/A .desc("Average write queue length when enqueuing") 19779243SN/A .precision(2); 19789243SN/A 19799243SN/A totQLat 19809243SN/A .name(name() + ".totQLat") 19819977SN/A .desc("Total ticks spent queuing"); 19829243SN/A 19839243SN/A totBusLat 19849243SN/A .name(name() + ".totBusLat") 19859977SN/A .desc("Total ticks spent in databus transfers"); 19869243SN/A 19879243SN/A totMemAccLat 19889243SN/A .name(name() + ".totMemAccLat") 19899977SN/A .desc("Total ticks spent from burst creation until serviced " 19909977SN/A "by the DRAM"); 19919243SN/A 19929243SN/A avgQLat 19939243SN/A .name(name() + ".avgQLat") 19949977SN/A .desc("Average queueing delay per DRAM burst") 19959243SN/A .precision(2); 19969243SN/A 19979831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 19989243SN/A 19999243SN/A avgBusLat 20009243SN/A .name(name() + ".avgBusLat") 20019977SN/A .desc("Average bus latency per DRAM burst") 20029243SN/A .precision(2); 20039243SN/A 20049831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 20059243SN/A 20069243SN/A avgMemAccLat 20079243SN/A .name(name() + ".avgMemAccLat") 20089977SN/A .desc("Average memory access latency per DRAM burst") 20099243SN/A .precision(2); 20109243SN/A 20119831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 20129243SN/A 20139243SN/A numRdRetry 20149243SN/A .name(name() + ".numRdRetry") 20159977SN/A .desc("Number of times read queue was full causing retry"); 20169243SN/A 20179243SN/A numWrRetry 20189243SN/A .name(name() + ".numWrRetry") 20199977SN/A .desc("Number of times write queue was full causing retry"); 20209243SN/A 20219243SN/A readRowHits 20229243SN/A .name(name() + ".readRowHits") 20239243SN/A .desc("Number of row buffer hits during reads"); 20249243SN/A 20259243SN/A writeRowHits 20269243SN/A .name(name() + ".writeRowHits") 20279243SN/A .desc("Number of row buffer hits during writes"); 20289243SN/A 20299243SN/A readRowHitRate 20309243SN/A .name(name() + ".readRowHitRate") 20319243SN/A .desc("Row buffer hit rate for reads") 20329243SN/A .precision(2); 20339243SN/A 20349831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 20359243SN/A 20369243SN/A writeRowHitRate 20379243SN/A .name(name() + ".writeRowHitRate") 20389243SN/A .desc("Row buffer hit rate for writes") 20399243SN/A .precision(2); 20409243SN/A 20419977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 20429243SN/A 20439243SN/A readPktSize 20449831SN/A .init(ceilLog2(burstSize) + 1) 20459243SN/A .name(name() + ".readPktSize") 20469977SN/A .desc("Read request sizes (log2)"); 20479243SN/A 20489243SN/A writePktSize 20499831SN/A .init(ceilLog2(burstSize) + 1) 20509243SN/A .name(name() + ".writePktSize") 20519977SN/A .desc("Write request sizes (log2)"); 20529243SN/A 20539243SN/A rdQLenPdf 20549567SN/A .init(readBufferSize) 20559243SN/A .name(name() + ".rdQLenPdf") 20569243SN/A .desc("What read queue length does an incoming req see"); 20579243SN/A 20589243SN/A wrQLenPdf 20599567SN/A .init(writeBufferSize) 20609243SN/A .name(name() + ".wrQLenPdf") 20619243SN/A .desc("What write queue length does an incoming req see"); 20629243SN/A 20639727SN/A bytesPerActivate 206410141SN/A .init(maxAccessesPerRow) 20659727SN/A .name(name() + ".bytesPerActivate") 20669727SN/A .desc("Bytes accessed per row activation") 20679727SN/A .flags(nozero); 20689243SN/A 206910147Sandreas.hansson@arm.com rdPerTurnAround 207010147Sandreas.hansson@arm.com .init(readBufferSize) 207110147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 207210147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 207310147Sandreas.hansson@arm.com .flags(nozero); 207410147Sandreas.hansson@arm.com 207510147Sandreas.hansson@arm.com wrPerTurnAround 207610147Sandreas.hansson@arm.com .init(writeBufferSize) 207710147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 207810147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 207910147Sandreas.hansson@arm.com .flags(nozero); 208010147Sandreas.hansson@arm.com 20819975SN/A bytesReadDRAM 20829975SN/A .name(name() + ".bytesReadDRAM") 20839975SN/A .desc("Total number of bytes read from DRAM"); 20849975SN/A 20859975SN/A bytesReadWrQ 20869975SN/A .name(name() + ".bytesReadWrQ") 20879975SN/A .desc("Total number of bytes read from write queue"); 20889243SN/A 20899243SN/A bytesWritten 20909243SN/A .name(name() + ".bytesWritten") 20919977SN/A .desc("Total number of bytes written to DRAM"); 20929243SN/A 20939977SN/A bytesReadSys 20949977SN/A .name(name() + ".bytesReadSys") 20959977SN/A .desc("Total read bytes from the system interface side"); 20969243SN/A 20979977SN/A bytesWrittenSys 20989977SN/A .name(name() + ".bytesWrittenSys") 20999977SN/A .desc("Total written bytes from the system interface side"); 21009243SN/A 21019243SN/A avgRdBW 21029243SN/A .name(name() + ".avgRdBW") 21039977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 21049243SN/A .precision(2); 21059243SN/A 21069977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 21079243SN/A 21089243SN/A avgWrBW 21099243SN/A .name(name() + ".avgWrBW") 21109977SN/A .desc("Average achieved write bandwidth in MiByte/s") 21119243SN/A .precision(2); 21129243SN/A 21139243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 21149243SN/A 21159977SN/A avgRdBWSys 21169977SN/A .name(name() + ".avgRdBWSys") 21179977SN/A .desc("Average system read bandwidth in MiByte/s") 21189243SN/A .precision(2); 21199243SN/A 21209977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 21219243SN/A 21229977SN/A avgWrBWSys 21239977SN/A .name(name() + ".avgWrBWSys") 21249977SN/A .desc("Average system write bandwidth in MiByte/s") 21259243SN/A .precision(2); 21269243SN/A 21279977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 21289243SN/A 21299243SN/A peakBW 21309243SN/A .name(name() + ".peakBW") 21319977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 21329243SN/A .precision(2); 21339243SN/A 21349831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 21359243SN/A 21369243SN/A busUtil 21379243SN/A .name(name() + ".busUtil") 21389243SN/A .desc("Data bus utilization in percentage") 21399243SN/A .precision(2); 21409243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 21419243SN/A 21429243SN/A totGap 21439243SN/A .name(name() + ".totGap") 21449243SN/A .desc("Total gap between requests"); 21459243SN/A 21469243SN/A avgGap 21479243SN/A .name(name() + ".avgGap") 21489243SN/A .desc("Average gap between requests") 21499243SN/A .precision(2); 21509243SN/A 21519243SN/A avgGap = totGap / (readReqs + writeReqs); 21529975SN/A 21539975SN/A // Stats for DRAM Power calculation based on Micron datasheet 21549975SN/A busUtilRead 21559975SN/A .name(name() + ".busUtilRead") 21569975SN/A .desc("Data bus utilization in percentage for reads") 21579975SN/A .precision(2); 21589975SN/A 21599975SN/A busUtilRead = avgRdBW / peakBW * 100; 21609975SN/A 21619975SN/A busUtilWrite 21629975SN/A .name(name() + ".busUtilWrite") 21639975SN/A .desc("Data bus utilization in percentage for writes") 21649975SN/A .precision(2); 21659975SN/A 21669975SN/A busUtilWrite = avgWrBW / peakBW * 100; 21679975SN/A 21689975SN/A pageHitRate 21699975SN/A .name(name() + ".pageHitRate") 21709975SN/A .desc("Row buffer hit rate, read and write combined") 21719975SN/A .precision(2); 21729975SN/A 21739977SN/A pageHitRate = (writeRowHits + readRowHits) / 21749977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 21759243SN/A} 21769243SN/A 21779243SN/Avoid 217810146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 21799243SN/A{ 21809243SN/A // rely on the abstract memory 21819243SN/A functionalAccess(pkt); 21829243SN/A} 21839243SN/A 21849294SN/ABaseSlavePort& 218510146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 21869243SN/A{ 21879243SN/A if (if_name != "port") { 21889243SN/A return MemObject::getSlavePort(if_name, idx); 21899243SN/A } else { 21909243SN/A return port; 21919243SN/A } 21929243SN/A} 21939243SN/A 21949243SN/Aunsigned int 219510146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 21969243SN/A{ 21979342SN/A unsigned int count = port.drain(dm); 21989243SN/A 21999243SN/A // if there is anything in any of our internal queues, keep track 22009243SN/A // of that as well 22019567SN/A if (!(writeQueue.empty() && readQueue.empty() && 22029567SN/A respQueue.empty())) { 22039352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 22049567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 22059567SN/A respQueue.size()); 22069243SN/A ++count; 22079342SN/A drainManager = dm; 220810206Sandreas.hansson@arm.com 22099352SN/A // the only part that is not drained automatically over time 221010206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 221110206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 221210206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 221310206Sandreas.hansson@arm.com } 22149243SN/A } 22159243SN/A 22169243SN/A if (count) 22179342SN/A setDrainState(Drainable::Draining); 22189243SN/A else 22199342SN/A setDrainState(Drainable::Drained); 22209243SN/A return count; 22219243SN/A} 22229243SN/A 222310619Sandreas.hansson@arm.comvoid 222410619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 222510619Sandreas.hansson@arm.com{ 222610619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 222710619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 222810619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 222910619Sandreas.hansson@arm.com startup(); 223010619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 223110619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 223210619Sandreas.hansson@arm.com // not cause issues with KVM 223310619Sandreas.hansson@arm.com for (auto r : ranks) { 223410619Sandreas.hansson@arm.com r->suspend(); 223510619Sandreas.hansson@arm.com } 223610619Sandreas.hansson@arm.com } 223710619Sandreas.hansson@arm.com 223810619Sandreas.hansson@arm.com // update the mode 223910619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 224010619Sandreas.hansson@arm.com} 224110619Sandreas.hansson@arm.com 224210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 22439243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 22449243SN/A memory(_memory) 22459243SN/A{ } 22469243SN/A 22479243SN/AAddrRangeList 224810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 22499243SN/A{ 22509243SN/A AddrRangeList ranges; 22519243SN/A ranges.push_back(memory.getAddrRange()); 22529243SN/A return ranges; 22539243SN/A} 22549243SN/A 22559243SN/Avoid 225610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 22579243SN/A{ 22589243SN/A pkt->pushLabel(memory.name()); 22599243SN/A 22609243SN/A if (!queue.checkFunctional(pkt)) { 22619243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 22629243SN/A // calls recvAtomic() and throws away the latency; we can save a 22639243SN/A // little here by just not calculating the latency. 22649243SN/A memory.recvFunctional(pkt); 22659243SN/A } 22669243SN/A 22679243SN/A pkt->popLabel(); 22689243SN/A} 22699243SN/A 22709243SN/ATick 227110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 22729243SN/A{ 22739243SN/A return memory.recvAtomic(pkt); 22749243SN/A} 22759243SN/A 22769243SN/Abool 227710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 22789243SN/A{ 22799243SN/A // pass it to the memory controller 22809243SN/A return memory.recvTimingReq(pkt); 22819243SN/A} 22829243SN/A 228310146Sandreas.hansson@arm.comDRAMCtrl* 228410146Sandreas.hansson@arm.comDRAMCtrlParams::create() 22859243SN/A{ 228610146Sandreas.hansson@arm.com return new DRAMCtrl(this); 22879243SN/A} 2288