dram_ctrl.cc revision 10405
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 4910208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 509352SN/A#include "debug/Drain.hh" 5110146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 529814SN/A#include "sim/system.hh" 539243SN/A 549243SN/Ausing namespace std; 559243SN/A 5610146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 579243SN/A AbstractMemory(p), 589243SN/A port(name() + ".port", *this), 599243SN/A retryRdReq(false), retryWrReq(false), 6010211Sandreas.hansson@arm.com busState(READ), 6110208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6210208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6310208Sandreas.hansson@arm.com drainManager(NULL), 649831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 659831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 669831SN/A devicesPerRank(p->devices_per_rank), 679831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 689831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6910140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7010286Sandreas.hansson@arm.com columnsPerStripe(range.granularity() / burstSize), 719243SN/A ranksPerChannel(p->ranks_per_channel), 7210394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7310394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 749566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 759243SN/A readBufferSize(p->read_buffer_size), 769243SN/A writeBufferSize(p->write_buffer_size), 7710140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7810140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7910147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8010147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8110393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8210394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8310394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8410394Swendy.elsasser@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 859243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 869243SN/A pageMgmt(p->page_policy), 8710141SN/A maxAccessesPerRow(p->max_accesses_per_row), 889726SN/A frontendLatency(p->static_frontend_latency), 899726SN/A backendLatency(p->static_backend_latency), 9010208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 9110208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 9210393Swendy.elsasser@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0), 9310393Swendy.elsasser@arm.com activeRank(0) 949243SN/A{ 959243SN/A // create the bank states based on the dimensions of the ranks and 969243SN/A // banks 979243SN/A banks.resize(ranksPerChannel); 989969SN/A actTicks.resize(ranksPerChannel); 999243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 1009243SN/A banks[c].resize(banksPerRank); 1019969SN/A actTicks[c].resize(activationLimit, 0); 1029243SN/A } 1039243SN/A 10410246Sandreas.hansson@arm.com // set the bank indices 10510246Sandreas.hansson@arm.com for (int r = 0; r < ranksPerChannel; r++) { 10610246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 10710246Sandreas.hansson@arm.com banks[r][b].rank = r; 10810246Sandreas.hansson@arm.com banks[r][b].bank = b; 10910394Swendy.elsasser@arm.com if (bankGroupArch) { 11010394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 11110394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 11210394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 11310394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 11410394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 11510394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 11610394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 11710394Swendy.elsasser@arm.com banks[r][b].bankgr = b % bankGroupsPerRank; 11810394Swendy.elsasser@arm.com } else { 11910394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 12010394Swendy.elsasser@arm.com banks[r][b].bankgr = b; 12110394Swendy.elsasser@arm.com } 12210246Sandreas.hansson@arm.com } 12310246Sandreas.hansson@arm.com } 12410246Sandreas.hansson@arm.com 12510140SN/A // perform a basic check of the write thresholds 12610140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 12710140SN/A fatal("Write buffer low threshold %d must be smaller than the " 12810140SN/A "high threshold %d\n", p->write_low_thresh_perc, 12910140SN/A p->write_high_thresh_perc); 1309243SN/A 1319243SN/A // determine the rows per bank by looking at the total capacity 1329567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1339243SN/A 1349243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1359243SN/A AbstractMemory::size()); 1369831SN/A 1379831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1389831SN/A rowBufferSize, columnsPerRowBuffer); 1399831SN/A 1409831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1419243SN/A 14210286Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving 1439566SN/A if (range.interleaved()) { 1449566SN/A if (channels != range.stripes()) 14510143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1469566SN/A name(), range.stripes(), channels); 1479566SN/A 14810136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1499831SN/A if (rowBufferSize != range.granularity()) { 15010286Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 15110136SN/A "address map\n", name()); 1529566SN/A } 15310286Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 15410286Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 15510286Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 15610286Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 15710286Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 15810286Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 15910286Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 16010286Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 16110286Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 16210286Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 16310286Sandreas.hansson@arm.com 16410286Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 16510286Sandreas.hansson@arm.com // is equal or larger to a cache line 16610286Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 16710286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 16810286Sandreas.hansson@arm.com "as the cache line size\n", name()); 1699669SN/A } 17010286Sandreas.hansson@arm.com 17110286Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 17210286Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 17310286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 17410286Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 17510286Sandreas.hansson@arm.com } 17610286Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 17710286Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 1789566SN/A } 1799566SN/A } 18010207Sandreas.hansson@arm.com 18110207Sandreas.hansson@arm.com // some basic sanity checks 18210207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 18310207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 18410207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 18510207Sandreas.hansson@arm.com } 18610394Swendy.elsasser@arm.com 18710394Swendy.elsasser@arm.com // basic bank group architecture checks -> 18810394Swendy.elsasser@arm.com if (bankGroupArch) { 18910394Swendy.elsasser@arm.com // must have at least one bank per bank group 19010394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 19110394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 19210394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 19310394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 19410394Swendy.elsasser@arm.com } 19510394Swendy.elsasser@arm.com // must have same number of banks in each bank group 19610394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 19710394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 19810394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 19910394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 20010394Swendy.elsasser@arm.com } 20110394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 20210394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 20310394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 20410394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 20510394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 20610394Swendy.elsasser@arm.com } 20710394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 20810394Swendy.elsasser@arm.com if (tRRD_L <= tRRD) { 20910394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 21010394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 21110394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 21210394Swendy.elsasser@arm.com } 21310394Swendy.elsasser@arm.com } 21410394Swendy.elsasser@arm.com 2159243SN/A} 2169243SN/A 2179243SN/Avoid 21810146Sandreas.hansson@arm.comDRAMCtrl::init() 21910140SN/A{ 22010140SN/A if (!port.isConnected()) { 22110146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 22210140SN/A } else { 22310140SN/A port.sendRangeChange(); 22410140SN/A } 22510140SN/A} 22610140SN/A 22710140SN/Avoid 22810146Sandreas.hansson@arm.comDRAMCtrl::startup() 2299243SN/A{ 23010143SN/A // update the start tick for the precharge accounting to the 23110143SN/A // current tick 23210208Sandreas.hansson@arm.com pwrStateTick = curTick(); 23310143SN/A 23410206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 23510206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 23610206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 23710206Sandreas.hansson@arm.com // start of simulation 23810206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 23910206Sandreas.hansson@arm.com 24010207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 24110207Sandreas.hansson@arm.com // precharge 24210207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 2439243SN/A} 2449243SN/A 2459243SN/ATick 24610146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2479243SN/A{ 2489243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2499243SN/A 2509243SN/A // do the actual memory access and turn the packet into a response 2519243SN/A access(pkt); 2529243SN/A 2539243SN/A Tick latency = 0; 2549243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2559243SN/A // this value is not supposed to be accurate, just enough to 2569243SN/A // keep things going, mimic a closed page 2579243SN/A latency = tRP + tRCD + tCL; 2589243SN/A } 2599243SN/A return latency; 2609243SN/A} 2619243SN/A 2629243SN/Abool 26310146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2649243SN/A{ 2659831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2669831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2679831SN/A neededEntries); 2689243SN/A 2699831SN/A return 2709831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2719243SN/A} 2729243SN/A 2739243SN/Abool 27410146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2759243SN/A{ 2769831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2779831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2789831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2799243SN/A} 2809243SN/A 28110146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 28210146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 28310143SN/A bool isRead) 2849243SN/A{ 2859669SN/A // decode the address based on the address mapping scheme, with 28610136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 28710136SN/A // channel, respectively 2889243SN/A uint8_t rank; 2899967SN/A uint8_t bank; 29010245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 29110245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 29210245Sandreas.hansson@arm.com uint64_t row; 2939243SN/A 29410286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 29510286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 2969831SN/A Addr addr = dramPktAddr / burstSize; 2979243SN/A 2989491SN/A // we have removed the lowest order address bits that denote the 2999831SN/A // position within the column 30010136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3019491SN/A // the lowest order bits denote the column to ensure that 3029491SN/A // sequential cache lines occupy the same row 3039831SN/A addr = addr / columnsPerRowBuffer; 3049243SN/A 3059669SN/A // take out the channel part of the address 3069566SN/A addr = addr / channels; 3079566SN/A 3089669SN/A // after the channel bits, get the bank bits to interleave 3099669SN/A // over the banks 3109669SN/A bank = addr % banksPerRank; 3119669SN/A addr = addr / banksPerRank; 3129669SN/A 3139669SN/A // after the bank, we get the rank bits which thus interleaves 3149669SN/A // over the ranks 3159669SN/A rank = addr % ranksPerChannel; 3169669SN/A addr = addr / ranksPerChannel; 3179669SN/A 3189669SN/A // lastly, get the row bits 3199669SN/A row = addr % rowsPerBank; 3209669SN/A addr = addr / rowsPerBank; 32110136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 32210286Sandreas.hansson@arm.com // take out the lower-order column bits 32310286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 32410286Sandreas.hansson@arm.com 3259669SN/A // take out the channel part of the address 3269669SN/A addr = addr / channels; 3279669SN/A 32810286Sandreas.hansson@arm.com // next, the higher-order column bites 32910286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3309669SN/A 3319669SN/A // after the column bits, we get the bank bits to interleave 3329491SN/A // over the banks 3339243SN/A bank = addr % banksPerRank; 3349243SN/A addr = addr / banksPerRank; 3359243SN/A 3369491SN/A // after the bank, we get the rank bits which thus interleaves 3379491SN/A // over the ranks 3389243SN/A rank = addr % ranksPerChannel; 3399243SN/A addr = addr / ranksPerChannel; 3409243SN/A 3419491SN/A // lastly, get the row bits 3429243SN/A row = addr % rowsPerBank; 3439243SN/A addr = addr / rowsPerBank; 34410136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3459491SN/A // optimise for closed page mode and utilise maximum 3469491SN/A // parallelism of the DRAM (at the cost of power) 3479491SN/A 34810286Sandreas.hansson@arm.com // take out the lower-order column bits 34910286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 35010286Sandreas.hansson@arm.com 3519566SN/A // take out the channel part of the address, not that this has 3529566SN/A // to match with how accesses are interleaved between the 3539566SN/A // controllers in the address mapping 3549566SN/A addr = addr / channels; 3559566SN/A 3569491SN/A // start with the bank bits, as this provides the maximum 3579491SN/A // opportunity for parallelism between requests 3589243SN/A bank = addr % banksPerRank; 3599243SN/A addr = addr / banksPerRank; 3609243SN/A 3619491SN/A // next get the rank bits 3629243SN/A rank = addr % ranksPerChannel; 3639243SN/A addr = addr / ranksPerChannel; 3649243SN/A 36510286Sandreas.hansson@arm.com // next, the higher-order column bites 36610286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3679243SN/A 3689491SN/A // lastly, get the row bits 3699243SN/A row = addr % rowsPerBank; 3709243SN/A addr = addr / rowsPerBank; 3719243SN/A } else 3729243SN/A panic("Unknown address mapping policy chosen!"); 3739243SN/A 3749243SN/A assert(rank < ranksPerChannel); 3759243SN/A assert(bank < banksPerRank); 3769243SN/A assert(row < rowsPerBank); 37710245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3789243SN/A 3799243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3809831SN/A dramPktAddr, rank, bank, row); 3819243SN/A 3829243SN/A // create the corresponding DRAM packet with the entry time and 3839567SN/A // ready time set to the current tick, the latter will be updated 3849567SN/A // later 3859967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3869967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3879967SN/A size, banks[rank][bank]); 3889243SN/A} 3899243SN/A 3909243SN/Avoid 39110146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3929243SN/A{ 3939243SN/A // only add to the read queue here. whenever the request is 3949243SN/A // eventually done, set the readyTime, and call schedule() 3959243SN/A assert(!pkt->isWrite()); 3969243SN/A 3979831SN/A assert(pktCount != 0); 3989831SN/A 3999831SN/A // if the request size is larger than burst size, the pkt is split into 4009831SN/A // multiple DRAM packets 4019831SN/A // Note if the pkt starting address is not aligened to burst size, the 4029831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4039831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4049831SN/A // check read packets against packets in write queue. 4059243SN/A Addr addr = pkt->getAddr(); 4069831SN/A unsigned pktsServicedByWrQ = 0; 4079831SN/A BurstHelper* burst_helper = NULL; 4089831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4099831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4109831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4119831SN/A readPktSize[ceilLog2(size)]++; 4129831SN/A readBursts++; 4139243SN/A 4149831SN/A // First check write buffer to see if the data is already at 4159831SN/A // the controller 4169831SN/A bool foundInWrQ = false; 4179833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 4189832SN/A // check if the read is subsumed in the write entry we are 4199832SN/A // looking at 4209832SN/A if ((*i)->addr <= addr && 4219832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 4229831SN/A foundInWrQ = true; 4239831SN/A servicedByWrQ++; 4249831SN/A pktsServicedByWrQ++; 4259831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 4269831SN/A "write queue\n", addr, size); 4279975SN/A bytesReadWrQ += burstSize; 4289831SN/A break; 4299831SN/A } 4309243SN/A } 4319831SN/A 4329831SN/A // If not found in the write q, make a DRAM packet and 4339831SN/A // push it onto the read queue 4349831SN/A if (!foundInWrQ) { 4359831SN/A 4369831SN/A // Make the burst helper for split packets 4379831SN/A if (pktCount > 1 && burst_helper == NULL) { 4389831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4399831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4409831SN/A burst_helper = new BurstHelper(pktCount); 4419831SN/A } 4429831SN/A 4439966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4449831SN/A dram_pkt->burstHelper = burst_helper; 4459831SN/A 4469831SN/A assert(!readQueueFull(1)); 4479831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4489831SN/A 4499831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4509831SN/A 4519831SN/A readQueue.push_back(dram_pkt); 4529831SN/A 4539831SN/A // Update stats 4549831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4559831SN/A } 4569831SN/A 4579831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4589831SN/A addr = (addr | (burstSize - 1)) + 1; 4599243SN/A } 4609243SN/A 4619831SN/A // If all packets are serviced by write queue, we send the repsonse back 4629831SN/A if (pktsServicedByWrQ == pktCount) { 4639831SN/A accessAndRespond(pkt, frontendLatency); 4649831SN/A return; 4659831SN/A } 4669243SN/A 4679831SN/A // Update how many split packets are serviced by write queue 4689831SN/A if (burst_helper != NULL) 4699831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4709243SN/A 47110206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 47210206Sandreas.hansson@arm.com // queue, do so now 47310206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4749567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4759567SN/A schedule(nextReqEvent, curTick()); 4769243SN/A } 4779243SN/A} 4789243SN/A 4799243SN/Avoid 48010146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4819243SN/A{ 4829243SN/A // only add to the write queue here. whenever the request is 4839243SN/A // eventually done, set the readyTime, and call schedule() 4849243SN/A assert(pkt->isWrite()); 4859243SN/A 4869831SN/A // if the request size is larger than burst size, the pkt is split into 4879831SN/A // multiple DRAM packets 4889831SN/A Addr addr = pkt->getAddr(); 4899831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4909831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4919831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4929831SN/A writePktSize[ceilLog2(size)]++; 4939831SN/A writeBursts++; 4949243SN/A 4959832SN/A // see if we can merge with an existing item in the write 4969838SN/A // queue and keep track of whether we have merged or not so we 4979838SN/A // can stop at that point and also avoid enqueueing a new 4989838SN/A // request 4999832SN/A bool merged = false; 5009832SN/A auto w = writeQueue.begin(); 5019243SN/A 5029832SN/A while(!merged && w != writeQueue.end()) { 5039832SN/A // either of the two could be first, if they are the same 5049832SN/A // it does not matter which way we go 5059832SN/A if ((*w)->addr >= addr) { 5069838SN/A // the existing one starts after the new one, figure 5079838SN/A // out where the new one ends with respect to the 5089838SN/A // existing one 5099832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 5109832SN/A // check if the existing one is completely 5119832SN/A // subsumed in the new one 5129832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 5139832SN/A merged = true; 5149832SN/A // update both the address and the size 5159832SN/A (*w)->addr = addr; 5169832SN/A (*w)->size = size; 5179832SN/A } else if ((addr + size) >= (*w)->addr && 5189832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 5199832SN/A // the new one is just before or partially 5209832SN/A // overlapping with the existing one, and together 5219832SN/A // they fit within a burst 5229832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 5239832SN/A merged = true; 5249832SN/A // the existing queue item needs to be adjusted with 5259832SN/A // respect to both address and size 52610047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 5279832SN/A (*w)->addr = addr; 5289832SN/A } 5299832SN/A } else { 5309838SN/A // the new one starts after the current one, figure 5319838SN/A // out where the existing one ends with respect to the 5329838SN/A // new one 5339832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 5349832SN/A // check if the new one is completely subsumed in the 5359832SN/A // existing one 5369832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 5379832SN/A merged = true; 5389832SN/A // no adjustments necessary 5399832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 5409832SN/A (addr + size - (*w)->addr) <= burstSize) { 5419832SN/A // the existing one is just before or partially 5429832SN/A // overlapping with the new one, and together 5439832SN/A // they fit within a burst 5449832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5459832SN/A merged = true; 5469832SN/A // the address is right, and only the size has 5479832SN/A // to be adjusted 5489832SN/A (*w)->size = addr + size - (*w)->addr; 5499832SN/A } 5509832SN/A } 5519832SN/A ++w; 5529832SN/A } 5539243SN/A 5549832SN/A // if the item was not merged we need to create a new write 5559832SN/A // and enqueue it 5569832SN/A if (!merged) { 5579966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5589243SN/A 5599832SN/A assert(writeQueue.size() < writeBufferSize); 5609832SN/A wrQLenPdf[writeQueue.size()]++; 5619243SN/A 5629832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5639831SN/A 5649832SN/A writeQueue.push_back(dram_pkt); 5659831SN/A 5669832SN/A // Update stats 5679832SN/A avgWrQLen = writeQueue.size(); 5689977SN/A } else { 5699977SN/A // keep track of the fact that this burst effectively 5709977SN/A // disappeared as it was merged with an existing one 5719977SN/A mergedWrBursts++; 5729832SN/A } 5739832SN/A 5749831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5759831SN/A addr = (addr | (burstSize - 1)) + 1; 5769831SN/A } 5779243SN/A 5789243SN/A // we do not wait for the writes to be send to the actual memory, 5799243SN/A // but instead take responsibility for the consistency here and 5809243SN/A // snoop the write queue for any upcoming reads 5819831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5829831SN/A // different front end latency 5839726SN/A accessAndRespond(pkt, frontendLatency); 5849243SN/A 58510206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 58610206Sandreas.hansson@arm.com // queue, do so now 58710206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 58810206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 58910206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5909243SN/A } 5919243SN/A} 5929243SN/A 5939243SN/Avoid 59410146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5959243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5969833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5979243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5989243SN/A } 5999243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 6009833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 6019243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 6029243SN/A } 6039243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 6049833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 6059243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 6069243SN/A } 6079243SN/A} 6089243SN/A 6099243SN/Abool 61010146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6119243SN/A{ 6129349SN/A /// @todo temporary hack to deal with memory corruption issues until 6139349SN/A /// 4-phase transactions are complete 6149349SN/A for (int x = 0; x < pendingDelete.size(); x++) 6159349SN/A delete pendingDelete[x]; 6169349SN/A pendingDelete.clear(); 6179349SN/A 6189243SN/A // This is where we enter from the outside world 6199567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6209831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6219243SN/A 6229567SN/A // simply drop inhibited packets for now 6239567SN/A if (pkt->memInhibitAsserted()) { 62410143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6259567SN/A pendingDelete.push_back(pkt); 6269567SN/A return true; 6279567SN/A } 6289243SN/A 6299243SN/A // Calc avg gap between requests 6309243SN/A if (prevArrival != 0) { 6319243SN/A totGap += curTick() - prevArrival; 6329243SN/A } 6339243SN/A prevArrival = curTick(); 6349243SN/A 6359831SN/A 6369831SN/A // Find out how many dram packets a pkt translates to 6379831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6389831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6399831SN/A // multiple dram packets 6409243SN/A unsigned size = pkt->getSize(); 6419831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6429831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6439243SN/A 6449243SN/A // check local buffers and do not accept if full 6459243SN/A if (pkt->isRead()) { 6469567SN/A assert(size != 0); 6479831SN/A if (readQueueFull(dram_pkt_count)) { 6489567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6499243SN/A // remember that we have to retry this port 6509243SN/A retryRdReq = true; 6519243SN/A numRdRetry++; 6529243SN/A return false; 6539243SN/A } else { 6549831SN/A addToReadQueue(pkt, dram_pkt_count); 6559243SN/A readReqs++; 6569977SN/A bytesReadSys += size; 6579243SN/A } 6589243SN/A } else if (pkt->isWrite()) { 6599567SN/A assert(size != 0); 6609831SN/A if (writeQueueFull(dram_pkt_count)) { 6619567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6629243SN/A // remember that we have to retry this port 6639243SN/A retryWrReq = true; 6649243SN/A numWrRetry++; 6659243SN/A return false; 6669243SN/A } else { 6679831SN/A addToWriteQueue(pkt, dram_pkt_count); 6689243SN/A writeReqs++; 6699977SN/A bytesWrittenSys += size; 6709243SN/A } 6719243SN/A } else { 6729243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6739243SN/A neitherReadNorWrite++; 6749726SN/A accessAndRespond(pkt, 1); 6759243SN/A } 6769243SN/A 6779243SN/A return true; 6789243SN/A} 6799243SN/A 6809243SN/Avoid 68110146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6829243SN/A{ 6839243SN/A DPRINTF(DRAM, 6849243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6859243SN/A 6869831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6879243SN/A 6889831SN/A if (dram_pkt->burstHelper) { 6899831SN/A // it is a split packet 6909831SN/A dram_pkt->burstHelper->burstsServiced++; 6919831SN/A if (dram_pkt->burstHelper->burstsServiced == 69210143SN/A dram_pkt->burstHelper->burstCount) { 6939831SN/A // we have now serviced all children packets of a system packet 6949831SN/A // so we can now respond to the requester 6959831SN/A // @todo we probably want to have a different front end and back 6969831SN/A // end latency for split packets 6979831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6989831SN/A delete dram_pkt->burstHelper; 6999831SN/A dram_pkt->burstHelper = NULL; 7009831SN/A } 7019831SN/A } else { 7029831SN/A // it is not a split packet 7039831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7049831SN/A } 7059243SN/A 7069831SN/A delete respQueue.front(); 7079831SN/A respQueue.pop_front(); 7089243SN/A 7099831SN/A if (!respQueue.empty()) { 7109831SN/A assert(respQueue.front()->readyTime >= curTick()); 7119831SN/A assert(!respondEvent.scheduled()); 7129831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7139831SN/A } else { 7149831SN/A // if there is nothing left in any queue, signal a drain 7159831SN/A if (writeQueue.empty() && readQueue.empty() && 7169831SN/A drainManager) { 7179831SN/A drainManager->signalDrainDone(); 7189831SN/A drainManager = NULL; 7199831SN/A } 7209831SN/A } 7219567SN/A 7229831SN/A // We have made a location in the queue available at this point, 7239831SN/A // so if there is a read that was forced to wait, retry now 7249831SN/A if (retryRdReq) { 7259831SN/A retryRdReq = false; 7269831SN/A port.sendRetry(); 7279831SN/A } 7289243SN/A} 7299243SN/A 7309243SN/Avoid 73110393Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7329243SN/A{ 73310206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 73410206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 73510206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 73610206Sandreas.hansson@arm.com // FCFS, this method does nothing 73710206Sandreas.hansson@arm.com assert(!queue.empty()); 7389243SN/A 73910206Sandreas.hansson@arm.com if (queue.size() == 1) { 74010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 7419243SN/A return; 7429243SN/A } 7439243SN/A 7449243SN/A if (memSchedPolicy == Enums::fcfs) { 7459243SN/A // Do nothing, since the correct request is already head 7469243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 74710393Swendy.elsasser@arm.com reorderQueue(queue, switched_cmd_type); 7489243SN/A } else 7499243SN/A panic("No scheduling policy chosen\n"); 7509243SN/A} 7519243SN/A 7529243SN/Avoid 75310393Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7549974SN/A{ 7559974SN/A // Only determine this when needed 7569974SN/A uint64_t earliest_banks = 0; 7579974SN/A 7589974SN/A // Search for row hits first, if no row hit is found then schedule the 7599974SN/A // packet to one of the earliest banks available 7609974SN/A bool found_earliest_pkt = false; 76110393Swendy.elsasser@arm.com bool found_prepped_diff_rank_pkt = false; 7629974SN/A auto selected_pkt_it = queue.begin(); 7639974SN/A 7649974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7659974SN/A DRAMPacket* dram_pkt = *i; 7669974SN/A const Bank& bank = dram_pkt->bankRef; 7679974SN/A // Check if it is a row hit 7689974SN/A if (bank.openRow == dram_pkt->row) { 76910393Swendy.elsasser@arm.com if (dram_pkt->rank == activeRank || switched_cmd_type) { 77010393Swendy.elsasser@arm.com // FCFS within the hits, giving priority to commands 77110393Swendy.elsasser@arm.com // that access the same rank as the previous burst 77210393Swendy.elsasser@arm.com // to minimize bus turnaround delays 77310393Swendy.elsasser@arm.com // Only give rank prioity when command type is not changing 77410393Swendy.elsasser@arm.com DPRINTF(DRAM, "Row buffer hit\n"); 77510393Swendy.elsasser@arm.com selected_pkt_it = i; 77610393Swendy.elsasser@arm.com break; 77710393Swendy.elsasser@arm.com } else if (!found_prepped_diff_rank_pkt) { 77810393Swendy.elsasser@arm.com // found row hit for command on different rank than prev burst 77910393Swendy.elsasser@arm.com selected_pkt_it = i; 78010393Swendy.elsasser@arm.com found_prepped_diff_rank_pkt = true; 78110393Swendy.elsasser@arm.com } 78210393Swendy.elsasser@arm.com } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 78310393Swendy.elsasser@arm.com // No row hit and 78410393Swendy.elsasser@arm.com // haven't found an entry with a row hit to a new rank 7859974SN/A if (earliest_banks == 0) 78610393Swendy.elsasser@arm.com // Determine entries with earliest bank prep delay 78710393Swendy.elsasser@arm.com // Function will give priority to commands that access the 78810393Swendy.elsasser@arm.com // same rank as previous burst and can prep the bank seamlessly 78910393Swendy.elsasser@arm.com earliest_banks = minBankPrep(queue, switched_cmd_type); 79010211Sandreas.hansson@arm.com 79110393Swendy.elsasser@arm.com // FCFS - Bank is first available bank 79210393Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7939974SN/A // Remember the packet to be scheduled to one of the earliest 79410211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 7959974SN/A selected_pkt_it = i; 7969974SN/A found_earliest_pkt = true; 7979974SN/A } 7989974SN/A } 7999974SN/A } 8009974SN/A 8019974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 8029974SN/A queue.erase(selected_pkt_it); 8039974SN/A queue.push_front(selected_pkt); 8049974SN/A} 8059974SN/A 8069974SN/Avoid 80710146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8089243SN/A{ 8099243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8109243SN/A 8119243SN/A bool needsResponse = pkt->needsResponse(); 8129243SN/A // do the actual memory access which also turns the packet into a 8139243SN/A // response 8149243SN/A access(pkt); 8159243SN/A 8169243SN/A // turn packet around to go back to requester if response expected 8179243SN/A if (needsResponse) { 8189243SN/A // access already turned the packet into a response 8199243SN/A assert(pkt->isResponse()); 8209243SN/A 8219549SN/A // @todo someone should pay for this 82210405Sandreas.hansson@arm.com pkt->firstWordDelay = pkt->lastWordDelay = 0; 8239549SN/A 8249726SN/A // queue the packet in the response queue to be sent out after 8259726SN/A // the static latency has passed 8269726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 8279243SN/A } else { 8289587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8299587SN/A // is still having a pointer to it 8309587SN/A pendingDelete.push_back(pkt); 8319243SN/A } 8329243SN/A 8339243SN/A DPRINTF(DRAM, "Done\n"); 8349243SN/A 8359243SN/A return; 8369243SN/A} 8379243SN/A 8389243SN/Avoid 83910246Sandreas.hansson@arm.comDRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row) 8409488SN/A{ 84110246Sandreas.hansson@arm.com // get the rank index from the bank 84210246Sandreas.hansson@arm.com uint8_t rank = bank.rank; 84310246Sandreas.hansson@arm.com 8449969SN/A assert(actTicks[rank].size() == activationLimit); 8459488SN/A 8469488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8479488SN/A 84810207Sandreas.hansson@arm.com // update the open row 84910246Sandreas.hansson@arm.com assert(bank.openRow == Bank::NO_ROW); 85010246Sandreas.hansson@arm.com bank.openRow = row; 85110207Sandreas.hansson@arm.com 85210207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 85310207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 85410207Sandreas.hansson@arm.com // precharge 85510246Sandreas.hansson@arm.com bank.bytesAccessed = 0; 85610246Sandreas.hansson@arm.com bank.rowAccesses = 0; 85710207Sandreas.hansson@arm.com 85810207Sandreas.hansson@arm.com ++numBanksActive; 85910207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 86010207Sandreas.hansson@arm.com 86110247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 86210247Sandreas.hansson@arm.com bank.bank, bank.rank, act_tick, numBanksActive); 86310247Sandreas.hansson@arm.com 86410247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK), bank.bank, 86510247Sandreas.hansson@arm.com bank.rank); 8669975SN/A 86710211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 86810246Sandreas.hansson@arm.com bank.preAllowedAt = act_tick + tRAS; 86910211Sandreas.hansson@arm.com 87010211Sandreas.hansson@arm.com // Respect the row-to-column command delay 87110394Swendy.elsasser@arm.com bank.colAllowedAt = std::max(act_tick + tRCD, bank.colAllowedAt); 87210211Sandreas.hansson@arm.com 8739971SN/A // start by enforcing tRRD 8749971SN/A for(int i = 0; i < banksPerRank; i++) { 87510210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 87610210Sandreas.hansson@arm.com // before tRRD 87710394Swendy.elsasser@arm.com if (bankGroupArch && (bank.bankgr == banks[rank][i].bankgr)) { 87810394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 87910394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 88010394Swendy.elsasser@arm.com // in this case 88110394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD_L, 88210394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt); 88310394Swendy.elsasser@arm.com } else { 88410394Swendy.elsasser@arm.com // use shorter tRRD value when either 88510394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 88610394Swendy.elsasser@arm.com // 2) bank is in a different bank group 88710394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 88810394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt); 88910394Swendy.elsasser@arm.com } 8909971SN/A } 89110208Sandreas.hansson@arm.com 8929971SN/A // next, we deal with tXAW, if the activation limit is disabled 8939971SN/A // then we are done 8949969SN/A if (actTicks[rank].empty()) 8959824SN/A return; 8969824SN/A 8979488SN/A // sanity check 8989969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 89910210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 90010210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 90110210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 9029488SN/A } 9039488SN/A 9049488SN/A // shift the times used for the book keeping, the last element 9059488SN/A // (highest index) is the oldest one and hence the lowest value 9069969SN/A actTicks[rank].pop_back(); 9079488SN/A 9089488SN/A // record an new activation (in the future) 9099969SN/A actTicks[rank].push_front(act_tick); 9109488SN/A 9119488SN/A // cannot activate more than X times in time window tXAW, push the 9129488SN/A // next one (the X + 1'st activate) to be tXAW away from the 9139488SN/A // oldest in our window of X 9149969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 9159488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 91610210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 9179488SN/A for(int j = 0; j < banksPerRank; j++) 9189488SN/A // next activate must not happen before end of window 91910210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 92010210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 92110210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 9229488SN/A } 92310208Sandreas.hansson@arm.com 92410208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 92510208Sandreas.hansson@arm.com // transition to the active power state 92610208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 92710208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 92810208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 92910208Sandreas.hansson@arm.com // move it sooner in time 93010208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 93110208Sandreas.hansson@arm.com} 93210208Sandreas.hansson@arm.com 93310208Sandreas.hansson@arm.comvoid 93410208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 93510208Sandreas.hansson@arm.com{ 93610208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 93710208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 93810208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 93910208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 94010208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 9419488SN/A} 9429488SN/A 9439488SN/Avoid 94410247Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at, bool trace) 94510207Sandreas.hansson@arm.com{ 94610207Sandreas.hansson@arm.com // make sure the bank has an open row 94710207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 94810207Sandreas.hansson@arm.com 94910207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 95010207Sandreas.hansson@arm.com // the page 95110207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 95210207Sandreas.hansson@arm.com 95310207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 95410207Sandreas.hansson@arm.com 95510214Sandreas.hansson@arm.com // no precharge allowed before this one 95610214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 95710214Sandreas.hansson@arm.com 95810211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 95910211Sandreas.hansson@arm.com 96010211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 96110207Sandreas.hansson@arm.com 96210207Sandreas.hansson@arm.com assert(numBanksActive != 0); 96310207Sandreas.hansson@arm.com --numBanksActive; 96410207Sandreas.hansson@arm.com 96510247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 96610247Sandreas.hansson@arm.com "%d active\n", bank.bank, bank.rank, pre_at, numBanksActive); 96710247Sandreas.hansson@arm.com 96810247Sandreas.hansson@arm.com if (trace) 96910247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK), 97010247Sandreas.hansson@arm.com bank.bank, bank.rank); 97110207Sandreas.hansson@arm.com 97210208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 97310208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 97410208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 97510208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 97610208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 97710208Sandreas.hansson@arm.com // the (last) precharge takes place 97810208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 97910211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 98010211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 98110211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 98210208Sandreas.hansson@arm.com} 98310208Sandreas.hansson@arm.com 98410208Sandreas.hansson@arm.comvoid 98510208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 98610208Sandreas.hansson@arm.com{ 98710207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 98810207Sandreas.hansson@arm.com // if all banks are precharged for the power models 98910207Sandreas.hansson@arm.com if (numBanksActive == 0) { 99010208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 99110208Sandreas.hansson@arm.com // is precharged 99210208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 99310207Sandreas.hansson@arm.com } 99410207Sandreas.hansson@arm.com} 99510207Sandreas.hansson@arm.com 99610207Sandreas.hansson@arm.comvoid 99710146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9989243SN/A{ 9999243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10009243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10019243SN/A 100210211Sandreas.hansson@arm.com // get the bank 10039967SN/A Bank& bank = dram_pkt->bankRef; 10049243SN/A 100510211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 100610211Sandreas.hansson@arm.com bool row_hit = true; 100710211Sandreas.hansson@arm.com 100810211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 100910211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 101010211Sandreas.hansson@arm.com 101110211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 101210211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 101310211Sandreas.hansson@arm.com // nothing to do 101410209Sandreas.hansson@arm.com } else { 101510211Sandreas.hansson@arm.com row_hit = false; 101610211Sandreas.hansson@arm.com 101710209Sandreas.hansson@arm.com // If there is a page open, precharge it. 101810209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 101910211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 10209488SN/A } 10219973SN/A 102210211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 102310211Sandreas.hansson@arm.com // page 102410211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10259973SN/A 102610210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 102710210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 102810246Sandreas.hansson@arm.com activateBank(bank, act_tick, dram_pkt->row); 102910210Sandreas.hansson@arm.com 103010211Sandreas.hansson@arm.com // issue the command as early as possible 103110211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 103210209Sandreas.hansson@arm.com } 103310209Sandreas.hansson@arm.com 103410211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 103510211Sandreas.hansson@arm.com // the command 103610211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 103710211Sandreas.hansson@arm.com 103810211Sandreas.hansson@arm.com // update the packet ready time 103910211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 104010211Sandreas.hansson@arm.com 104110211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 104210211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 104310211Sandreas.hansson@arm.com 104410394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 104510394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 104610394Swendy.elsasser@arm.com Tick cmd_dly; 104710394Swendy.elsasser@arm.com for(int j = 0; j < ranksPerChannel; j++) { 104810394Swendy.elsasser@arm.com for(int i = 0; i < banksPerRank; i++) { 104910394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 105010394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 105110394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 105210394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 105310394Swendy.elsasser@arm.com if (bankGroupArch && (bank.bankgr == banks[j][i].bankgr)) { 105410394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 105510394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 105610394Swendy.elsasser@arm.com // Use tCCD_L in this case 105710394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 105810394Swendy.elsasser@arm.com } else { 105910394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 106010394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 106110394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 106210394Swendy.elsasser@arm.com // 2) bank is in a different bank group 106310394Swendy.elsasser@arm.com cmd_dly = tBURST; 106410394Swendy.elsasser@arm.com } 106510394Swendy.elsasser@arm.com } else { 106610394Swendy.elsasser@arm.com // different rank is by default in a different bank group 106710394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 106810394Swendy.elsasser@arm.com // cas-to-cas delay in this case 106910394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 107010394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 107110394Swendy.elsasser@arm.com } 107210394Swendy.elsasser@arm.com banks[j][i].colAllowedAt = std::max(cmd_at + cmd_dly, 107310394Swendy.elsasser@arm.com banks[j][i].colAllowedAt); 107410394Swendy.elsasser@arm.com } 107510394Swendy.elsasser@arm.com } 107610211Sandreas.hansson@arm.com 107710393Swendy.elsasser@arm.com // Save rank of current access 107810393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 107910393Swendy.elsasser@arm.com 108010212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 108110212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 108210212Sandreas.hansson@arm.com // read to precharge constraint 108310212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 108410212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 108510212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 108610210Sandreas.hansson@arm.com 108710209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 108810209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 108910209Sandreas.hansson@arm.com ++bank.rowAccesses; 109010209Sandreas.hansson@arm.com 109110209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 109210209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 109310209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 109410209Sandreas.hansson@arm.com 109510209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 109610209Sandreas.hansson@arm.com // auto-precharge 109710209Sandreas.hansson@arm.com if (!auto_precharge && 109810209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 109910209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 110010209Sandreas.hansson@arm.com // a twist on the open and close page policies: 110110209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 110210209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 110310209Sandreas.hansson@arm.com // are bank conflicts in the queue 110410209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 110510209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 110610209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 110710209Sandreas.hansson@arm.com // are no same page hits in the queue 110810209Sandreas.hansson@arm.com bool got_more_hits = false; 110910209Sandreas.hansson@arm.com bool got_bank_conflict = false; 111010209Sandreas.hansson@arm.com 111110209Sandreas.hansson@arm.com // either look at the read queue or write queue 111210209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 111310209Sandreas.hansson@arm.com writeQueue; 111410209Sandreas.hansson@arm.com auto p = queue.begin(); 111510209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 111610209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 111710209Sandreas.hansson@arm.com ++p; 111810209Sandreas.hansson@arm.com 111910209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 112010209Sandreas.hansson@arm.com // reached the end 112110209Sandreas.hansson@arm.com while (!(got_more_hits && 112210209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 112310209Sandreas.hansson@arm.com p != queue.end()) { 112410209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 112510209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 112610209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 112710209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 112810209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11299973SN/A ++p; 113010141SN/A } 113110141SN/A 113210209Sandreas.hansson@arm.com // auto pre-charge when either 113310209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 113410209Sandreas.hansson@arm.com // have a bank conflict 113510209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 113610209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 113710209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 113810209Sandreas.hansson@arm.com } 113910142SN/A 114010247Sandreas.hansson@arm.com // DRAMPower trace command to be written 114110247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 114210247Sandreas.hansson@arm.com 114310209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 114410209Sandreas.hansson@arm.com // closing the row 114510209Sandreas.hansson@arm.com if (auto_precharge) { 114610247Sandreas.hansson@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt), false); 114710247Sandreas.hansson@arm.com 114810247Sandreas.hansson@arm.com mem_cmd.append("A"); 11499973SN/A 115010209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 115110209Sandreas.hansson@arm.com } 11529963SN/A 11539243SN/A // Update bus state 11549243SN/A busBusyUntil = dram_pkt->readyTime; 11559243SN/A 115610211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 115710211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 11589243SN/A 115910247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK), mem_cmd, 116010247Sandreas.hansson@arm.com dram_pkt->bank, dram_pkt->rank); 116110247Sandreas.hansson@arm.com 116210206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 116310206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 116410206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 116510206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 116610206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 11679972SN/A 116810206Sandreas.hansson@arm.com // Update the stats and schedule the next request 11699977SN/A if (dram_pkt->isRead) { 117010147Sandreas.hansson@arm.com ++readsThisTime; 117110211Sandreas.hansson@arm.com if (row_hit) 11729977SN/A readRowHits++; 11739977SN/A bytesReadDRAM += burstSize; 11749977SN/A perBankRdBursts[dram_pkt->bankId]++; 117510206Sandreas.hansson@arm.com 117610206Sandreas.hansson@arm.com // Update latency stats 117710206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 117810206Sandreas.hansson@arm.com totBusLat += tBURST; 117910211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 11809977SN/A } else { 118110147Sandreas.hansson@arm.com ++writesThisTime; 118210211Sandreas.hansson@arm.com if (row_hit) 11839977SN/A writeRowHits++; 11849977SN/A bytesWritten += burstSize; 11859977SN/A perBankWrBursts[dram_pkt->bankId]++; 11869243SN/A } 11879243SN/A} 11889243SN/A 11899243SN/Avoid 119010206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 11919243SN/A{ 119210393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 119310393Swendy.elsasser@arm.com // or WRITE_TO_READ state 119410393Swendy.elsasser@arm.com bool switched_cmd_type = false; 119510206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 119610206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 119710206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 11989243SN/A 119910206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 120010206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 120110206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 120210206Sandreas.hansson@arm.com readsThisTime = 0; 120310206Sandreas.hansson@arm.com 120410206Sandreas.hansson@arm.com // now proceed to do the actual writes 120510206Sandreas.hansson@arm.com busState = WRITE; 120610393Swendy.elsasser@arm.com switched_cmd_type = true; 120710206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 120810206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 120910206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 121010206Sandreas.hansson@arm.com 121110206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 121210206Sandreas.hansson@arm.com writesThisTime = 0; 121310206Sandreas.hansson@arm.com 121410206Sandreas.hansson@arm.com busState = READ; 121510393Swendy.elsasser@arm.com switched_cmd_type = true; 121610206Sandreas.hansson@arm.com } 121710206Sandreas.hansson@arm.com 121810207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 121910207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 122010207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 122110207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 122210207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 122310207Sandreas.hansson@arm.com 122410207Sandreas.hansson@arm.com refreshState = REF_PRE; 122510207Sandreas.hansson@arm.com 122610207Sandreas.hansson@arm.com // hand control back to the refresh event loop 122710207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 122810207Sandreas.hansson@arm.com } 122910207Sandreas.hansson@arm.com 123010207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 123110207Sandreas.hansson@arm.com return; 123210207Sandreas.hansson@arm.com } 123310207Sandreas.hansson@arm.com 123410206Sandreas.hansson@arm.com // when we get here it is either a read or a write 123510206Sandreas.hansson@arm.com if (busState == READ) { 123610206Sandreas.hansson@arm.com 123710206Sandreas.hansson@arm.com // track if we should switch or not 123810206Sandreas.hansson@arm.com bool switch_to_writes = false; 123910206Sandreas.hansson@arm.com 124010206Sandreas.hansson@arm.com if (readQueue.empty()) { 124110206Sandreas.hansson@arm.com // In the case there is no read request to go next, 124210206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 124310206Sandreas.hansson@arm.com // if we are draining) 124410206Sandreas.hansson@arm.com if (!writeQueue.empty() && 124510206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 124610206Sandreas.hansson@arm.com 124710206Sandreas.hansson@arm.com switch_to_writes = true; 124810206Sandreas.hansson@arm.com } else { 124910206Sandreas.hansson@arm.com // check if we are drained 125010206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 125110206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 125210206Sandreas.hansson@arm.com drainManager = NULL; 125310206Sandreas.hansson@arm.com } 125410206Sandreas.hansson@arm.com 125510206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 125610206Sandreas.hansson@arm.com // event for the next request 125710206Sandreas.hansson@arm.com return; 125810206Sandreas.hansson@arm.com } 125910206Sandreas.hansson@arm.com } else { 126010206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 126110206Sandreas.hansson@arm.com // front of the read queue 126210393Swendy.elsasser@arm.com chooseNext(readQueue, switched_cmd_type); 126310206Sandreas.hansson@arm.com 126410215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 126510215Sandreas.hansson@arm.com 126610393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 126710393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 126810393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 126910393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 127010393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 127110394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 127210394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 127310393Swendy.elsasser@arm.com } 127410393Swendy.elsasser@arm.com 127510215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 127610206Sandreas.hansson@arm.com 127710206Sandreas.hansson@arm.com // At this point we're done dealing with the request 127810215Sandreas.hansson@arm.com readQueue.pop_front(); 127910215Sandreas.hansson@arm.com 128010215Sandreas.hansson@arm.com // sanity check 128110215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 128210215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 128310215Sandreas.hansson@arm.com 128410215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 128510215Sandreas.hansson@arm.com // requestor at its readyTime 128610215Sandreas.hansson@arm.com if (respQueue.empty()) { 128710215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 128810215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 128910215Sandreas.hansson@arm.com } else { 129010215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 129110215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 129210215Sandreas.hansson@arm.com } 129310215Sandreas.hansson@arm.com 129410215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 129510206Sandreas.hansson@arm.com 129610206Sandreas.hansson@arm.com // we have so many writes that we have to transition 129710206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 129810206Sandreas.hansson@arm.com switch_to_writes = true; 129910206Sandreas.hansson@arm.com } 130010206Sandreas.hansson@arm.com } 130110206Sandreas.hansson@arm.com 130210206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 130310206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 130410206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 130510206Sandreas.hansson@arm.com if (switch_to_writes) { 130610206Sandreas.hansson@arm.com // transition to writing 130710206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 130810206Sandreas.hansson@arm.com } 13099352SN/A } else { 131010393Swendy.elsasser@arm.com chooseNext(writeQueue, switched_cmd_type); 131110206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 131210206Sandreas.hansson@arm.com // sanity check 131310206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 131410393Swendy.elsasser@arm.com 131510394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 131610394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 131710394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 131810394Swendy.elsasser@arm.com // applied to colAllowedAt 131910394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 132010394Swendy.elsasser@arm.com busBusyUntil += tRTW; 132110393Swendy.elsasser@arm.com } 132210393Swendy.elsasser@arm.com 132310206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 132410206Sandreas.hansson@arm.com 132510206Sandreas.hansson@arm.com writeQueue.pop_front(); 132610206Sandreas.hansson@arm.com delete dram_pkt; 132710206Sandreas.hansson@arm.com 132810206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 132910206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 133010206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 133110206Sandreas.hansson@arm.com // writes, then switch to reads. 133210206Sandreas.hansson@arm.com if (writeQueue.empty() || 133310206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 133410206Sandreas.hansson@arm.com !drainManager) || 133510206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 133610206Sandreas.hansson@arm.com // turn the bus back around for reads again 133710206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 133810206Sandreas.hansson@arm.com 133910206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 134010206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 134110206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 134210206Sandreas.hansson@arm.com // nothing to do 134310206Sandreas.hansson@arm.com } 134410206Sandreas.hansson@arm.com } 134510206Sandreas.hansson@arm.com 134610206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 134710206Sandreas.hansson@arm.com 134810206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 134910206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 135010206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 135110206Sandreas.hansson@arm.com // the next request processing 135210206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 135310206Sandreas.hansson@arm.com retryWrReq = false; 135410206Sandreas.hansson@arm.com port.sendRetry(); 13559352SN/A } 13569243SN/A} 13579243SN/A 13589967SN/Auint64_t 135910393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 136010393Swendy.elsasser@arm.com bool switched_cmd_type) const 13619967SN/A{ 13629967SN/A uint64_t bank_mask = 0; 136310211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 13649967SN/A 136510393Swendy.elsasser@arm.com uint64_t bank_mask_same_rank = 0; 136610393Swendy.elsasser@arm.com Tick min_act_at_same_rank = MaxTick; 136710393Swendy.elsasser@arm.com 136810393Swendy.elsasser@arm.com // Give precedence to commands that access same rank as previous command 136910393Swendy.elsasser@arm.com bool same_rank_match = false; 137010393Swendy.elsasser@arm.com 137110393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 13729967SN/A // bank in question 13739967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 13749967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 13759967SN/A got_waiting[(*p)->bankId] = true; 13769967SN/A } 13779967SN/A 13789967SN/A for (int i = 0; i < ranksPerChannel; i++) { 13799967SN/A for (int j = 0; j < banksPerRank; j++) { 138010211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 138110211Sandreas.hansson@arm.com 13829967SN/A // if we have waiting requests for the bank, and it is 13839967SN/A // amongst the first available, update the mask 138410211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 138510211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 138610211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 138710393Swendy.elsasser@arm.com // cost in this calculation 138810211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 138910211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 139010211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 139110211Sandreas.hansson@arm.com 139210393Swendy.elsasser@arm.com // prioritize commands that access the 139310393Swendy.elsasser@arm.com // same rank as previous burst 139410393Swendy.elsasser@arm.com // Calculate bank mask separately for the case and 139510393Swendy.elsasser@arm.com // evaluate after loop iterations complete 139610393Swendy.elsasser@arm.com if (i == activeRank && ranksPerChannel > 1) { 139710393Swendy.elsasser@arm.com if (act_at <= min_act_at_same_rank) { 139810393Swendy.elsasser@arm.com // reset same rank bank mask if new minimum is found 139910393Swendy.elsasser@arm.com // and previous minimum could not immediately send ACT 140010393Swendy.elsasser@arm.com if (act_at < min_act_at_same_rank && 140110393Swendy.elsasser@arm.com min_act_at_same_rank > curTick()) 140210393Swendy.elsasser@arm.com bank_mask_same_rank = 0; 140310393Swendy.elsasser@arm.com 140410393Swendy.elsasser@arm.com // Set flag indicating that a same rank 140510393Swendy.elsasser@arm.com // opportunity was found 140610393Swendy.elsasser@arm.com same_rank_match = true; 140710393Swendy.elsasser@arm.com 140810393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 140910393Swendy.elsasser@arm.com replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 141010393Swendy.elsasser@arm.com min_act_at_same_rank = act_at; 141110393Swendy.elsasser@arm.com } 141210393Swendy.elsasser@arm.com } else { 141310393Swendy.elsasser@arm.com if (act_at <= min_act_at) { 141410393Swendy.elsasser@arm.com // reset bank mask if new minimum is found 141510393Swendy.elsasser@arm.com // and either previous minimum could not immediately send ACT 141610393Swendy.elsasser@arm.com if (act_at < min_act_at && min_act_at > curTick()) 141710393Swendy.elsasser@arm.com bank_mask = 0; 141810393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 141910393Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 142010393Swendy.elsasser@arm.com min_act_at = act_at; 142110393Swendy.elsasser@arm.com } 142210211Sandreas.hansson@arm.com } 14239967SN/A } 14249967SN/A } 14259967SN/A } 142610211Sandreas.hansson@arm.com 142710393Swendy.elsasser@arm.com // Determine the earliest time when the next burst can issue based 142810393Swendy.elsasser@arm.com // on the current busBusyUntil delay. 142910393Swendy.elsasser@arm.com // Offset by tRCD to correlate with ACT timing variables 143010393Swendy.elsasser@arm.com Tick min_cmd_at = busBusyUntil - tCL - tRCD; 143110393Swendy.elsasser@arm.com 143210393Swendy.elsasser@arm.com // Prioritize same rank accesses that can issue B2B 143310393Swendy.elsasser@arm.com // Only optimize for same ranks when the command type 143410393Swendy.elsasser@arm.com // does not change; do not want to unnecessarily incur tWTR 143510393Swendy.elsasser@arm.com // 143610393Swendy.elsasser@arm.com // Resulting FCFS prioritization Order is: 143710393Swendy.elsasser@arm.com // 1) Commands that access the same rank as previous burst 143810393Swendy.elsasser@arm.com // and can prep the bank seamlessly. 143910393Swendy.elsasser@arm.com // 2) Commands (any rank) with earliest bank prep 144010393Swendy.elsasser@arm.com if (!switched_cmd_type && same_rank_match && 144110393Swendy.elsasser@arm.com min_act_at_same_rank <= min_cmd_at) { 144210393Swendy.elsasser@arm.com bank_mask = bank_mask_same_rank; 144310393Swendy.elsasser@arm.com } 144410393Swendy.elsasser@arm.com 14459967SN/A return bank_mask; 14469967SN/A} 14479967SN/A 14489243SN/Avoid 144910146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 14509243SN/A{ 145110207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 145210207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 145310207Sandreas.hansson@arm.com // remember when the refresh is due 145410207Sandreas.hansson@arm.com refreshDueAt = curTick(); 14559243SN/A 145610207Sandreas.hansson@arm.com // proceed to drain 145710207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 14589243SN/A 145910207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 146010207Sandreas.hansson@arm.com } 146110207Sandreas.hansson@arm.com 146210207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 146310207Sandreas.hansson@arm.com // hand control back to this event loop 146410207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 146510207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 146610207Sandreas.hansson@arm.com // hand control over to the request loop until it is 146710207Sandreas.hansson@arm.com // evaluated next 146810207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 146910207Sandreas.hansson@arm.com 147010207Sandreas.hansson@arm.com return; 147110207Sandreas.hansson@arm.com } else { 147210207Sandreas.hansson@arm.com refreshState = REF_PRE; 147310207Sandreas.hansson@arm.com } 147410207Sandreas.hansson@arm.com } 147510207Sandreas.hansson@arm.com 147610207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 147710207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 147810208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 147910208Sandreas.hansson@arm.com // state 148010208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 148110214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 148210214Sandreas.hansson@arm.com // only a single bank open 148310208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 148410214Sandreas.hansson@arm.com 148510214Sandreas.hansson@arm.com // first determine when we can precharge 148610214Sandreas.hansson@arm.com Tick pre_at = curTick(); 148710214Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 148810214Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 148910214Sandreas.hansson@arm.com // respect both causality and any existing bank 149010214Sandreas.hansson@arm.com // constraints, some banks could already have a 149110214Sandreas.hansson@arm.com // (auto) precharge scheduled 149210214Sandreas.hansson@arm.com pre_at = std::max(banks[i][j].preAllowedAt, pre_at); 149310214Sandreas.hansson@arm.com } 149410214Sandreas.hansson@arm.com } 149510214Sandreas.hansson@arm.com 149610214Sandreas.hansson@arm.com // make sure all banks are precharged, and for those that 149710214Sandreas.hansson@arm.com // already are, update their availability 149810214Sandreas.hansson@arm.com Tick act_allowed_at = pre_at + tRP; 149910214Sandreas.hansson@arm.com 150010208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 150110208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 150210208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 150310247Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at, false); 150410214Sandreas.hansson@arm.com } else { 150510214Sandreas.hansson@arm.com banks[i][j].actAllowedAt = 150610214Sandreas.hansson@arm.com std::max(banks[i][j].actAllowedAt, act_allowed_at); 150710214Sandreas.hansson@arm.com banks[i][j].preAllowedAt = 150810214Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, pre_at); 150910208Sandreas.hansson@arm.com } 151010207Sandreas.hansson@arm.com } 151110247Sandreas.hansson@arm.com 151210247Sandreas.hansson@arm.com // at the moment this affects all ranks 151310247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", divCeil(pre_at, tCK), 151410247Sandreas.hansson@arm.com i); 151510207Sandreas.hansson@arm.com } 151610208Sandreas.hansson@arm.com } else { 151710208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 151810208Sandreas.hansson@arm.com 151910208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 152010208Sandreas.hansson@arm.com // we are already idle 152110208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 15229975SN/A } 15239975SN/A 152410208Sandreas.hansson@arm.com refreshState = REF_RUN; 152510208Sandreas.hansson@arm.com assert(numBanksActive == 0); 15269243SN/A 152710208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 152810208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 152910208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 153010208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 153110207Sandreas.hansson@arm.com return; 153210207Sandreas.hansson@arm.com } 153310207Sandreas.hansson@arm.com 153410207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 153510207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 153610207Sandreas.hansson@arm.com // should never get here with any banks active 153710207Sandreas.hansson@arm.com assert(numBanksActive == 0); 153810208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 153910207Sandreas.hansson@arm.com 154010211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 154110207Sandreas.hansson@arm.com 154210207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 154310207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 154410211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 154510207Sandreas.hansson@arm.com } 154610247Sandreas.hansson@arm.com 154710247Sandreas.hansson@arm.com // at the moment this affects all ranks 154810247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), tCK), i); 154910207Sandreas.hansson@arm.com } 155010207Sandreas.hansson@arm.com 155110207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 155210207Sandreas.hansson@arm.com // for it 155310211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 155410207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 155510207Sandreas.hansson@arm.com } 155610207Sandreas.hansson@arm.com 155710207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 155810207Sandreas.hansson@arm.com // when scheduling the next one 155910207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 156010207Sandreas.hansson@arm.com 156110208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 156210207Sandreas.hansson@arm.com 156310208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 156410208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 156510208Sandreas.hansson@arm.com // idle state 156610211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 156710207Sandreas.hansson@arm.com 156810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 156910211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 157010208Sandreas.hansson@arm.com } 157110208Sandreas.hansson@arm.com} 157210208Sandreas.hansson@arm.com 157310208Sandreas.hansson@arm.comvoid 157410208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 157510208Sandreas.hansson@arm.com{ 157610208Sandreas.hansson@arm.com // respect causality 157710208Sandreas.hansson@arm.com assert(tick >= curTick()); 157810208Sandreas.hansson@arm.com 157910208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 158010208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 158110208Sandreas.hansson@arm.com tick, pwr_state); 158210208Sandreas.hansson@arm.com 158310208Sandreas.hansson@arm.com // insert the new transition 158410208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 158510208Sandreas.hansson@arm.com 158610208Sandreas.hansson@arm.com schedule(powerEvent, tick); 158710208Sandreas.hansson@arm.com } else { 158810208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 158910208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 159010208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 159110208Sandreas.hansson@arm.com } 159210208Sandreas.hansson@arm.com} 159310208Sandreas.hansson@arm.com 159410208Sandreas.hansson@arm.comvoid 159510208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 159610208Sandreas.hansson@arm.com{ 159710208Sandreas.hansson@arm.com // remember where we were, and for how long 159810208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 159910208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 160010208Sandreas.hansson@arm.com 160110208Sandreas.hansson@arm.com // update the accounting 160210208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 160310208Sandreas.hansson@arm.com 160410208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 160510208Sandreas.hansson@arm.com pwrStateTick = curTick(); 160610208Sandreas.hansson@arm.com 160710208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 160810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 160910208Sandreas.hansson@arm.com 161010208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 161110208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 161210208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 161310208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 161410208Sandreas.hansson@arm.com 161510208Sandreas.hansson@arm.com // kick things into action again 161610208Sandreas.hansson@arm.com refreshState = REF_IDLE; 161710208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 161810208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 161910208Sandreas.hansson@arm.com } else { 162010208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 162110208Sandreas.hansson@arm.com 162210208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 162310208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 162410208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 162510208Sandreas.hansson@arm.com // there should be nothing waiting at this point 162610208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 162710208Sandreas.hansson@arm.com 162810208Sandreas.hansson@arm.com // update the state in zero time and proceed below 162910208Sandreas.hansson@arm.com pwrState = PWR_REF; 163010208Sandreas.hansson@arm.com } 163110208Sandreas.hansson@arm.com } 163210208Sandreas.hansson@arm.com } 163310208Sandreas.hansson@arm.com 163410208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 163510208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 163610208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 163710208Sandreas.hansson@arm.com // following refresh 163810208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 163910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 164010208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 164110208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 164210208Sandreas.hansson@arm.com // state once the refresh is done 164310208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 164410208Sandreas.hansson@arm.com processRefreshEvent(); 164510207Sandreas.hansson@arm.com } 16469243SN/A} 16479243SN/A 16489243SN/Avoid 164910146Sandreas.hansson@arm.comDRAMCtrl::regStats() 16509243SN/A{ 16519243SN/A using namespace Stats; 16529243SN/A 16539243SN/A AbstractMemory::regStats(); 16549243SN/A 16559243SN/A readReqs 16569243SN/A .name(name() + ".readReqs") 16579977SN/A .desc("Number of read requests accepted"); 16589243SN/A 16599243SN/A writeReqs 16609243SN/A .name(name() + ".writeReqs") 16619977SN/A .desc("Number of write requests accepted"); 16629831SN/A 16639831SN/A readBursts 16649831SN/A .name(name() + ".readBursts") 16659977SN/A .desc("Number of DRAM read bursts, " 16669977SN/A "including those serviced by the write queue"); 16679831SN/A 16689831SN/A writeBursts 16699831SN/A .name(name() + ".writeBursts") 16709977SN/A .desc("Number of DRAM write bursts, " 16719977SN/A "including those merged in the write queue"); 16729243SN/A 16739243SN/A servicedByWrQ 16749243SN/A .name(name() + ".servicedByWrQ") 16759977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 16769977SN/A 16779977SN/A mergedWrBursts 16789977SN/A .name(name() + ".mergedWrBursts") 16799977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 16809243SN/A 16819243SN/A neitherReadNorWrite 16829977SN/A .name(name() + ".neitherReadNorWriteReqs") 16839977SN/A .desc("Number of requests that are neither read nor write"); 16849243SN/A 16859977SN/A perBankRdBursts 16869243SN/A .init(banksPerRank * ranksPerChannel) 16879977SN/A .name(name() + ".perBankRdBursts") 16889977SN/A .desc("Per bank write bursts"); 16899243SN/A 16909977SN/A perBankWrBursts 16919243SN/A .init(banksPerRank * ranksPerChannel) 16929977SN/A .name(name() + ".perBankWrBursts") 16939977SN/A .desc("Per bank write bursts"); 16949243SN/A 16959243SN/A avgRdQLen 16969243SN/A .name(name() + ".avgRdQLen") 16979977SN/A .desc("Average read queue length when enqueuing") 16989243SN/A .precision(2); 16999243SN/A 17009243SN/A avgWrQLen 17019243SN/A .name(name() + ".avgWrQLen") 17029977SN/A .desc("Average write queue length when enqueuing") 17039243SN/A .precision(2); 17049243SN/A 17059243SN/A totQLat 17069243SN/A .name(name() + ".totQLat") 17079977SN/A .desc("Total ticks spent queuing"); 17089243SN/A 17099243SN/A totBusLat 17109243SN/A .name(name() + ".totBusLat") 17119977SN/A .desc("Total ticks spent in databus transfers"); 17129243SN/A 17139243SN/A totMemAccLat 17149243SN/A .name(name() + ".totMemAccLat") 17159977SN/A .desc("Total ticks spent from burst creation until serviced " 17169977SN/A "by the DRAM"); 17179243SN/A 17189243SN/A avgQLat 17199243SN/A .name(name() + ".avgQLat") 17209977SN/A .desc("Average queueing delay per DRAM burst") 17219243SN/A .precision(2); 17229243SN/A 17239831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 17249243SN/A 17259243SN/A avgBusLat 17269243SN/A .name(name() + ".avgBusLat") 17279977SN/A .desc("Average bus latency per DRAM burst") 17289243SN/A .precision(2); 17299243SN/A 17309831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 17319243SN/A 17329243SN/A avgMemAccLat 17339243SN/A .name(name() + ".avgMemAccLat") 17349977SN/A .desc("Average memory access latency per DRAM burst") 17359243SN/A .precision(2); 17369243SN/A 17379831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 17389243SN/A 17399243SN/A numRdRetry 17409243SN/A .name(name() + ".numRdRetry") 17419977SN/A .desc("Number of times read queue was full causing retry"); 17429243SN/A 17439243SN/A numWrRetry 17449243SN/A .name(name() + ".numWrRetry") 17459977SN/A .desc("Number of times write queue was full causing retry"); 17469243SN/A 17479243SN/A readRowHits 17489243SN/A .name(name() + ".readRowHits") 17499243SN/A .desc("Number of row buffer hits during reads"); 17509243SN/A 17519243SN/A writeRowHits 17529243SN/A .name(name() + ".writeRowHits") 17539243SN/A .desc("Number of row buffer hits during writes"); 17549243SN/A 17559243SN/A readRowHitRate 17569243SN/A .name(name() + ".readRowHitRate") 17579243SN/A .desc("Row buffer hit rate for reads") 17589243SN/A .precision(2); 17599243SN/A 17609831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 17619243SN/A 17629243SN/A writeRowHitRate 17639243SN/A .name(name() + ".writeRowHitRate") 17649243SN/A .desc("Row buffer hit rate for writes") 17659243SN/A .precision(2); 17669243SN/A 17679977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 17689243SN/A 17699243SN/A readPktSize 17709831SN/A .init(ceilLog2(burstSize) + 1) 17719243SN/A .name(name() + ".readPktSize") 17729977SN/A .desc("Read request sizes (log2)"); 17739243SN/A 17749243SN/A writePktSize 17759831SN/A .init(ceilLog2(burstSize) + 1) 17769243SN/A .name(name() + ".writePktSize") 17779977SN/A .desc("Write request sizes (log2)"); 17789243SN/A 17799243SN/A rdQLenPdf 17809567SN/A .init(readBufferSize) 17819243SN/A .name(name() + ".rdQLenPdf") 17829243SN/A .desc("What read queue length does an incoming req see"); 17839243SN/A 17849243SN/A wrQLenPdf 17859567SN/A .init(writeBufferSize) 17869243SN/A .name(name() + ".wrQLenPdf") 17879243SN/A .desc("What write queue length does an incoming req see"); 17889243SN/A 17899727SN/A bytesPerActivate 179010141SN/A .init(maxAccessesPerRow) 17919727SN/A .name(name() + ".bytesPerActivate") 17929727SN/A .desc("Bytes accessed per row activation") 17939727SN/A .flags(nozero); 17949243SN/A 179510147Sandreas.hansson@arm.com rdPerTurnAround 179610147Sandreas.hansson@arm.com .init(readBufferSize) 179710147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 179810147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 179910147Sandreas.hansson@arm.com .flags(nozero); 180010147Sandreas.hansson@arm.com 180110147Sandreas.hansson@arm.com wrPerTurnAround 180210147Sandreas.hansson@arm.com .init(writeBufferSize) 180310147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 180410147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 180510147Sandreas.hansson@arm.com .flags(nozero); 180610147Sandreas.hansson@arm.com 18079975SN/A bytesReadDRAM 18089975SN/A .name(name() + ".bytesReadDRAM") 18099975SN/A .desc("Total number of bytes read from DRAM"); 18109975SN/A 18119975SN/A bytesReadWrQ 18129975SN/A .name(name() + ".bytesReadWrQ") 18139975SN/A .desc("Total number of bytes read from write queue"); 18149243SN/A 18159243SN/A bytesWritten 18169243SN/A .name(name() + ".bytesWritten") 18179977SN/A .desc("Total number of bytes written to DRAM"); 18189243SN/A 18199977SN/A bytesReadSys 18209977SN/A .name(name() + ".bytesReadSys") 18219977SN/A .desc("Total read bytes from the system interface side"); 18229243SN/A 18239977SN/A bytesWrittenSys 18249977SN/A .name(name() + ".bytesWrittenSys") 18259977SN/A .desc("Total written bytes from the system interface side"); 18269243SN/A 18279243SN/A avgRdBW 18289243SN/A .name(name() + ".avgRdBW") 18299977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 18309243SN/A .precision(2); 18319243SN/A 18329977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 18339243SN/A 18349243SN/A avgWrBW 18359243SN/A .name(name() + ".avgWrBW") 18369977SN/A .desc("Average achieved write bandwidth in MiByte/s") 18379243SN/A .precision(2); 18389243SN/A 18399243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 18409243SN/A 18419977SN/A avgRdBWSys 18429977SN/A .name(name() + ".avgRdBWSys") 18439977SN/A .desc("Average system read bandwidth in MiByte/s") 18449243SN/A .precision(2); 18459243SN/A 18469977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 18479243SN/A 18489977SN/A avgWrBWSys 18499977SN/A .name(name() + ".avgWrBWSys") 18509977SN/A .desc("Average system write bandwidth in MiByte/s") 18519243SN/A .precision(2); 18529243SN/A 18539977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 18549243SN/A 18559243SN/A peakBW 18569243SN/A .name(name() + ".peakBW") 18579977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 18589243SN/A .precision(2); 18599243SN/A 18609831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 18619243SN/A 18629243SN/A busUtil 18639243SN/A .name(name() + ".busUtil") 18649243SN/A .desc("Data bus utilization in percentage") 18659243SN/A .precision(2); 18669243SN/A 18679243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 18689243SN/A 18699243SN/A totGap 18709243SN/A .name(name() + ".totGap") 18719243SN/A .desc("Total gap between requests"); 18729243SN/A 18739243SN/A avgGap 18749243SN/A .name(name() + ".avgGap") 18759243SN/A .desc("Average gap between requests") 18769243SN/A .precision(2); 18779243SN/A 18789243SN/A avgGap = totGap / (readReqs + writeReqs); 18799975SN/A 18809975SN/A // Stats for DRAM Power calculation based on Micron datasheet 18819975SN/A busUtilRead 18829975SN/A .name(name() + ".busUtilRead") 18839975SN/A .desc("Data bus utilization in percentage for reads") 18849975SN/A .precision(2); 18859975SN/A 18869975SN/A busUtilRead = avgRdBW / peakBW * 100; 18879975SN/A 18889975SN/A busUtilWrite 18899975SN/A .name(name() + ".busUtilWrite") 18909975SN/A .desc("Data bus utilization in percentage for writes") 18919975SN/A .precision(2); 18929975SN/A 18939975SN/A busUtilWrite = avgWrBW / peakBW * 100; 18949975SN/A 18959975SN/A pageHitRate 18969975SN/A .name(name() + ".pageHitRate") 18979975SN/A .desc("Row buffer hit rate, read and write combined") 18989975SN/A .precision(2); 18999975SN/A 19009977SN/A pageHitRate = (writeRowHits + readRowHits) / 19019977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 19029975SN/A 190310208Sandreas.hansson@arm.com pwrStateTime 190410208Sandreas.hansson@arm.com .init(5) 190510208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 190610208Sandreas.hansson@arm.com .desc("Time in different power states"); 190710208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 190810208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 190910208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 191010208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 191110208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 19129243SN/A} 19139243SN/A 19149243SN/Avoid 191510146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 19169243SN/A{ 19179243SN/A // rely on the abstract memory 19189243SN/A functionalAccess(pkt); 19199243SN/A} 19209243SN/A 19219294SN/ABaseSlavePort& 192210146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 19239243SN/A{ 19249243SN/A if (if_name != "port") { 19259243SN/A return MemObject::getSlavePort(if_name, idx); 19269243SN/A } else { 19279243SN/A return port; 19289243SN/A } 19299243SN/A} 19309243SN/A 19319243SN/Aunsigned int 193210146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 19339243SN/A{ 19349342SN/A unsigned int count = port.drain(dm); 19359243SN/A 19369243SN/A // if there is anything in any of our internal queues, keep track 19379243SN/A // of that as well 19389567SN/A if (!(writeQueue.empty() && readQueue.empty() && 19399567SN/A respQueue.empty())) { 19409352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 19419567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 19429567SN/A respQueue.size()); 19439243SN/A ++count; 19449342SN/A drainManager = dm; 194510206Sandreas.hansson@arm.com 19469352SN/A // the only part that is not drained automatically over time 194710206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 194810206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 194910206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 195010206Sandreas.hansson@arm.com } 19519243SN/A } 19529243SN/A 19539243SN/A if (count) 19549342SN/A setDrainState(Drainable::Draining); 19559243SN/A else 19569342SN/A setDrainState(Drainable::Drained); 19579243SN/A return count; 19589243SN/A} 19599243SN/A 196010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 19619243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 19629243SN/A memory(_memory) 19639243SN/A{ } 19649243SN/A 19659243SN/AAddrRangeList 196610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 19679243SN/A{ 19689243SN/A AddrRangeList ranges; 19699243SN/A ranges.push_back(memory.getAddrRange()); 19709243SN/A return ranges; 19719243SN/A} 19729243SN/A 19739243SN/Avoid 197410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 19759243SN/A{ 19769243SN/A pkt->pushLabel(memory.name()); 19779243SN/A 19789243SN/A if (!queue.checkFunctional(pkt)) { 19799243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 19809243SN/A // calls recvAtomic() and throws away the latency; we can save a 19819243SN/A // little here by just not calculating the latency. 19829243SN/A memory.recvFunctional(pkt); 19839243SN/A } 19849243SN/A 19859243SN/A pkt->popLabel(); 19869243SN/A} 19879243SN/A 19889243SN/ATick 198910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 19909243SN/A{ 19919243SN/A return memory.recvAtomic(pkt); 19929243SN/A} 19939243SN/A 19949243SN/Abool 199510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 19969243SN/A{ 19979243SN/A // pass it to the memory controller 19989243SN/A return memory.recvTimingReq(pkt); 19999243SN/A} 20009243SN/A 200110146Sandreas.hansson@arm.comDRAMCtrl* 200210146Sandreas.hansson@arm.comDRAMCtrlParams::create() 20039243SN/A{ 200410146Sandreas.hansson@arm.com return new DRAMCtrl(this); 20059243SN/A} 2006