coherent_xbar.hh revision 9712
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Ali Saidi 42 * Andreas Hansson 43 * William Wang 44 */ 45 46/** 47 * @file 48 * Declaration of a coherent bus. 49 */ 50 51#ifndef __MEM_COHERENT_BUS_HH__ 52#define __MEM_COHERENT_BUS_HH__ 53 54#include "base/hashmap.hh" 55#include "mem/bus.hh" 56#include "params/CoherentBus.hh" 57 58/** 59 * A coherent bus connects a number of (potentially) snooping masters 60 * and slaves, and routes the request and response packets based on 61 * the address, and also forwards all requests to the snoopers and 62 * deals with the snoop responses. 63 * 64 * The coherent bus can be used as a template for modelling QPI, 65* HyperTransport, ACE and coherent OCP buses, and is typically used 66 * for the L1-to-L2 buses and as the main system interconnect. 67 * @sa \ref gem5MemorySystem "gem5 Memory System" 68 */ 69class CoherentBus : public BaseBus 70{ 71 72 protected: 73 74 /** 75 * Declare the three layers of this bus, one for requests, one 76 * for responses, and one for snoop responses 77 */ 78 Layer<SlavePort> reqLayer; 79 Layer<MasterPort> respLayer; 80 Layer<SlavePort> snoopRespLayer; 81 82 /** 83 * Declaration of the coherent bus slave port type, one will be 84 * instantiated for each of the master ports connecting to the 85 * bus. 86 */ 87 class CoherentBusSlavePort : public SlavePort 88 { 89 90 private: 91 92 /** A reference to the bus to which this port belongs. */ 93 CoherentBus &bus; 94 95 public: 96 97 CoherentBusSlavePort(const std::string &_name, 98 CoherentBus &_bus, PortID _id) 99 : SlavePort(_name, &_bus, _id), bus(_bus) 100 { } 101 102 protected: 103 104 /** 105 * When receiving a timing request, pass it to the bus. 106 */ 107 virtual bool recvTimingReq(PacketPtr pkt) 108 { return bus.recvTimingReq(pkt, id); } 109 110 /** 111 * When receiving a timing snoop response, pass it to the bus. 112 */ 113 virtual bool recvTimingSnoopResp(PacketPtr pkt) 114 { return bus.recvTimingSnoopResp(pkt, id); } 115 116 /** 117 * When receiving an atomic request, pass it to the bus. 118 */ 119 virtual Tick recvAtomic(PacketPtr pkt) 120 { return bus.recvAtomic(pkt, id); } 121 122 /** 123 * When receiving a functional request, pass it to the bus. 124 */ 125 virtual void recvFunctional(PacketPtr pkt) 126 { bus.recvFunctional(pkt, id); } 127 128 /** 129 * When receiving a retry, pass it to the bus. 130 */ 131 virtual void recvRetry() 132 { panic("Bus slave ports always succeed and should never retry.\n"); } 133 134 /** 135 * Return the union of all adress ranges seen by this bus. 136 */ 137 virtual AddrRangeList getAddrRanges() const 138 { return bus.getAddrRanges(); } 139 140 /** 141 * Get the maximum block size as seen by the bus. 142 */ 143 virtual unsigned deviceBlockSize() const 144 { return bus.deviceBlockSize(); } 145 146 }; 147 148 /** 149 * Declaration of the coherent bus master port type, one will be 150 * instantiated for each of the slave interfaces connecting to the 151 * bus. 152 */ 153 class CoherentBusMasterPort : public MasterPort 154 { 155 private: 156 /** A reference to the bus to which this port belongs. */ 157 CoherentBus &bus; 158 159 public: 160 161 CoherentBusMasterPort(const std::string &_name, 162 CoherentBus &_bus, PortID _id) 163 : MasterPort(_name, &_bus, _id), bus(_bus) 164 { } 165 166 protected: 167 168 /** 169 * Determine if this port should be considered a snooper. For 170 * a coherent bus master port this is always true. 171 * 172 * @return a boolean that is true if this port is snooping 173 */ 174 virtual bool isSnooping() const 175 { return true; } 176 177 /** 178 * When receiving a timing response, pass it to the bus. 179 */ 180 virtual bool recvTimingResp(PacketPtr pkt) 181 { return bus.recvTimingResp(pkt, id); } 182 183 /** 184 * When receiving a timing snoop request, pass it to the bus. 185 */ 186 virtual void recvTimingSnoopReq(PacketPtr pkt) 187 { return bus.recvTimingSnoopReq(pkt, id); } 188 189 /** 190 * When receiving an atomic snoop request, pass it to the bus. 191 */ 192 virtual Tick recvAtomicSnoop(PacketPtr pkt) 193 { return bus.recvAtomicSnoop(pkt, id); } 194 195 /** 196 * When receiving a functional snoop request, pass it to the bus. 197 */ 198 virtual void recvFunctionalSnoop(PacketPtr pkt) 199 { bus.recvFunctionalSnoop(pkt, id); } 200 201 /** When reciving a range change from the peer port (at id), 202 pass it to the bus. */ 203 virtual void recvRangeChange() 204 { bus.recvRangeChange(id); } 205 206 /** When reciving a retry from the peer port (at id), 207 pass it to the bus. */ 208 virtual void recvRetry() 209 { bus.recvRetry(id); } 210 211 // Ask the bus to ask everyone on the bus what their block size is and 212 // take the max of it. This might need to be changed a bit if we ever 213 // support multiple block sizes. 214 virtual unsigned deviceBlockSize() const 215 { return bus.deviceBlockSize(); } 216 217 }; 218 219 std::vector<SlavePort*> snoopPorts; 220 221 /** 222 * Store the outstanding requests so we can determine which ones 223 * we generated and which ones were merely forwarded. This is used 224 * in the coherent bus when coherency responses come back. 225 */ 226 m5::hash_set<RequestPtr> outstandingReq; 227 228 /** 229 * Keep a pointer to the system to be allow to querying memory system 230 * properties. 231 */ 232 System *system; 233 234 /** Function called by the port when the bus is recieving a Timing 235 request packet.*/ 236 virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id); 237 238 /** Function called by the port when the bus is recieving a Timing 239 response packet.*/ 240 virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id); 241 242 /** Function called by the port when the bus is recieving a timing 243 snoop request.*/ 244 virtual void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id); 245 246 /** Function called by the port when the bus is recieving a timing 247 snoop response.*/ 248 virtual bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id); 249 250 /** Timing function called by port when it is once again able to process 251 * requests. */ 252 void recvRetry(PortID master_port_id); 253 254 /** 255 * Forward a timing packet to our snoopers, potentially excluding 256 * one of the connected coherent masters to avoid sending a packet 257 * back to where it came from. 258 * 259 * @param pkt Packet to forward 260 * @param exclude_slave_port_id Id of slave port to exclude 261 */ 262 void forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id); 263 264 /** Function called by the port when the bus is recieving a Atomic 265 transaction.*/ 266 Tick recvAtomic(PacketPtr pkt, PortID slave_port_id); 267 268 /** Function called by the port when the bus is recieving an 269 atomic snoop transaction.*/ 270 Tick recvAtomicSnoop(PacketPtr pkt, PortID master_port_id); 271 272 /** 273 * Forward an atomic packet to our snoopers, potentially excluding 274 * one of the connected coherent masters to avoid sending a packet 275 * back to where it came from. 276 * 277 * @param pkt Packet to forward 278 * @param exclude_slave_port_id Id of slave port to exclude 279 * 280 * @return a pair containing the snoop response and snoop latency 281 */ 282 std::pair<MemCmd, Tick> forwardAtomic(PacketPtr pkt, 283 PortID exclude_slave_port_id); 284 285 /** Function called by the port when the bus is recieving a Functional 286 transaction.*/ 287 void recvFunctional(PacketPtr pkt, PortID slave_port_id); 288 289 /** Function called by the port when the bus is recieving a functional 290 snoop transaction.*/ 291 void recvFunctionalSnoop(PacketPtr pkt, PortID master_port_id); 292 293 /** 294 * Forward a functional packet to our snoopers, potentially 295 * excluding one of the connected coherent masters to avoid 296 * sending a packet back to where it came from. 297 * 298 * @param pkt Packet to forward 299 * @param exclude_slave_port_id Id of slave port to exclude 300 */ 301 void forwardFunctional(PacketPtr pkt, PortID exclude_slave_port_id); 302 303 Stats::Scalar dataThroughBus; 304 Stats::Scalar snoopDataThroughBus; 305 306 public: 307 308 virtual void init(); 309 310 CoherentBus(const CoherentBusParams *p); 311 312 unsigned int drain(DrainManager *dm); 313 314 virtual void regStats(); 315}; 316 317#endif //__MEM_COHERENT_BUS_HH__ 318