write_queue_entry.cc revision 12823
111375Sandreas.hansson@arm.com/* 212345Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2017 ARM Limited 311375Sandreas.hansson@arm.com * All rights reserved. 411375Sandreas.hansson@arm.com * 511375Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611375Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711375Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811375Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911375Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011375Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111375Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211375Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311375Sandreas.hansson@arm.com * 1411375Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511375Sandreas.hansson@arm.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 1611375Sandreas.hansson@arm.com * All rights reserved. 1711375Sandreas.hansson@arm.com * 1811375Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 1911375Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 2011375Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 2111375Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 2211375Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 2311375Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 2411375Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 2511375Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 2611375Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 2711375Sandreas.hansson@arm.com * this software without specific prior written permission. 2811375Sandreas.hansson@arm.com * 2911375Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011375Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111375Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211375Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311375Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411375Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511375Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611375Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711375Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811375Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911375Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011375Sandreas.hansson@arm.com * 4111375Sandreas.hansson@arm.com * Authors: Erik Hallnor 4211375Sandreas.hansson@arm.com * Dave Greene 4311375Sandreas.hansson@arm.com * Andreas Hansson 4411375Sandreas.hansson@arm.com */ 4511375Sandreas.hansson@arm.com 4611375Sandreas.hansson@arm.com/** 4711375Sandreas.hansson@arm.com * @file 4811375Sandreas.hansson@arm.com * Miss Status and Handling Register (WriteQueueEntry) definitions. 4911375Sandreas.hansson@arm.com */ 5011375Sandreas.hansson@arm.com 5111375Sandreas.hansson@arm.com#include "mem/cache/write_queue_entry.hh" 5211375Sandreas.hansson@arm.com 5311375Sandreas.hansson@arm.com#include <cassert> 5411375Sandreas.hansson@arm.com#include <string> 5511375Sandreas.hansson@arm.com 5612334Sgabeblack@google.com#include "base/logging.hh" 5711375Sandreas.hansson@arm.com#include "base/types.hh" 5812727Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 5912727Snikos.nikoleris@arm.com#include "mem/request.hh" 6011375Sandreas.hansson@arm.com 6111375Sandreas.hansson@arm.cominline void 6211375Sandreas.hansson@arm.comWriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime, 6311375Sandreas.hansson@arm.com Counter order) 6411375Sandreas.hansson@arm.com{ 6511375Sandreas.hansson@arm.com emplace_back(pkt, readyTime, order); 6611375Sandreas.hansson@arm.com} 6711375Sandreas.hansson@arm.com 6811375Sandreas.hansson@arm.combool 6912823Srmk35@cl.cam.ac.ukWriteQueueEntry::TargetList::trySatisfyFunctional(PacketPtr pkt) 7011375Sandreas.hansson@arm.com{ 7111375Sandreas.hansson@arm.com for (auto& t : *this) { 7212823Srmk35@cl.cam.ac.uk if (pkt->trySatisfyFunctional(t.pkt)) { 7311375Sandreas.hansson@arm.com return true; 7411375Sandreas.hansson@arm.com } 7511375Sandreas.hansson@arm.com } 7611375Sandreas.hansson@arm.com 7711375Sandreas.hansson@arm.com return false; 7811375Sandreas.hansson@arm.com} 7911375Sandreas.hansson@arm.com 8011375Sandreas.hansson@arm.comvoid 8111375Sandreas.hansson@arm.comWriteQueueEntry::TargetList::print(std::ostream &os, int verbosity, 8211375Sandreas.hansson@arm.com const std::string &prefix) const 8311375Sandreas.hansson@arm.com{ 8411375Sandreas.hansson@arm.com for (auto& t : *this) { 8511375Sandreas.hansson@arm.com ccprintf(os, "%sFromCPU: ", prefix); 8611375Sandreas.hansson@arm.com t.pkt->print(os, verbosity, ""); 8711375Sandreas.hansson@arm.com } 8811375Sandreas.hansson@arm.com} 8911375Sandreas.hansson@arm.com 9011375Sandreas.hansson@arm.comvoid 9111375Sandreas.hansson@arm.comWriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, 9211375Sandreas.hansson@arm.com Tick when_ready, Counter _order) 9311375Sandreas.hansson@arm.com{ 9411375Sandreas.hansson@arm.com blkAddr = blk_addr; 9511375Sandreas.hansson@arm.com blkSize = blk_size; 9611375Sandreas.hansson@arm.com isSecure = target->isSecure(); 9711375Sandreas.hansson@arm.com readyTime = when_ready; 9811375Sandreas.hansson@arm.com order = _order; 9911375Sandreas.hansson@arm.com assert(target); 10011375Sandreas.hansson@arm.com _isUncacheable = target->req->isUncacheable(); 10111375Sandreas.hansson@arm.com inService = false; 10211375Sandreas.hansson@arm.com 10311375Sandreas.hansson@arm.com // we should never have more than a single target for cacheable 10411375Sandreas.hansson@arm.com // writes (writebacks and clean evictions) 10511375Sandreas.hansson@arm.com panic_if(!_isUncacheable && !targets.empty(), 10611375Sandreas.hansson@arm.com "Write queue entry %#llx should never have more than one " 10711375Sandreas.hansson@arm.com "cacheable target", blkAddr); 10811375Sandreas.hansson@arm.com panic_if(!((target->isWrite() && _isUncacheable) || 10912345Snikos.nikoleris@arm.com (target->isEviction() && !_isUncacheable) || 11012345Snikos.nikoleris@arm.com target->cmd == MemCmd::WriteClean), 11112345Snikos.nikoleris@arm.com "Write queue entry %#llx should be an uncacheable write or " 11212345Snikos.nikoleris@arm.com "a cacheable eviction or a writeclean"); 11311375Sandreas.hansson@arm.com 11411375Sandreas.hansson@arm.com targets.add(target, when_ready, _order); 11511375Sandreas.hansson@arm.com} 11611375Sandreas.hansson@arm.com 11711375Sandreas.hansson@arm.comvoid 11811375Sandreas.hansson@arm.comWriteQueueEntry::deallocate() 11911375Sandreas.hansson@arm.com{ 12011375Sandreas.hansson@arm.com assert(targets.empty()); 12111375Sandreas.hansson@arm.com inService = false; 12211375Sandreas.hansson@arm.com} 12311375Sandreas.hansson@arm.com 12411375Sandreas.hansson@arm.combool 12512823Srmk35@cl.cam.ac.ukWriteQueueEntry::trySatisfyFunctional(PacketPtr pkt) 12611375Sandreas.hansson@arm.com{ 12711375Sandreas.hansson@arm.com // For printing, we treat the WriteQueueEntry as a whole as single 12811375Sandreas.hansson@arm.com // entity. For other requests, we iterate over the individual 12911375Sandreas.hansson@arm.com // targets since that's where the actual data lies. 13011375Sandreas.hansson@arm.com if (pkt->isPrint()) { 13112823Srmk35@cl.cam.ac.uk pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr); 13211375Sandreas.hansson@arm.com return false; 13311375Sandreas.hansson@arm.com } else { 13412823Srmk35@cl.cam.ac.uk return targets.trySatisfyFunctional(pkt); 13511375Sandreas.hansson@arm.com } 13611375Sandreas.hansson@arm.com} 13711375Sandreas.hansson@arm.com 13811375Sandreas.hansson@arm.combool 13912724Snikos.nikoleris@arm.comWriteQueueEntry::sendPacket(BaseCache &cache) 14011375Sandreas.hansson@arm.com{ 14111375Sandreas.hansson@arm.com return cache.sendWriteQueuePacket(this); 14211375Sandreas.hansson@arm.com} 14311375Sandreas.hansson@arm.com 14411375Sandreas.hansson@arm.comvoid 14511375Sandreas.hansson@arm.comWriteQueueEntry::print(std::ostream &os, int verbosity, 14611375Sandreas.hansson@arm.com const std::string &prefix) const 14711375Sandreas.hansson@arm.com{ 14811375Sandreas.hansson@arm.com ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n", 14911375Sandreas.hansson@arm.com prefix, blkAddr, blkAddr + blkSize - 1, 15011375Sandreas.hansson@arm.com isSecure ? "s" : "ns", 15111375Sandreas.hansson@arm.com _isUncacheable ? "Unc" : "", 15211375Sandreas.hansson@arm.com inService ? "InSvc" : ""); 15311375Sandreas.hansson@arm.com 15411375Sandreas.hansson@arm.com ccprintf(os, "%s Targets:\n", prefix); 15511375Sandreas.hansson@arm.com targets.print(os, verbosity, prefix + " "); 15611375Sandreas.hansson@arm.com} 15711375Sandreas.hansson@arm.com 15811375Sandreas.hansson@arm.comstd::string 15911375Sandreas.hansson@arm.comWriteQueueEntry::print() const 16011375Sandreas.hansson@arm.com{ 16112637Sodanrc@yahoo.com.br std::ostringstream str; 16211375Sandreas.hansson@arm.com print(str); 16311375Sandreas.hansson@arm.com return str.str(); 16411375Sandreas.hansson@arm.com} 165