write_queue.hh revision 11375:f98df9231cdd 
1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
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20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40/**
41 * @file Declaration of a queue structure to manage uncacheable write
42 * and writebacks.
43 */
44
45#ifndef __MEM_CACHE_WRITE_QUEUE_HH__
46#define __MEM_CACHE_WRITE_QUEUE_HH__
47
48#include <vector>
49
50#include "mem/cache/queue.hh"
51#include "mem/cache/write_queue_entry.hh"
52
53/**
54 * A write queue for all eviction packets, i.e. writebacks and clean
55 * evictions, as well as uncacheable writes.
56 */
57class WriteQueue : public Queue<WriteQueueEntry>
58{
59
60  public:
61
62    /**
63     * Create a write queue with a given number of entries.
64     * @param num_entries The number of entries in this queue.
65     * @param reserve The maximum number of entries needed to satisfy
66     *        any access.
67     */
68    WriteQueue(const std::string &_label, int num_entries, int reserve);
69
70    /**
71     * Allocates a new WriteQueueEntry for the request and size. This
72     * places the request as the first target in the WriteQueueEntry.
73     *
74     * @param blk_addr The address of the block.
75     * @param blk_size The number of bytes to request.
76     * @param pkt The original write.
77     * @param when_ready When is the WriteQueueEntry be ready to act upon.
78     * @param order The logical order of this WriteQueueEntry
79     *
80     * @return The a pointer to the WriteQueueEntry allocated.
81     *
82     * @pre There are free entries.
83     */
84    WriteQueueEntry *allocate(Addr blk_addr, unsigned blk_size,
85                              PacketPtr pkt, Tick when_ready, Counter order);
86
87    /**
88     * Mark the given entry as in service. This removes the entry from
89     * the readyList or deallocates the entry if it does not expect a
90     * response (writeback/eviction rather than an uncacheable write).
91     *
92     * @param entry The entry to mark in service.
93     */
94    void markInService(WriteQueueEntry *entry);
95};
96
97#endif //__MEM_CACHE_WRITE_QUEUE_HH__
98